94 lines · c
1/* SPDX-License-Identifier: MIT */2 3#ifndef __AST_REG_H__4#define __AST_REG_H__5 6#include <linux/bits.h>7 8/*9 * Modesetting10 */11 12#define AST_IO_MM_OFFSET (0x380)13#define AST_IO_MM_LENGTH (128)14 15#define AST_IO_VGAARI_W (0x40)16 17#define AST_IO_VGAMR_W (0x42)18#define AST_IO_VGAMR_R (0x4c)19#define AST_IO_VGAMR_IOSEL BIT(0)20 21#define AST_IO_VGAER (0x43)22#define AST_IO_VGAER_VGA_ENABLE BIT(0)23 24#define AST_IO_VGASRI (0x44)25#define AST_IO_VGASR1_SD BIT(5)26#define AST_IO_VGADRR (0x47)27#define AST_IO_VGADWR (0x48)28#define AST_IO_VGAPDR (0x49)29#define AST_IO_VGAGRI (0x4E)30 31#define AST_IO_VGACRI (0x54)32#define AST_IO_VGACR80_PASSWORD (0xa8)33#define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1)34#define AST_IO_VGACRA1_MMIO_ENABLED BIT(2)35#define AST_IO_VGACRB6_HSYNC_OFF BIT(0)36#define AST_IO_VGACRB6_VSYNC_OFF BIT(1)37#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */38#define AST_IO_VGACRCB_HWC_ENABLED BIT(1)39 40#define AST_IO_VGACRD1_MCU_FW_EXECUTING BIT(5)41#define AST_IO_VGACRD7_EDID_VALID_FLAG BIT(0)42#define AST_IO_VGACRDC_LINK_SUCCESS BIT(0)43#define AST_IO_VGACRDF_HPD BIT(0)44#define AST_IO_VGACRE5_EDID_READ_DONE BIT(0)45 46#define AST_IO_VGAIR1_R (0x5A)47#define AST_IO_VGAIR1_VREFRESH BIT(3)48 49/*50 * Display Transmitter Type51 */52 53#define TX_TYPE_MASK GENMASK(3, 1)54#define NO_TX (0 << 1)55#define ITE66121_VBIOS_TX (1 << 1)56#define SI164_VBIOS_TX (2 << 1)57#define CH7003_VBIOS_TX (3 << 1)58#define DP501_VBIOS_TX (4 << 1)59#define ANX9807_VBIOS_TX (5 << 1)60#define TX_FW_EMBEDDED_FW_TX (6 << 1)61#define ASTDP_DPMCU_TX (7 << 1)62 63#define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6)64//#define AST_VRAM_INIT_BY_BMC BIT(7)65//#define AST_VRAM_INIT_READY BIT(6)66 67/*68 * AST DisplayPort69 */70 71/* Define for Soc scratched reg used on ASTDP */72#define AST_DP_PHY_SLEEP BIT(4)73#define AST_DP_VIDEO_ENABLE BIT(0)74 75/*76 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE77 * Precondition: A. ~AST_DP_PHY_SLEEP &&78 * B. DP_HPD &&79 * C. DP_LINK_SUCCESS80 */81#define ASTDP_MIRROR_VIDEO_ENABLE BIT(4)82 83/*84 * ASTDP setmode registers:85 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)86 * CRE1[7:0]: MISC1 (default: 0x00)87 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)88 */89#define ASTDP_MISC0_24bpp BIT(5)90#define ASTDP_MISC1 091#define ASTDP_AND_CLEAR_MASK 0x0092 93#endif94