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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Analog Devices ADV7511 HDMI transmitter driver4 *5 * Copyright 2012 Analog Devices Inc.6 */7 8#ifndef __DRM_I2C_ADV7511_H__9#define __DRM_I2C_ADV7511_H__10 11#include <linux/hdmi.h>12#include <linux/i2c.h>13#include <linux/regmap.h>14#include <linux/regulator/consumer.h>15 16#include <drm/drm_bridge.h>17#include <drm/drm_connector.h>18#include <drm/drm_mipi_dsi.h>19#include <drm/drm_modes.h>20 21#define ADV7511_REG_CHIP_REVISION 0x0022#define ADV7511_REG_N0 0x0123#define ADV7511_REG_N1 0x0224#define ADV7511_REG_N2 0x0325#define ADV7511_REG_SPDIF_FREQ 0x0426#define ADV7511_REG_CTS_AUTOMATIC1 0x0527#define ADV7511_REG_CTS_AUTOMATIC2 0x0628#define ADV7511_REG_CTS_MANUAL0 0x0729#define ADV7511_REG_CTS_MANUAL1 0x0830#define ADV7511_REG_CTS_MANUAL2 0x0931#define ADV7511_REG_AUDIO_SOURCE 0x0a32#define ADV7511_REG_AUDIO_CONFIG 0x0b33#define ADV7511_REG_I2S_CONFIG 0x0c34#define ADV7511_REG_I2S_WIDTH 0x0d35#define ADV7511_REG_AUDIO_SUB_SRC0 0x0e36#define ADV7511_REG_AUDIO_SUB_SRC1 0x0f37#define ADV7511_REG_AUDIO_SUB_SRC2 0x1038#define ADV7511_REG_AUDIO_SUB_SRC3 0x1139#define ADV7511_REG_AUDIO_CFG1 0x1240#define ADV7511_REG_AUDIO_CFG2 0x1341#define ADV7511_REG_AUDIO_CFG3 0x1442#define ADV7511_REG_I2C_FREQ_ID_CFG 0x1543#define ADV7511_REG_VIDEO_INPUT_CFG1 0x1644#define ADV7511_REG_CSC_UPPER(x) (0x18 + (x) * 2)45#define ADV7511_REG_CSC_LOWER(x) (0x19 + (x) * 2)46#define ADV7511_REG_SYNC_DECODER(x) (0x30 + (x))47#define ADV7511_REG_DE_GENERATOR (0x35 + (x))48#define ADV7511_REG_PIXEL_REPETITION 0x3b49#define ADV7511_REG_VIC_MANUAL 0x3c50#define ADV7511_REG_VIC_SEND 0x3d51#define ADV7511_REG_VIC_DETECTED 0x3e52#define ADV7511_REG_AUX_VIC_DETECTED 0x3f53#define ADV7511_REG_PACKET_ENABLE0 0x4054#define ADV7511_REG_POWER 0x4155#define ADV7511_REG_STATUS 0x4256#define ADV7511_REG_EDID_I2C_ADDR 0x4357#define ADV7511_REG_PACKET_ENABLE1 0x4458#define ADV7511_REG_PACKET_I2C_ADDR 0x4559#define ADV7511_REG_DSD_ENABLE 0x4660#define ADV7511_REG_VIDEO_INPUT_CFG2 0x4861#define ADV7511_REG_INFOFRAME_UPDATE 0x4a62#define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */63#define ADV7511_REG_AVI_INFOFRAME_VERSION 0x5264#define ADV7511_REG_AVI_INFOFRAME_LENGTH 0x5365#define ADV7511_REG_AVI_INFOFRAME_CHECKSUM 0x5466#define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */67#define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x7068#define ADV7511_REG_AUDIO_INFOFRAME_LENGTH 0x7169#define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM 0x7270#define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */71#define ADV7511_REG_INT_ENABLE(x) (0x94 + (x))72#define ADV7511_REG_INT(x) (0x96 + (x))73#define ADV7511_REG_INPUT_CLK_DIV 0x9d74#define ADV7511_REG_PLL_STATUS 0x9e75#define ADV7511_REG_HDMI_POWER 0xa176#define ADV7511_REG_HDCP_HDMI_CFG 0xaf77#define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */78#define ADV7511_REG_HDCP_STATUS 0xb879#define ADV7511_REG_BCAPS 0xbe80#define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */81#define ADV7511_REG_EDID_SEGMENT 0xc482#define ADV7511_REG_DDC_STATUS 0xc883#define ADV7511_REG_EDID_READ_CTRL 0xc984#define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */85#define ADV7511_REG_TIMING_GEN_SEQ 0xd086#define ADV7511_REG_POWER2 0xd687#define ADV7511_REG_HSYNC_PLACEMENT_MSB 0xfa88 89#define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */90#define ADV7511_REG_TMDS_CLOCK_INV 0xde91#define ADV7511_REG_ARC_CTRL 0xdf92#define ADV7511_REG_CEC_I2C_ADDR 0xe193#define ADV7511_REG_CEC_CTRL 0xe294#define ADV7511_REG_CHIP_ID_HIGH 0xf595#define ADV7511_REG_CHIP_ID_LOW 0xf696 97/* Hardware defined default addresses for I2C register maps */98#define ADV7511_CEC_I2C_ADDR_DEFAULT 0x3c99#define ADV7511_EDID_I2C_ADDR_DEFAULT 0x3f100#define ADV7511_PACKET_I2C_ADDR_DEFAULT 0x38101 102#define ADV7511_CSC_ENABLE BIT(7)103#define ADV7511_CSC_UPDATE_MODE BIT(5)104 105#define ADV7511_INT0_HPD BIT(7)106#define ADV7511_INT0_VSYNC BIT(5)107#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)108#define ADV7511_INT0_EDID_READY BIT(2)109#define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)110 111#define ADV7511_INT1_DDC_ERROR BIT(7)112#define ADV7511_INT1_BKSV BIT(6)113#define ADV7511_INT1_CEC_TX_READY BIT(5)114#define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4)115#define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)116#define ADV7511_INT1_CEC_RX_READY3 BIT(2)117#define ADV7511_INT1_CEC_RX_READY2 BIT(1)118#define ADV7511_INT1_CEC_RX_READY1 BIT(0)119 120#define ADV7511_ARC_CTRL_POWER_DOWN BIT(0)121 122#define ADV7511_CEC_CTRL_POWER_DOWN BIT(0)123 124#define ADV7511_POWER_POWER_DOWN BIT(6)125 126#define ADV7511_HDMI_CFG_MODE_MASK 0x2127#define ADV7511_HDMI_CFG_MODE_DVI 0x0128#define ADV7511_HDMI_CFG_MODE_HDMI 0x2129 130#define ADV7511_AUDIO_SELECT_I2C 0x0131#define ADV7511_AUDIO_SELECT_SPDIF 0x1132#define ADV7511_AUDIO_SELECT_DSD 0x2133#define ADV7511_AUDIO_SELECT_HBR 0x3134#define ADV7511_AUDIO_SELECT_DST 0x4135 136#define ADV7511_I2S_SAMPLE_LEN_16 0x2137#define ADV7511_I2S_SAMPLE_LEN_20 0x3138#define ADV7511_I2S_SAMPLE_LEN_18 0x4139#define ADV7511_I2S_SAMPLE_LEN_22 0x5140#define ADV7511_I2S_SAMPLE_LEN_19 0x8141#define ADV7511_I2S_SAMPLE_LEN_23 0x9142#define ADV7511_I2S_SAMPLE_LEN_24 0xb143#define ADV7511_I2S_SAMPLE_LEN_17 0xc144#define ADV7511_I2S_SAMPLE_LEN_21 0xd145 146#define ADV7511_SAMPLE_FREQ_44100 0x0147#define ADV7511_SAMPLE_FREQ_48000 0x2148#define ADV7511_SAMPLE_FREQ_32000 0x3149#define ADV7511_SAMPLE_FREQ_88200 0x8150#define ADV7511_SAMPLE_FREQ_96000 0xa151#define ADV7511_SAMPLE_FREQ_176400 0xc152#define ADV7511_SAMPLE_FREQ_192000 0xe153 154#define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7)155#define ADV7511_STATUS_HPD BIT(6)156#define ADV7511_STATUS_MONITOR_SENSE BIT(5)157#define ADV7511_STATUS_I2S_32BIT_MODE BIT(3)158 159#define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6)160#define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)161#define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)162#define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)163#define ADV7511_PACKET_ENABLE_GC BIT(7)164#define ADV7511_PACKET_ENABLE_SPD BIT(6)165#define ADV7511_PACKET_ENABLE_MPEG BIT(5)166#define ADV7511_PACKET_ENABLE_ACP BIT(4)167#define ADV7511_PACKET_ENABLE_ISRC BIT(3)168#define ADV7511_PACKET_ENABLE_GM BIT(2)169#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)170#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)171 172#define ADV7535_REG_POWER2_HPD_OVERRIDE BIT(6)173#define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0174#define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00175#define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40176#define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80177#define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0178#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)179#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)180 181#define ADV7511_LOW_REFRESH_RATE_NONE 0x0182#define ADV7511_LOW_REFRESH_RATE_24HZ 0x1183#define ADV7511_LOW_REFRESH_RATE_25HZ 0x2184#define ADV7511_LOW_REFRESH_RATE_30HZ 0x3185 186#define ADV7511_AUDIO_CFG3_LEN_MASK 0x0f187#define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK 0xf0188 189#define ADV7511_AUDIO_SOURCE_I2S 0190#define ADV7511_AUDIO_SOURCE_SPDIF 1191 192#define ADV7511_I2S_FORMAT_I2S 0193#define ADV7511_I2S_FORMAT_RIGHT_J 1194#define ADV7511_I2S_FORMAT_LEFT_J 2195#define ADV7511_I2S_IEC958_DIRECT 3196 197#define ADV7511_PACKET(p, x) ((p) * 0x20 + (x))198#define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x)199#define ADV7511_PACKET_MPEG(x) ADV7511_PACKET(1, x)200#define ADV7511_PACKET_ACP(x) ADV7511_PACKET(2, x)201#define ADV7511_PACKET_ISRC1(x) ADV7511_PACKET(3, x)202#define ADV7511_PACKET_ISRC2(x) ADV7511_PACKET(4, x)203#define ADV7511_PACKET_GM(x) ADV7511_PACKET(5, x)204#define ADV7511_PACKET_SPARE(x) ADV7511_PACKET(6, x)205 206#define ADV7511_REG_CEC_TX_FRAME_HDR 0x00207#define ADV7511_REG_CEC_TX_FRAME_DATA0 0x01208#define ADV7511_REG_CEC_TX_FRAME_LEN 0x10209#define ADV7511_REG_CEC_TX_ENABLE 0x11210#define ADV7511_REG_CEC_TX_RETRY 0x12211#define ADV7511_REG_CEC_TX_LOW_DRV_CNT 0x14212#define ADV7511_REG_CEC_RX1_FRAME_HDR 0x15213#define ADV7511_REG_CEC_RX1_FRAME_DATA0 0x16214#define ADV7511_REG_CEC_RX1_FRAME_LEN 0x25215#define ADV7511_REG_CEC_RX_STATUS 0x26216#define ADV7511_REG_CEC_RX2_FRAME_HDR 0x27217#define ADV7511_REG_CEC_RX2_FRAME_DATA0 0x28218#define ADV7511_REG_CEC_RX2_FRAME_LEN 0x37219#define ADV7511_REG_CEC_RX3_FRAME_HDR 0x38220#define ADV7511_REG_CEC_RX3_FRAME_DATA0 0x39221#define ADV7511_REG_CEC_RX3_FRAME_LEN 0x48222#define ADV7511_REG_CEC_RX_BUFFERS 0x4a223#define ADV7511_REG_CEC_LOG_ADDR_MASK 0x4b224#define ADV7511_REG_CEC_LOG_ADDR_0_1 0x4c225#define ADV7511_REG_CEC_LOG_ADDR_2 0x4d226#define ADV7511_REG_CEC_CLK_DIV 0x4e227#define ADV7511_REG_CEC_SOFT_RESET 0x50228 229#define ADV7533_REG_CEC_OFFSET 0x70230 231enum adv7511_input_clock {232 ADV7511_INPUT_CLOCK_1X,233 ADV7511_INPUT_CLOCK_2X,234 ADV7511_INPUT_CLOCK_DDR,235};236 237enum adv7511_input_justification {238 ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,239 ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,240 ADV7511_INPUT_JUSTIFICATION_LEFT = 2,241};242 243enum adv7511_input_sync_pulse {244 ADV7511_INPUT_SYNC_PULSE_DE = 0,245 ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,246 ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,247 ADV7511_INPUT_SYNC_PULSE_NONE = 3,248};249 250/**251 * enum adv7511_sync_polarity - Polarity for the input sync signals252 * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of253 * the currently configured mode.254 * @ADV7511_SYNC_POLARITY_LOW: Sync polarity is low255 * @ADV7511_SYNC_POLARITY_HIGH: Sync polarity is high256 *257 * If the polarity is set to either LOW or HIGH the driver will configure the258 * ADV7511 to internally invert the sync signal if required to match the sync259 * polarity setting for the currently selected output mode.260 *261 * If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal262 * unchanged. This is used when the upstream graphics core already generates263 * the sync signals with the correct polarity.264 */265enum adv7511_sync_polarity {266 ADV7511_SYNC_POLARITY_PASSTHROUGH,267 ADV7511_SYNC_POLARITY_LOW,268 ADV7511_SYNC_POLARITY_HIGH,269};270 271/**272 * struct adv7511_link_config - Describes adv7511 hardware configuration273 * @input_color_depth: Number of bits per color component (8, 10 or 12)274 * @input_colorspace: The input colorspace (RGB, YUV444, YUV422)275 * @input_clock: The input video clock style (1x, 2x, DDR)276 * @input_style: The input component arrangement variant277 * @input_justification: Video input format bit justification278 * @clock_delay: Clock delay for the input clock (in ps)279 * @embedded_sync: Video input uses BT.656-style embedded sync280 * @sync_pulse: Select the sync pulse281 * @vsync_polarity: vsync input signal configuration282 * @hsync_polarity: hsync input signal configuration283 */284struct adv7511_link_config {285 unsigned int input_color_depth;286 enum hdmi_colorspace input_colorspace;287 enum adv7511_input_clock input_clock;288 unsigned int input_style;289 enum adv7511_input_justification input_justification;290 291 int clock_delay;292 293 bool embedded_sync;294 enum adv7511_input_sync_pulse sync_pulse;295 enum adv7511_sync_polarity vsync_polarity;296 enum adv7511_sync_polarity hsync_polarity;297};298 299/**300 * enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC301 * @ADV7511_CSC_SCALING_1: CSC results are not scaled302 * @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two303 * @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four304 */305enum adv7511_csc_scaling {306 ADV7511_CSC_SCALING_1 = 0,307 ADV7511_CSC_SCALING_2 = 1,308 ADV7511_CSC_SCALING_4 = 2,309};310 311/**312 * struct adv7511_video_config - Describes adv7511 hardware configuration313 * @csc_enable: Whether to enable color space conversion314 * @csc_scaling_factor: Color space conversion scaling factor315 * @csc_coefficents: Color space conversion coefficents316 * @hdmi_mode: Whether to use HDMI or DVI output mode317 * @avi_infoframe: HDMI infoframe318 */319struct adv7511_video_config {320 bool csc_enable;321 enum adv7511_csc_scaling csc_scaling_factor;322 const uint16_t *csc_coefficents;323 324 bool hdmi_mode;325 struct hdmi_avi_infoframe avi_infoframe;326};327 328enum adv7511_type {329 ADV7511,330 ADV7533,331 ADV7535,332};333 334#define ADV7511_MAX_ADDRS 3335 336struct adv7511_chip_info {337 enum adv7511_type type;338 unsigned int max_mode_clock_khz;339 unsigned int max_lane_freq_khz;340 const char * const *supply_names;341 unsigned int num_supplies;342 unsigned int reg_cec_offset;343 bool has_dsi;344 bool link_config;345 bool hpd_override_enable;346};347 348struct adv7511 {349 struct i2c_client *i2c_main;350 struct i2c_client *i2c_edid;351 struct i2c_client *i2c_packet;352 struct i2c_client *i2c_cec;353 354 struct regmap *regmap;355 struct regmap *regmap_cec;356 enum drm_connector_status status;357 bool powered;358 359 struct drm_bridge *next_bridge;360 struct drm_display_mode curr_mode;361 362 unsigned int f_tmds;363 unsigned int f_audio;364 unsigned int audio_source;365 366 unsigned int current_edid_segment;367 uint8_t edid_buf[256];368 bool edid_read;369 370 wait_queue_head_t wq;371 struct work_struct hpd_work;372 373 struct drm_bridge bridge;374 struct drm_connector connector;375 376 bool embedded_sync;377 enum adv7511_sync_polarity vsync_polarity;378 enum adv7511_sync_polarity hsync_polarity;379 bool rgb;380 381 struct gpio_desc *gpio_pd;382 383 struct regulator_bulk_data *supplies;384 385 /* ADV7533 DSI RX related params */386 struct device_node *host_node;387 struct mipi_dsi_device *dsi;388 u8 num_dsi_lanes;389 bool use_timing_gen;390 391 const struct adv7511_chip_info *info;392 struct platform_device *audio_pdev;393 394 struct cec_adapter *cec_adap;395 u8 cec_addr[ADV7511_MAX_ADDRS];396 u8 cec_valid_addrs;397 bool cec_enabled_adap;398 struct clk *cec_clk;399 u32 cec_clk_freq;400};401 402#ifdef CONFIG_DRM_I2C_ADV7511_CEC403int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);404int adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);405#else406static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)407{408 regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,409 ADV7511_CEC_CTRL_POWER_DOWN);410 return 0;411}412#endif413 414void adv7533_dsi_power_on(struct adv7511 *adv);415void adv7533_dsi_power_off(struct adv7511 *adv);416enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,417 const struct drm_display_mode *mode);418int adv7533_patch_registers(struct adv7511 *adv);419int adv7533_patch_cec_registers(struct adv7511 *adv);420int adv7533_attach_dsi(struct adv7511 *adv);421int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);422 423#ifdef CONFIG_DRM_I2C_ADV7511_AUDIO424int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511);425void adv7511_audio_exit(struct adv7511 *adv7511);426#else /*CONFIG_DRM_I2C_ADV7511_AUDIO */427static inline int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511)428{429 return 0;430}431static inline void adv7511_audio_exit(struct adv7511 *adv7511)432{433}434#endif /* CONFIG_DRM_I2C_ADV7511_AUDIO */435 436#endif /* __DRM_I2C_ADV7511_H__ */437