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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright(c) 2016, Analogix Semiconductor.4 *5 * Based on anx7808 driver obtained from chromeos with copyright:6 * Copyright(c) 2013, Google Inc.7 */8#include <linux/delay.h>9#include <linux/err.h>10#include <linux/gpio/consumer.h>11#include <linux/i2c.h>12#include <linux/interrupt.h>13#include <linux/kernel.h>14#include <linux/module.h>15#include <linux/of_irq.h>16#include <linux/of_platform.h>17#include <linux/regmap.h>18#include <linux/regulator/consumer.h>19#include <linux/types.h>20 21#include <drm/display/drm_dp_helper.h>22#include <drm/drm_atomic_helper.h>23#include <drm/drm_bridge.h>24#include <drm/drm_crtc.h>25#include <drm/drm_edid.h>26#include <drm/drm_print.h>27#include <drm/drm_probe_helper.h>28 29#include "analogix-anx78xx.h"30 31#define I2C_NUM_ADDRESSES 532#define I2C_IDX_TX_P0 033#define I2C_IDX_TX_P1 134#define I2C_IDX_TX_P2 235#define I2C_IDX_RX_P0 336#define I2C_IDX_RX_P1 437 38#define XTAL_CLK 270 /* 27M */39 40static const u8 anx7808_i2c_addresses[] = {41 [I2C_IDX_TX_P0] = 0x78,42 [I2C_IDX_TX_P1] = 0x7a,43 [I2C_IDX_TX_P2] = 0x72,44 [I2C_IDX_RX_P0] = 0x7e,45 [I2C_IDX_RX_P1] = 0x80,46};47 48static const u8 anx781x_i2c_addresses[] = {49 [I2C_IDX_TX_P0] = 0x70,50 [I2C_IDX_TX_P1] = 0x7a,51 [I2C_IDX_TX_P2] = 0x72,52 [I2C_IDX_RX_P0] = 0x7e,53 [I2C_IDX_RX_P1] = 0x80,54};55 56struct anx78xx_platform_data {57 struct regulator *dvdd10;58 struct gpio_desc *gpiod_hpd;59 struct gpio_desc *gpiod_pd;60 struct gpio_desc *gpiod_reset;61 62 int hpd_irq;63 int intp_irq;64};65 66struct anx78xx {67 struct drm_dp_aux aux;68 struct drm_bridge bridge;69 struct i2c_client *client;70 const struct drm_edid *drm_edid;71 struct drm_connector connector;72 struct anx78xx_platform_data pdata;73 struct mutex lock;74 75 /*76 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,77 * RX_P0 and RX_P1.78 */79 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];80 struct regmap *map[I2C_NUM_ADDRESSES];81 82 u16 chipid;83 u8 dpcd[DP_RECEIVER_CAP_SIZE];84 85 bool powered;86};87 88static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)89{90 return container_of(c, struct anx78xx, connector);91}92 93static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)94{95 return container_of(bridge, struct anx78xx, bridge);96}97 98static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)99{100 return regmap_update_bits(map, reg, mask, mask);101}102 103static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)104{105 return regmap_update_bits(map, reg, mask, 0);106}107 108static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,109 struct drm_dp_aux_msg *msg)110{111 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);112 return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg);113}114 115static int anx78xx_set_hpd(struct anx78xx *anx78xx)116{117 int err;118 119 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],120 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);121 if (err)122 return err;123 124 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,125 SP_HPD_OUT);126 if (err)127 return err;128 129 return 0;130}131 132static int anx78xx_clear_hpd(struct anx78xx *anx78xx)133{134 int err;135 136 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,137 SP_HPD_OUT);138 if (err)139 return err;140 141 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],142 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);143 if (err)144 return err;145 146 return 0;147}148 149static const struct reg_sequence tmds_phy_initialization[] = {150 { SP_TMDS_CTRL_BASE + 1, 0x90 },151 { SP_TMDS_CTRL_BASE + 2, 0xa9 },152 { SP_TMDS_CTRL_BASE + 6, 0x92 },153 { SP_TMDS_CTRL_BASE + 7, 0x80 },154 { SP_TMDS_CTRL_BASE + 20, 0xf2 },155 { SP_TMDS_CTRL_BASE + 22, 0xc4 },156 { SP_TMDS_CTRL_BASE + 23, 0x18 },157};158 159static int anx78xx_rx_initialization(struct anx78xx *anx78xx)160{161 int err;162 163 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,164 SP_AUD_MUTE | SP_VID_MUTE);165 if (err)166 return err;167 168 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,169 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |170 SP_DIGITAL_CKDT_EN);171 if (err)172 return err;173 174 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],175 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |176 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);177 if (err)178 return err;179 180 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],181 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |182 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);183 if (err)184 return err;185 186 /* Sync detect change, GP set mute */187 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],188 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |189 BIT(6));190 if (err)191 return err;192 193 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],194 SP_AUD_EXCEPTION_ENABLE_BASE + 3,195 SP_AEC_EN21);196 if (err)197 return err;198 199 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,200 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);201 if (err)202 return err;203 204 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],205 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);206 if (err)207 return err;208 209 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],210 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);211 if (err)212 return err;213 214 /* Enable DDC stretch */215 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],216 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);217 if (err)218 return err;219 220 /* TMDS phy initialization */221 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],222 tmds_phy_initialization,223 ARRAY_SIZE(tmds_phy_initialization));224 if (err)225 return err;226 227 err = anx78xx_clear_hpd(anx78xx);228 if (err)229 return err;230 231 return 0;232}233 234static const u8 dp_tx_output_precise_tune_bits[20] = {235 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,236 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,237 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,238};239 240static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)241{242 int err;243 244 /*245 * REVISIT : It is writing to a RESERVED bits in Analog Control 0246 * register.247 */248 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,249 0x02);250 if (err)251 return err;252 253 /*254 * Write DP TX output emphasis precise tune bits.255 */256 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],257 SP_DP_TX_LT_CTRL0_REG,258 dp_tx_output_precise_tune_bits,259 ARRAY_SIZE(dp_tx_output_precise_tune_bits));260 261 if (err)262 return err;263 264 return 0;265}266 267static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)268{269 unsigned int value;270 int err;271 272 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],273 SP_ANALOG_DEBUG2_REG,274 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,275 SP_XTAL_FRQ_27M);276 if (err)277 return err;278 279 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,280 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);281 if (err)282 return err;283 284 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,285 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));286 if (err)287 return err;288 289 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],290 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);291 if (err)292 return err;293 294 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],295 SP_I2C_GEN_10US_TIMER1_REG,296 (XTAL_CLK & 0xff00) >> 8);297 if (err)298 return err;299 300 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,301 XTAL_CLK / 10 - 1);302 if (err)303 return err;304 305 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],306 SP_HDMI_US_TIMER_CTRL_REG,307 &value);308 if (err)309 return err;310 311 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],312 SP_HDMI_US_TIMER_CTRL_REG,313 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |314 ((((XTAL_CLK / 10) >> 1) - 2) << 3));315 if (err)316 return err;317 318 return 0;319}320 321static const struct reg_sequence otp_key_protect[] = {322 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },323 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },324 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },325};326 327static int anx78xx_tx_initialization(struct anx78xx *anx78xx)328{329 int err;330 331 /* Set terminal resistor to 50 ohm */332 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,333 0x30);334 if (err)335 return err;336 337 /* Enable aux double diff output */338 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],339 SP_DP_AUX_CH_CTRL2_REG, 0x08);340 if (err)341 return err;342 343 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],344 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |345 SP_AUTO_START);346 if (err)347 return err;348 349 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],350 otp_key_protect,351 ARRAY_SIZE(otp_key_protect));352 if (err)353 return err;354 355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],356 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);357 if (err)358 return err;359 360 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,361 SP_VID_VRES_TH);362 if (err)363 return err;364 365 /*366 * DP HDCP auto authentication wait timer (when downstream starts to367 * auth, DP side will wait for this period then do auth automatically)368 */369 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,370 0x00);371 if (err)372 return err;373 374 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],375 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);376 if (err)377 return err;378 379 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],380 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);381 if (err)382 return err;383 384 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],385 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);386 if (err)387 return err;388 389 err = anx78xx_xtal_clk_sel(anx78xx);390 if (err)391 return err;392 393 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,394 SP_DEFER_CTRL_EN | 0x0c);395 if (err)396 return err;397 398 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],399 SP_DP_POLLING_CTRL_REG,400 SP_AUTO_POLLING_DISABLE);401 if (err)402 return err;403 404 /*405 * Short the link integrity check timer to speed up bstatus406 * polling for HDCP CTS item 1A-07407 */408 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],409 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);410 if (err)411 return err;412 413 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],414 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);415 if (err)416 return err;417 418 /* Power down the main link by default */419 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],420 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);421 if (err)422 return err;423 424 err = anx78xx_link_phy_initialization(anx78xx);425 if (err)426 return err;427 428 /* Gen m_clk with downspreading */429 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],430 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);431 if (err)432 return err;433 434 return 0;435}436 437static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)438{439 int err;440 441 /*442 * BIT0: INT pin assertion polarity: 1 = assert high443 * BIT1: INT pin output type: 0 = push/pull444 */445 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);446 if (err)447 return err;448 449 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],450 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);451 if (err)452 return err;453 454 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,455 SP_TRAINING_FINISH);456 if (err)457 return err;458 459 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,460 SP_CKDT_CHG | SP_SCDT_CHG);461 if (err)462 return err;463 464 return 0;465}466 467static void anx78xx_poweron(struct anx78xx *anx78xx)468{469 struct anx78xx_platform_data *pdata = &anx78xx->pdata;470 int err;471 472 if (WARN_ON(anx78xx->powered))473 return;474 475 if (pdata->dvdd10) {476 err = regulator_enable(pdata->dvdd10);477 if (err) {478 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",479 err);480 return;481 }482 483 usleep_range(1000, 2000);484 }485 486 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);487 usleep_range(1000, 2000);488 489 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);490 usleep_range(1000, 2000);491 492 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);493 494 /* Power on registers module */495 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,496 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);497 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,498 SP_REGISTER_PD | SP_TOTAL_PD);499 500 anx78xx->powered = true;501}502 503static void anx78xx_poweroff(struct anx78xx *anx78xx)504{505 struct anx78xx_platform_data *pdata = &anx78xx->pdata;506 int err;507 508 if (WARN_ON(!anx78xx->powered))509 return;510 511 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);512 usleep_range(1000, 2000);513 514 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);515 usleep_range(1000, 2000);516 517 if (pdata->dvdd10) {518 err = regulator_disable(pdata->dvdd10);519 if (err) {520 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",521 err);522 return;523 }524 525 usleep_range(1000, 2000);526 }527 528 anx78xx->powered = false;529}530 531static int anx78xx_start(struct anx78xx *anx78xx)532{533 int err;534 535 /* Power on all modules */536 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],537 SP_POWERDOWN_CTRL_REG,538 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |539 SP_LINK_PD);540 541 err = anx78xx_enable_interrupts(anx78xx);542 if (err) {543 DRM_ERROR("Failed to enable interrupts: %d\n", err);544 goto err_poweroff;545 }546 547 err = anx78xx_rx_initialization(anx78xx);548 if (err) {549 DRM_ERROR("Failed receiver initialization: %d\n", err);550 goto err_poweroff;551 }552 553 err = anx78xx_tx_initialization(anx78xx);554 if (err) {555 DRM_ERROR("Failed transmitter initialization: %d\n", err);556 goto err_poweroff;557 }558 559 /*560 * This delay seems to help keep the hardware in a good state. Without561 * it, there are times where it fails silently.562 */563 usleep_range(10000, 15000);564 565 return 0;566 567err_poweroff:568 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);569 anx78xx_poweroff(anx78xx);570 571 return err;572}573 574static int anx78xx_init_pdata(struct anx78xx *anx78xx)575{576 struct anx78xx_platform_data *pdata = &anx78xx->pdata;577 struct device *dev = &anx78xx->client->dev;578 579 /* 1.0V digital core power regulator */580 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");581 if (IS_ERR(pdata->dvdd10)) {582 if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)583 DRM_ERROR("DVDD10 regulator not found\n");584 585 return PTR_ERR(pdata->dvdd10);586 }587 588 /* GPIO for HPD */589 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);590 if (IS_ERR(pdata->gpiod_hpd))591 return PTR_ERR(pdata->gpiod_hpd);592 593 /* GPIO for chip power down */594 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);595 if (IS_ERR(pdata->gpiod_pd))596 return PTR_ERR(pdata->gpiod_pd);597 598 /* GPIO for chip reset */599 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);600 601 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);602}603 604static int anx78xx_dp_link_training(struct anx78xx *anx78xx)605{606 u8 dp_bw, dpcd[2];607 int err;608 609 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,610 0x0);611 if (err)612 return err;613 614 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],615 SP_POWERDOWN_CTRL_REG,616 SP_TOTAL_PD);617 if (err)618 return err;619 620 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);621 if (err < 0)622 return err;623 624 switch (dp_bw) {625 case DP_LINK_BW_1_62:626 case DP_LINK_BW_2_7:627 case DP_LINK_BW_5_4:628 break;629 630 default:631 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);632 return -EINVAL;633 }634 635 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,636 SP_VIDEO_MUTE);637 if (err)638 return err;639 640 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],641 SP_VID_CTRL1_REG, SP_VIDEO_EN);642 if (err)643 return err;644 645 /* Get DPCD info */646 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);648 if (err < 0) {649 DRM_ERROR("Failed to read DPCD: %d\n", err);650 return err;651 }652 653 /* Clear channel x SERDES power down */654 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],655 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);656 if (err)657 return err;658 659 /*660 * Power up the sink (DP_SET_POWER register is only available on DPCD661 * v1.1 and later).662 */663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) {664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]);665 if (err < 0) {666 DRM_ERROR("Failed to read DP_SET_POWER register: %d\n",667 err);668 return err;669 }670 671 dpcd[0] &= ~DP_SET_POWER_MASK;672 dpcd[0] |= DP_SET_POWER_D0;673 674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]);675 if (err < 0) {676 DRM_ERROR("Failed to power up DisplayPort link: %d\n",677 err);678 return err;679 }680 681 /*682 * According to the DP 1.1 specification, a "Sink Device must683 * exit the power saving state within 1 ms" (Section 2.5.3.1,684 * Table 5-52, "Sink Control Field" (register 0x600).685 */686 usleep_range(1000, 2000);687 }688 689 /* Possibly enable downspread on the sink */690 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],691 SP_DP_DOWNSPREAD_CTRL1_REG, 0);692 if (err)693 return err;694 695 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {696 DRM_DEBUG("Enable downspread on the sink\n");697 /* 4000PPM */698 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],699 SP_DP_DOWNSPREAD_CTRL1_REG, 8);700 if (err)701 return err;702 703 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,704 DP_SPREAD_AMP_0_5);705 if (err < 0)706 return err;707 } else {708 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);709 if (err < 0)710 return err;711 }712 713 /* Set the lane count and the link rate on the sink */714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))715 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],716 SP_DP_SYSTEM_CTRL_BASE + 4,717 SP_ENHANCED_MODE);718 else719 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],720 SP_DP_SYSTEM_CTRL_BASE + 4,721 SP_ENHANCED_MODE);722 if (err)723 return err;724 725 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],726 SP_DP_MAIN_LINK_BW_SET_REG,727 anx78xx->dpcd[DP_MAX_LINK_RATE]);728 if (err)729 return err;730 731 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd);732 733 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))734 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;735 736 err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,737 sizeof(dpcd));738 if (err < 0) {739 DRM_ERROR("Failed to configure link: %d\n", err);740 return err;741 }742 743 /* Start training on the source */744 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,745 SP_LT_EN);746 if (err)747 return err;748 749 return 0;750}751 752static int anx78xx_config_dp_output(struct anx78xx *anx78xx)753{754 int err;755 756 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,757 SP_VIDEO_MUTE);758 if (err)759 return err;760 761 /* Enable DP output */762 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,763 SP_VIDEO_EN);764 if (err)765 return err;766 767 return 0;768}769 770static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,771 struct hdmi_avi_infoframe *frame)772{773 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];774 int err;775 776 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));777 if (err < 0) {778 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);779 return err;780 }781 782 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],783 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);784 if (err)785 return err;786 787 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],788 SP_INFOFRAME_AVI_DB1_REG, buffer,789 frame->length);790 if (err)791 return err;792 793 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],794 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);795 if (err)796 return err;797 798 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],799 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);800 if (err)801 return err;802 803 return 0;804}805 806static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)807{808 u8 value;809 int err;810 811 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);812 if (err < 0) {813 DRM_ERROR("Get sink count failed %d\n", err);814 return err;815 }816 817 if (!DP_GET_SINK_COUNT(value)) {818 DRM_ERROR("Downstream disconnected\n");819 return -EIO;820 }821 822 return 0;823}824 825static int anx78xx_get_modes(struct drm_connector *connector)826{827 struct anx78xx *anx78xx = connector_to_anx78xx(connector);828 int err, num_modes = 0;829 830 if (WARN_ON(!anx78xx->powered))831 return 0;832 833 if (anx78xx->drm_edid)834 return drm_edid_connector_add_modes(connector);835 836 mutex_lock(&anx78xx->lock);837 838 err = anx78xx_get_downstream_info(anx78xx);839 if (err) {840 DRM_ERROR("Failed to get downstream info: %d\n", err);841 goto unlock;842 }843 844 anx78xx->drm_edid = drm_edid_read_ddc(connector, &anx78xx->aux.ddc);845 846 err = drm_edid_connector_update(connector, anx78xx->drm_edid);847 848 if (!anx78xx->drm_edid) {849 DRM_ERROR("Failed to read EDID\n");850 goto unlock;851 }852 853 if (err) {854 DRM_ERROR("Failed to update EDID property: %d\n", err);855 goto unlock;856 }857 858 num_modes = drm_edid_connector_add_modes(connector);859 860unlock:861 mutex_unlock(&anx78xx->lock);862 863 return num_modes;864}865 866static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {867 .get_modes = anx78xx_get_modes,868};869 870static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,871 bool force)872{873 struct anx78xx *anx78xx = connector_to_anx78xx(connector);874 875 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))876 return connector_status_disconnected;877 878 return connector_status_connected;879}880 881static const struct drm_connector_funcs anx78xx_connector_funcs = {882 .fill_modes = drm_helper_probe_single_connector_modes,883 .detect = anx78xx_detect,884 .destroy = drm_connector_cleanup,885 .reset = drm_atomic_helper_connector_reset,886 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,887 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,888};889 890static int anx78xx_bridge_attach(struct drm_bridge *bridge,891 enum drm_bridge_attach_flags flags)892{893 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);894 int err;895 896 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {897 DRM_ERROR("Fix bridge driver to make connector optional!");898 return -EINVAL;899 }900 901 /* Register aux channel */902 anx78xx->aux.name = "DP-AUX";903 anx78xx->aux.dev = &anx78xx->client->dev;904 anx78xx->aux.drm_dev = bridge->dev;905 anx78xx->aux.transfer = anx78xx_aux_transfer;906 907 err = drm_dp_aux_register(&anx78xx->aux);908 if (err < 0) {909 DRM_ERROR("Failed to register aux channel: %d\n", err);910 return err;911 }912 913 err = drm_connector_init(bridge->dev, &anx78xx->connector,914 &anx78xx_connector_funcs,915 DRM_MODE_CONNECTOR_DisplayPort);916 if (err) {917 DRM_ERROR("Failed to initialize connector: %d\n", err);918 goto aux_unregister;919 }920 921 drm_connector_helper_add(&anx78xx->connector,922 &anx78xx_connector_helper_funcs);923 924 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;925 926 err = drm_connector_attach_encoder(&anx78xx->connector,927 bridge->encoder);928 if (err) {929 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);930 goto connector_cleanup;931 }932 933 err = drm_connector_register(&anx78xx->connector);934 if (err) {935 DRM_ERROR("Failed to register connector: %d\n", err);936 goto connector_cleanup;937 }938 939 return 0;940connector_cleanup:941 drm_connector_cleanup(&anx78xx->connector);942aux_unregister:943 drm_dp_aux_unregister(&anx78xx->aux);944 return err;945}946 947static void anx78xx_bridge_detach(struct drm_bridge *bridge)948{949 drm_dp_aux_unregister(&bridge_to_anx78xx(bridge)->aux);950}951 952static enum drm_mode_status953anx78xx_bridge_mode_valid(struct drm_bridge *bridge,954 const struct drm_display_info *info,955 const struct drm_display_mode *mode)956{957 if (mode->flags & DRM_MODE_FLAG_INTERLACE)958 return MODE_NO_INTERLACE;959 960 /* Max 1200p at 5.4 Ghz, one lane */961 if (mode->clock > 154000)962 return MODE_CLOCK_HIGH;963 964 return MODE_OK;965}966 967static void anx78xx_bridge_disable(struct drm_bridge *bridge)968{969 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);970 971 /* Power off all modules except configuration registers access */972 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,973 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);974}975 976static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,977 const struct drm_display_mode *mode,978 const struct drm_display_mode *adjusted_mode)979{980 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);981 struct hdmi_avi_infoframe frame;982 int err;983 984 if (WARN_ON(!anx78xx->powered))985 return;986 987 mutex_lock(&anx78xx->lock);988 989 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,990 &anx78xx->connector,991 adjusted_mode);992 if (err) {993 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);994 goto unlock;995 }996 997 err = anx78xx_send_video_infoframe(anx78xx, &frame);998 if (err)999 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);1000 1001unlock:1002 mutex_unlock(&anx78xx->lock);1003}1004 1005static void anx78xx_bridge_enable(struct drm_bridge *bridge)1006{1007 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);1008 int err;1009 1010 err = anx78xx_start(anx78xx);1011 if (err) {1012 DRM_ERROR("Failed to initialize: %d\n", err);1013 return;1014 }1015 1016 err = anx78xx_set_hpd(anx78xx);1017 if (err)1018 DRM_ERROR("Failed to set HPD: %d\n", err);1019}1020 1021static const struct drm_bridge_funcs anx78xx_bridge_funcs = {1022 .attach = anx78xx_bridge_attach,1023 .detach = anx78xx_bridge_detach,1024 .mode_valid = anx78xx_bridge_mode_valid,1025 .disable = anx78xx_bridge_disable,1026 .mode_set = anx78xx_bridge_mode_set,1027 .enable = anx78xx_bridge_enable,1028};1029 1030static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)1031{1032 struct anx78xx *anx78xx = data;1033 int err;1034 1035 if (anx78xx->powered)1036 return IRQ_HANDLED;1037 1038 mutex_lock(&anx78xx->lock);1039 1040 /* Cable is pulled, power on the chip */1041 anx78xx_poweron(anx78xx);1042 1043 err = anx78xx_enable_interrupts(anx78xx);1044 if (err)1045 DRM_ERROR("Failed to enable interrupts: %d\n", err);1046 1047 mutex_unlock(&anx78xx->lock);1048 1049 return IRQ_HANDLED;1050}1051 1052static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)1053{1054 int err;1055 1056 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);1057 1058 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,1059 irq);1060 if (err)1061 return err;1062 1063 if (irq & SP_TRAINING_FINISH) {1064 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");1065 err = anx78xx_config_dp_output(anx78xx);1066 }1067 1068 return err;1069}1070 1071static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)1072{1073 bool event = false;1074 int err;1075 1076 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);1077 1078 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],1079 SP_COMMON_INT_STATUS4_REG, irq);1080 if (err) {1081 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);1082 return event;1083 }1084 1085 if (irq & SP_HPD_LOST) {1086 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");1087 event = true;1088 anx78xx_poweroff(anx78xx);1089 /* Free cached EDID */1090 drm_edid_free(anx78xx->drm_edid);1091 anx78xx->drm_edid = NULL;1092 } else if (irq & SP_HPD_PLUG) {1093 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");1094 event = true;1095 }1096 1097 return event;1098}1099 1100static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)1101{1102 unsigned int value;1103 int err;1104 1105 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);1106 1107 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,1108 irq);1109 if (err) {1110 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);1111 return;1112 }1113 1114 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {1115 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");1116 1117 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],1118 SP_SYSTEM_STATUS_REG, &value);1119 if (err) {1120 DRM_ERROR("Read system status reg failed: %d\n", err);1121 return;1122 }1123 1124 if (!(value & SP_TMDS_CLOCK_DET)) {1125 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");1126 return;1127 }1128 1129 if (!(value & SP_TMDS_DE_DET)) {1130 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");1131 return;1132 }1133 1134 err = anx78xx_dp_link_training(anx78xx);1135 if (err)1136 DRM_ERROR("Failed to start link training: %d\n", err);1137 }1138}1139 1140static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)1141{1142 struct anx78xx *anx78xx = data;1143 bool event = false;1144 unsigned int irq;1145 int err;1146 1147 mutex_lock(&anx78xx->lock);1148 1149 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,1150 &irq);1151 if (err) {1152 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);1153 goto unlock;1154 }1155 1156 if (irq)1157 anx78xx_handle_dp_int_1(anx78xx, irq);1158 1159 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],1160 SP_COMMON_INT_STATUS4_REG, &irq);1161 if (err) {1162 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",1163 err);1164 goto unlock;1165 }1166 1167 if (irq)1168 event = anx78xx_handle_common_int_4(anx78xx, irq);1169 1170 /* Make sure we are still powered after handle HPD events */1171 if (!anx78xx->powered)1172 goto unlock;1173 1174 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,1175 &irq);1176 if (err) {1177 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);1178 goto unlock;1179 }1180 1181 if (irq)1182 anx78xx_handle_hdmi_int_1(anx78xx, irq);1183 1184unlock:1185 mutex_unlock(&anx78xx->lock);1186 1187 if (event)1188 drm_helper_hpd_irq_event(anx78xx->connector.dev);1189 1190 return IRQ_HANDLED;1191}1192 1193static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)1194{1195 unsigned int i;1196 1197 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)1198 i2c_unregister_device(anx78xx->i2c_dummy[i]);1199}1200 1201static const struct regmap_config anx78xx_regmap_config = {1202 .reg_bits = 8,1203 .val_bits = 8,1204};1205 1206static const u16 anx78xx_chipid_list[] = {1207 0x7808,1208 0x7812,1209 0x7814,1210 0x7816,1211 0x7818,1212};1213 1214static int anx78xx_i2c_probe(struct i2c_client *client)1215{1216 struct anx78xx *anx78xx;1217 struct anx78xx_platform_data *pdata;1218 unsigned int i, idl, idh, version;1219 const u8 *i2c_addresses;1220 bool found = false;1221 int err;1222 1223 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);1224 if (!anx78xx)1225 return -ENOMEM;1226 1227 pdata = &anx78xx->pdata;1228 1229 mutex_init(&anx78xx->lock);1230 1231 anx78xx->bridge.of_node = client->dev.of_node;1232 1233 anx78xx->client = client;1234 i2c_set_clientdata(client, anx78xx);1235 1236 err = anx78xx_init_pdata(anx78xx);1237 if (err) {1238 if (err != -EPROBE_DEFER)1239 DRM_ERROR("Failed to initialize pdata: %d\n", err);1240 1241 return err;1242 }1243 1244 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);1245 if (pdata->hpd_irq < 0) {1246 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);1247 return -ENODEV;1248 }1249 1250 pdata->intp_irq = client->irq;1251 if (!pdata->intp_irq) {1252 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");1253 return -ENODEV;1254 }1255 1256 /* Map slave addresses of ANX7814 */1257 i2c_addresses = device_get_match_data(&client->dev);1258 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {1259 struct i2c_client *i2c_dummy;1260 1261 i2c_dummy = i2c_new_dummy_device(client->adapter,1262 i2c_addresses[i] >> 1);1263 if (IS_ERR(i2c_dummy)) {1264 err = PTR_ERR(i2c_dummy);1265 DRM_ERROR("Failed to reserve I2C bus %02x: %d\n",1266 i2c_addresses[i], err);1267 goto err_unregister_i2c;1268 }1269 1270 anx78xx->i2c_dummy[i] = i2c_dummy;1271 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],1272 &anx78xx_regmap_config);1273 if (IS_ERR(anx78xx->map[i])) {1274 err = PTR_ERR(anx78xx->map[i]);1275 DRM_ERROR("Failed regmap initialization %02x\n",1276 i2c_addresses[i]);1277 goto err_unregister_i2c;1278 }1279 }1280 1281 /* Look for supported chip ID */1282 anx78xx_poweron(anx78xx);1283 1284 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,1285 &idl);1286 if (err)1287 goto err_poweroff;1288 1289 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,1290 &idh);1291 if (err)1292 goto err_poweroff;1293 1294 anx78xx->chipid = (u8)idl | ((u8)idh << 8);1295 1296 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,1297 &version);1298 if (err)1299 goto err_poweroff;1300 1301 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {1302 if (anx78xx->chipid == anx78xx_chipid_list[i]) {1303 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",1304 anx78xx->chipid, version);1305 found = true;1306 break;1307 }1308 }1309 1310 if (!found) {1311 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",1312 anx78xx->chipid, version);1313 err = -ENODEV;1314 goto err_poweroff;1315 }1316 1317 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,1318 anx78xx_hpd_threaded_handler,1319 IRQF_TRIGGER_RISING | IRQF_ONESHOT,1320 "anx78xx-hpd", anx78xx);1321 if (err) {1322 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",1323 err);1324 goto err_poweroff;1325 }1326 1327 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,1328 anx78xx_intp_threaded_handler,1329 IRQF_TRIGGER_RISING | IRQF_ONESHOT,1330 "anx78xx-intp", anx78xx);1331 if (err) {1332 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);1333 goto err_poweroff;1334 }1335 1336 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;1337 1338 drm_bridge_add(&anx78xx->bridge);1339 1340 /* If cable is pulled out, just poweroff and wait for HPD event */1341 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))1342 anx78xx_poweroff(anx78xx);1343 1344 return 0;1345 1346err_poweroff:1347 anx78xx_poweroff(anx78xx);1348 1349err_unregister_i2c:1350 unregister_i2c_dummy_clients(anx78xx);1351 return err;1352}1353 1354static void anx78xx_i2c_remove(struct i2c_client *client)1355{1356 struct anx78xx *anx78xx = i2c_get_clientdata(client);1357 1358 drm_bridge_remove(&anx78xx->bridge);1359 1360 unregister_i2c_dummy_clients(anx78xx);1361 1362 drm_edid_free(anx78xx->drm_edid);1363}1364 1365static const struct of_device_id anx78xx_match_table[] = {1366 { .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses },1367 { .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses },1368 { .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses },1369 { .compatible = "analogix,anx7816", .data = anx781x_i2c_addresses },1370 { .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses },1371 { /* sentinel */ },1372};1373MODULE_DEVICE_TABLE(of, anx78xx_match_table);1374 1375static struct i2c_driver anx78xx_driver = {1376 .driver = {1377 .name = "anx7814",1378 .of_match_table = anx78xx_match_table,1379 },1380 .probe = anx78xx_i2c_probe,1381 .remove = anx78xx_i2c_remove,1382};1383module_i2c_driver(anx78xx_driver);1384 1385MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");1386MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");1387MODULE_LICENSE("GPL v2");1388