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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.4 *5 */6 7#ifndef __ANX7625_H__8#define __ANX7625_H__9 10#define ANX7625_DRV_VERSION "0.1.04"11 12/* Loading OCM re-trying times */13#define OCM_LOADING_TIME 1014 15/********* ANX7625 Register **********/16#define TX_P0_ADDR 0x7017#define TX_P1_ADDR 0x7A18#define TX_P2_ADDR 0x7219 20#define RX_P0_ADDR 0x7e21#define RX_P1_ADDR 0x8422#define RX_P2_ADDR 0x5423 24#define RSVD_00_ADDR 0x0025#define RSVD_D1_ADDR 0xD126#define RSVD_60_ADDR 0x6027#define RSVD_39_ADDR 0x3928#define RSVD_7F_ADDR 0x7F29 30#define TCPC_INTERFACE_ADDR 0x5831 32/* Clock frequency in Hz */33#define XTAL_FRQ (27 * 1000000)34 35#define POST_DIVIDER_MIN 136#define POST_DIVIDER_MAX 1637#define PLL_OUT_FREQ_MIN 520000000UL38#define PLL_OUT_FREQ_MAX 730000000UL39#define PLL_OUT_FREQ_ABS_MIN 300000000UL40#define PLL_OUT_FREQ_ABS_MAX 800000000UL41#define MAX_UNSIGNED_24BIT 16777215UL42 43/***************************************************************/44/* Register definition of device address 0x58 */45 46#define PRODUCT_ID_L 0x0247#define PRODUCT_ID_H 0x0348 49#define INTR_ALERT_1 0xCC50#define INTR_SOFTWARE_INT BIT(3)51#define INTR_RECEIVED_MSG BIT(5)52 53#define SYSTEM_STSTUS 0x4554#define INTERFACE_CHANGE_INT 0x4455#define HPD_STATUS_CHANGE 0x8056#define HPD_STATUS 0x8057 58/******** END of I2C Address 0x58 ********/59 60/***************************************************************/61/* Register definition of device address 0x70 */62#define TX_HDCP_CTRL0 0x0163#define STORE_AN BIT(7)64#define RX_REPEATER BIT(6)65#define RE_AUTHEN BIT(5)66#define SW_AUTH_OK BIT(4)67#define HARD_AUTH_EN BIT(3)68#define ENC_EN BIT(2)69#define BKSV_SRM_PASS BIT(1)70#define KSVLIST_VLD BIT(0)71 72#define SP_TX_WAIT_R0_TIME 0x4073#define SP_TX_WAIT_KSVR_TIME 0x4274#define SP_TX_SYS_CTRL1_REG 0x8075#define HDCP2TX_FW_EN BIT(4)76 77#define SP_TX_LINK_BW_SET_REG 0xA078#define SP_TX_LANE_COUNT_SET_REG 0xA179 80#define M_VID_0 0xC081#define M_VID_1 0xC182#define M_VID_2 0xC283#define N_VID_0 0xC384#define N_VID_1 0xC485#define N_VID_2 0xC586 87#define KEY_START_ADDR 0x900088#define KEY_RESERVED 41689 90#define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED)91#define HDCP14KEY_SIZE 62492 93/***************************************************************/94/* Register definition of device address 0x72 */95#define AUX_RST 0x0496#define RST_CTRL2 0x0797 98#define SP_TX_TOTAL_LINE_STA_L 0x2499#define SP_TX_TOTAL_LINE_STA_H 0x25100#define SP_TX_ACT_LINE_STA_L 0x26101#define SP_TX_ACT_LINE_STA_H 0x27102#define SP_TX_V_F_PORCH_STA 0x28103#define SP_TX_V_SYNC_STA 0x29104#define SP_TX_V_B_PORCH_STA 0x2A105#define SP_TX_TOTAL_PIXEL_STA_L 0x2B106#define SP_TX_TOTAL_PIXEL_STA_H 0x2C107#define SP_TX_ACT_PIXEL_STA_L 0x2D108#define SP_TX_ACT_PIXEL_STA_H 0x2E109#define SP_TX_H_F_PORCH_STA_L 0x2F110#define SP_TX_H_F_PORCH_STA_H 0x30111#define SP_TX_H_SYNC_STA_L 0x31112#define SP_TX_H_SYNC_STA_H 0x32113#define SP_TX_H_B_PORCH_STA_L 0x33114#define SP_TX_H_B_PORCH_STA_H 0x34115 116#define SP_TX_VID_CTRL 0x84117#define SP_TX_BPC_MASK 0xE0118#define SP_TX_BPC_6 0x00119#define SP_TX_BPC_8 0x20120#define SP_TX_BPC_10 0x40121#define SP_TX_BPC_12 0x60122 123#define VIDEO_BIT_MATRIX_12 0x4c124 125#define AUDIO_CHANNEL_STATUS_1 0xd0126#define AUDIO_CHANNEL_STATUS_2 0xd1127#define AUDIO_CHANNEL_STATUS_3 0xd2128#define AUDIO_CHANNEL_STATUS_4 0xd3129#define AUDIO_CHANNEL_STATUS_5 0xd4130#define AUDIO_CHANNEL_STATUS_6 0xd5131#define TDM_SLAVE_MODE 0x10132#define I2S_SLAVE_MODE 0x08133#define AUDIO_LAYOUT 0x01134 135#define HPD_DET_TIMER_BIT0_7 0xea136#define HPD_DET_TIMER_BIT8_15 0xeb137#define HPD_DET_TIMER_BIT16_23 0xec138/* HPD debounce time 2ms for 27M clock */139#define HPD_TIME 54000140 141#define AUDIO_CONTROL_REGISTER 0xe6142#define TDM_TIMING_MODE 0x08143 144#define I2C_ADDR_72_DPTX 0x72145 146#define HP_MIN 8147#define HBLANKING_MIN 80148#define SYNC_LEN_DEF 32149#define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2)150#define VIDEO_CONTROL_0 0x08151 152#define ACTIVE_LINES_L 0x14153#define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */154#define VERTICAL_FRONT_PORCH 0x16155#define VERTICAL_SYNC_WIDTH 0x17156#define VERTICAL_BACK_PORCH 0x18157 158#define HORIZONTAL_TOTAL_PIXELS_L 0x19159#define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */160#define HORIZONTAL_ACTIVE_PIXELS_L 0x1B161#define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */162#define HORIZONTAL_FRONT_PORCH_L 0x1D163#define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */164#define HORIZONTAL_SYNC_WIDTH_L 0x1F165#define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */166#define HORIZONTAL_BACK_PORCH_L 0x21167#define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */168 169/******** END of I2C Address 0x72 *********/170 171/***************************************************************/172/* Register definition of device address 0x7a */173#define DP_TX_SWING_REG_CNT 0x14174#define DP_TX_LANE0_SWING_REG0 0x00175#define DP_TX_LANE1_SWING_REG0 0x14176/******** END of I2C Address 0x7a *********/177 178/***************************************************************/179/* Register definition of device address 0x7e */180 181#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E182 183#define R_BOOT_RETRY 0x00184#define R_RAM_ADDR_H 0x01185#define R_RAM_ADDR_L 0x02186#define R_RAM_LEN_H 0x03187#define R_RAM_LEN_L 0x04188#define FLASH_LOAD_STA 0x05189#define FLASH_LOAD_STA_CHK BIT(7)190 191#define R_RAM_CTRL 0x05192/* bit positions */193#define FLASH_DONE BIT(7)194#define BOOT_LOAD_DONE BIT(6)195#define CRC_OK BIT(5)196#define LOAD_DONE BIT(4)197#define O_RW_DONE BIT(3)198#define FUSE_BUSY BIT(2)199#define DECRYPT_EN BIT(1)200#define LOAD_START BIT(0)201 202#define FLASH_ADDR_HIGH 0x0F203#define FLASH_ADDR_LOW 0x10204#define FLASH_LEN_HIGH 0x31205#define FLASH_LEN_LOW 0x32206#define R_FLASH_RW_CTRL 0x33207/* bit positions */208#define READ_DELAY_SELECT BIT(7)209#define GENERAL_INSTRUCTION_EN BIT(6)210#define FLASH_ERASE_EN BIT(5)211#define RDID_READ_EN BIT(4)212#define REMS_READ_EN BIT(3)213#define WRITE_STATUS_EN BIT(2)214#define FLASH_READ BIT(1)215#define FLASH_WRITE BIT(0)216 217#define FLASH_BUF_BASE_ADDR 0x60218#define FLASH_BUF_LEN 0x20219 220#define XTAL_FRQ_SEL 0x3F221/* bit field positions */222#define XTAL_FRQ_SEL_POS 5223/* bit field values */224#define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS)225#define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS)226 227#define R_DSC_CTRL_0 0x40228#define READ_STATUS_EN 7229#define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */230#define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */231#define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */232 233#define OCM_FW_VERSION 0x31234#define OCM_FW_REVERSION 0x32235 236#define AP_AUX_ADDR_7_0 0x11237#define AP_AUX_ADDR_15_8 0x12238#define AP_AUX_ADDR_19_16 0x13239 240/* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */241#define AP_AUX_CTRL_STATUS 0x14242#define AP_AUX_CTRL_OP_EN 0x10243#define AP_AUX_CTRL_ADDRONLY 0x20244 245#define AP_AUX_BUFF_START 0x15246#define PIXEL_CLOCK_L 0x25247#define PIXEL_CLOCK_H 0x26248 249#define AP_AUX_COMMAND 0x27 /* com+len */250#define LENGTH_SHIFT 4251#define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd))252 253/* Bit 0&1: 3D video structure */254/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */255#define AP_AV_STATUS 0x28256#define AP_VIDEO_CHG BIT(2)257#define AP_AUDIO_CHG BIT(3)258#define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */259#define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */260#define AP_DISABLE_PD BIT(6)261#define AP_DISABLE_DISPLAY BIT(7)262 263#define GPIO_CTRL_2 0x49264#define HPD_SOURCE BIT(6)265 266/***************************************************************/267/* Register definition of device address 0x84 */268#define MIPI_PHY_CONTROL_3 0x03269#define MIPI_HS_PWD_CLK 7270#define MIPI_HS_RT_CLK 6271#define MIPI_PD_CLK 5272#define MIPI_CLK_RT_MANUAL_PD_EN 4273#define MIPI_CLK_HS_MANUAL_PD_EN 3274#define MIPI_CLK_DET_DET_BYPASS 2275#define MIPI_CLK_MISS_CTRL 1276#define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0277 278#define MIPI_LANE_CTRL_0 0x05279#define MIPI_TIME_HS_PRPR 0x08280 281/*282 * After MIPI RX protocol layer received video frames,283 * Protocol layer starts to reconstruct video stream from PHY284 */285#define MIPI_VIDEO_STABLE_CNT 0x0A286 287#define MIPI_LANE_CTRL_10 0x0F288#define MIPI_DIGITAL_ADJ_1 0x1B289#define IVO_MID 0x26CF290 291#define MIPI_PLL_M_NUM_23_16 0x1E292#define MIPI_PLL_M_NUM_15_8 0x1F293#define MIPI_PLL_M_NUM_7_0 0x20294#define MIPI_PLL_N_NUM_23_16 0x21295#define MIPI_PLL_N_NUM_15_8 0x22296#define MIPI_PLL_N_NUM_7_0 0x23297 298#define MIPI_DIGITAL_PLL_6 0x2A299/* Bit[7:6]: VCO band control, only effective */300#define MIPI_M_NUM_READY 0x10301#define MIPI_N_NUM_READY 0x08302#define STABLE_INTEGER_CNT_EN 0x04303#define MIPI_PLL_TEST_BIT 0304/* Bit[1:0]: test point output select - */305/* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */306 307#define MIPI_DIGITAL_PLL_7 0x2B308#define MIPI_PLL_FORCE_N_EN 7309#define MIPI_PLL_FORCE_BAND_EN 6310 311#define MIPI_PLL_VCO_TUNE_REG 4312/* Bit[5:4]: VCO metal capacitance - */313/* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */314#define MIPI_PLL_VCO_TUNE_REG_VAL 0x30315 316#define MIPI_PLL_PLL_LDO_BIT 2317/* Bit[3:2]: vco_v2i power - */318/* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */319#define MIPI_PLL_RESET_N 0x02320#define MIPI_FRQ_FORCE_NDET 0321 322#define MIPI_ALERT_CLR_0 0x2D323#define HS_link_error_clear 7324/* This bit itself is S/C, and it clears 0x84:0x31[7] */325 326#define MIPI_ALERT_OUT_0 0x31327#define check_sum_err_hs_sync 7328/* This bit is cleared by 0x84:0x2D[7] */329 330#define MIPI_DIGITAL_PLL_8 0x33331#define MIPI_POST_DIV_VAL 4332/* N means divided by (n+1), n = 0~15 */333#define MIPI_EN_LOCK_FRZ 3334#define MIPI_FRQ_COUNTER_RST 2335#define MIPI_FRQ_SET_REG_8 1336/* Bit 0 is reserved */337 338#define MIPI_DIGITAL_PLL_9 0x34339 340#define MIPI_DIGITAL_PLL_16 0x3B341#define MIPI_FRQ_FREEZE_NDET 7342#define MIPI_FRQ_REG_SET_ENABLE 6343#define MIPI_REG_FORCE_SEL_EN 5344#define MIPI_REG_SEL_DIV_REG 4345#define MIPI_REG_FORCE_PRE_DIV_EN 3346/* Bit 2 is reserved */347#define MIPI_FREF_D_IND 1348#define REF_CLK_27000KHZ 1349#define REF_CLK_19200KHZ 0350#define MIPI_REG_PLL_PLL_TEST_ENABLE 0351 352#define MIPI_DIGITAL_PLL_18 0x3D353#define FRQ_COUNT_RB_SEL 7354#define REG_FORCE_POST_DIV_EN 6355#define MIPI_DPI_SELECT 5356#define SELECT_DSI 1357#define SELECT_DPI 0358#define REG_BAUD_DIV_RATIO 0359 360#define H_BLANK_L 0x3E361/* For DSC only */362#define H_BLANK_H 0x3F363/* For DSC only; note: bit[7:6] are reserved */364#define MIPI_SWAP 0x4A365#define MIPI_SWAP_CH0 7366#define MIPI_SWAP_CH1 6367#define MIPI_SWAP_CH2 5368#define MIPI_SWAP_CH3 4369#define MIPI_SWAP_CLK 3370/* Bit[2:0] are reserved */371 372/******** END of I2C Address 0x84 *********/373 374/* DPCD regs */375#define DPCD_DPCD_REV 0x00376#define DPCD_MAX_LINK_RATE 0x01377#define DPCD_MAX_LANE_COUNT 0x02378 379/********* ANX7625 Register End **********/380 381/***************** Display *****************/382enum audio_fs {383 AUDIO_FS_441K = 0x00,384 AUDIO_FS_48K = 0x02,385 AUDIO_FS_32K = 0x03,386 AUDIO_FS_882K = 0x08,387 AUDIO_FS_96K = 0x0a,388 AUDIO_FS_1764K = 0x0c,389 AUDIO_FS_192K = 0x0e390};391 392enum audio_wd_len {393 AUDIO_W_LEN_16_20MAX = 0x02,394 AUDIO_W_LEN_18_20MAX = 0x04,395 AUDIO_W_LEN_17_20MAX = 0x0c,396 AUDIO_W_LEN_19_20MAX = 0x08,397 AUDIO_W_LEN_20_20MAX = 0x0a,398 AUDIO_W_LEN_20_24MAX = 0x03,399 AUDIO_W_LEN_22_24MAX = 0x05,400 AUDIO_W_LEN_21_24MAX = 0x0d,401 AUDIO_W_LEN_23_24MAX = 0x09,402 AUDIO_W_LEN_24_24MAX = 0x0b403};404 405#define I2S_CH_2 0x01406#define TDM_CH_4 0x03407#define TDM_CH_6 0x05408#define TDM_CH_8 0x07409 410#define MAX_DPCD_BUFFER_SIZE 16411 412#define ONE_BLOCK_SIZE 128413#define FOUR_BLOCK_SIZE (128 * 4)414 415#define MAX_EDID_BLOCK 3416#define EDID_TRY_CNT 3417#define SUPPORT_PIXEL_CLOCK 300000418 419/***************** Display End *****************/420 421#define MAX_LANES_SUPPORT 4422 423struct anx7625_platform_data {424 struct gpio_desc *gpio_p_on;425 struct gpio_desc *gpio_reset;426 struct regulator_bulk_data supplies[3];427 struct drm_bridge *panel_bridge;428 int intp_irq;429 int is_dpi;430 int mipi_lanes;431 int audio_en;432 int dp_lane0_swing_reg_cnt;433 u8 lane0_reg_data[DP_TX_SWING_REG_CNT];434 int dp_lane1_swing_reg_cnt;435 u8 lane1_reg_data[DP_TX_SWING_REG_CNT];436 u32 low_power_mode;437 struct device_node *mipi_host_node;438};439 440struct anx7625_i2c_client {441 struct i2c_client *tx_p0_client;442 struct i2c_client *tx_p1_client;443 struct i2c_client *tx_p2_client;444 struct i2c_client *rx_p0_client;445 struct i2c_client *rx_p1_client;446 struct i2c_client *rx_p2_client;447 struct i2c_client *tcpc_client;448};449 450struct anx7625_data {451 struct anx7625_platform_data pdata;452 struct platform_device *audio_pdev;453 int hpd_status;454 int hpd_high_cnt;455 int dp_en;456 int hdcp_cp;457 /* Lock for work queue */458 struct mutex lock;459 struct device *dev;460 struct anx7625_i2c_client i2c;461 struct i2c_client *last_client;462 struct timer_list hdcp_timer;463 const struct drm_edid *cached_drm_edid;464 struct device *codec_dev;465 hdmi_codec_plugged_cb plugged_cb;466 struct work_struct work;467 struct workqueue_struct *workqueue;468 struct delayed_work hdcp_work;469 struct workqueue_struct *hdcp_workqueue;470 /* Lock for hdcp work queue */471 struct mutex hdcp_wq_lock;472 /* Lock for aux transfer and disable */473 struct mutex aux_lock;474 char edid_block;475 struct display_timing dt;476 u8 display_timing_valid;477 struct drm_bridge bridge;478 u8 bridge_attached;479 struct drm_connector *connector;480 struct mipi_dsi_device *dsi;481 struct drm_dp_aux aux;482};483 484#endif /* __ANX7625_H__ */485