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1# SPDX-License-Identifier: GPL-2.0-only2config DRM_CDNS_DSI3 tristate "Cadence DPI/DSI bridge"4 select DRM_KMS_HELPER5 select DRM_MIPI_DSI6 select DRM_PANEL_BRIDGE7 select GENERIC_PHY8 select GENERIC_PHY_MIPI_DPHY9 depends on OF10 help11 Support Cadence DPI to DSI bridge. This is an internal12 bridge and is meant to be directly embedded in a SoC.13 14if DRM_CDNS_DSI15 16config DRM_CDNS_DSI_J721E17 bool "J721E Cadence DSI wrapper support"18 default y19 help20 Support J721E Cadence DSI wrapper. The wrapper manages21 the routing of the DSS DPI signal to the Cadence DSI.22endif23 24config DRM_CDNS_MHDP854625 tristate "Cadence DPI/DP bridge"26 select DRM_DISPLAY_DP_HELPER27 select DRM_DISPLAY_HDCP_HELPER28 select DRM_DISPLAY_HELPER29 select DRM_KMS_HELPER30 select DRM_PANEL_BRIDGE31 depends on OF32 help33 Support Cadence DPI to DP bridge. This is an internal34 bridge and is meant to be directly embedded in a SoC.35 It takes a DPI stream as input and outputs it encoded36 in DP format.37 38if DRM_CDNS_MHDP854639 40config DRM_CDNS_MHDP8546_J721E41 depends on ARCH_K3 || COMPILE_TEST42 bool "J721E Cadence DPI/DP wrapper support"43 default y44 help45 Support J721E Cadence DPI/DP wrapper. This is a wrapper46 which adds support for J721E related platform ops. It47 initializes the J721E Display Port and sets up the48 clock and data muxes.49endif50