824 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright (C) 2020 Amarula Solutions(India)4 * Author: Jagan Teki <jagan@amarulasolutions.com>5 */6 7#include <drm/drm_atomic_helper.h>8#include <drm/drm_of.h>9#include <drm/drm_print.h>10#include <drm/drm_mipi_dsi.h>11 12#include <linux/bitfield.h>13#include <linux/bits.h>14#include <linux/clk.h>15#include <linux/delay.h>16#include <linux/gpio/consumer.h>17#include <linux/i2c.h>18#include <linux/media-bus-format.h>19#include <linux/module.h>20#include <linux/of.h>21#include <linux/regmap.h>22#include <linux/regulator/consumer.h>23 24#define VENDOR_ID 0x0025#define DEVICE_ID_H 0x0126#define DEVICE_ID_L 0x0227#define VERSION_ID 0x0328#define FIRMWARE_VERSION 0x0829#define CONFIG_FINISH 0x0930#define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */31#define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */32#define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */33#define SYS_CTRL_1_CLK_PHASE_MSK GENMASK(5, 4)34#define CLK_PHASE_0 035#define CLK_PHASE_1_4 136#define CLK_PHASE_1_2 237#define CLK_PHASE_3_4 338#define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */39#define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */40#define RGB_TEST_CTRL 0x1e41#define ATE_PLL_EN 0x1f42#define HACTIVE_LI 0x2043#define VACTIVE_LI 0x2144#define VACTIVE_HACTIVE_HI 0x2245#define HFP_LI 0x2346#define HSYNC_LI 0x2447#define HBP_LI 0x2548#define HFP_HSW_HBP_HI 0x2649#define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4)50#define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6)51#define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8)52#define VFP 0x2753#define VSYNC 0x2854#define VBP 0x2955#define BIST_POL 0x2a56#define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4)57#define BIST_POL_BIST_GEN BIT(3)58#define BIST_POL_HSYNC_POL BIT(2)59#define BIST_POL_VSYNC_POL BIT(1)60#define BIST_POL_DE_POL BIT(0)61#define BIST_RED 0x2b62#define BIST_GREEN 0x2c63#define BIST_BLUE 0x2d64#define BIST_CHESS_X 0x2e65#define BIST_CHESS_Y 0x2f66#define BIST_CHESS_XY_H 0x3067#define BIST_FRAME_TIME_L 0x3168#define BIST_FRAME_TIME_H 0x3269#define FIFO_MAX_ADDR_LOW 0x3370#define SYNC_EVENT_DLY 0x3471#define HSW_MIN 0x3572#define HFP_MIN 0x3673#define LOGIC_RST_NUM 0x3774#define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */75#define BG_CTRL 0x4e76#define LDO_PLL 0x4f77#define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */78#define PLL_CTRL_6_EXTERNAL 0x9079#define PLL_CTRL_6_MIPI_CLK 0x9280#define PLL_CTRL_6_INTERNAL 0x9381#define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */82#define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */83#define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */84#define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */85#define PLL_REF_DIV 0x6b86#define PLL_REF_DIV_P(n) ((n) & 0xf)87#define PLL_REF_DIV_Pe BIT(4)88#define PLL_REF_DIV_S(n) (((n) & 0x7) << 5)89#define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */90#define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */91#define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */92#define GPIO_OEN 0x7993#define MIPI_CFG_PW 0x7a94#define MIPI_CFG_PW_CONFIG_DSI 0xc195#define MIPI_CFG_PW_CONFIG_I2C 0x3e96#define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */97#define IRQ_SEL 0x7d98#define DBG_SEL 0x7e99#define DBG_SIGNAL 0x7f100#define MIPI_ERR_VECTOR_L 0x80101#define MIPI_ERR_VECTOR_H 0x81102#define MIPI_ERR_VECTOR_EN_L 0x82103#define MIPI_ERR_VECTOR_EN_H 0x83104#define MIPI_MAX_SIZE_L 0x84105#define MIPI_MAX_SIZE_H 0x85106#define DSI_CTRL 0x86107#define DSI_CTRL_UNKNOWN 0x28108#define DSI_CTRL_DSI_LANES(n) ((n) & 0x3)109#define MIPI_PN_SWAP 0x87110#define MIPI_PN_SWAP_CLK BIT(4)111#define MIPI_PN_SWAP_D(n) BIT((n) & 0x3)112#define MIPI_SOT_SYNC_BIT(n) (0x88 + ((n) & 0x1)) /* 0..1 */113#define MIPI_ULPS_CTRL 0x8a114#define MIPI_CLK_CHK_VAR 0x8e115#define MIPI_CLK_CHK_INI 0x8f116#define MIPI_T_TERM_EN 0x90117#define MIPI_T_HS_SETTLE 0x91118#define MIPI_T_TA_SURE_PRE 0x92119#define MIPI_T_LPX_SET 0x94120#define MIPI_T_CLK_MISS 0x95121#define MIPI_INIT_TIME_L 0x96122#define MIPI_INIT_TIME_H 0x97123#define MIPI_T_CLK_TERM_EN 0x99124#define MIPI_T_CLK_SETTLE 0x9a125#define MIPI_TO_HS_RX_L 0x9e126#define MIPI_TO_HS_RX_H 0x9f127#define MIPI_PHY(n) (0xa0 + ((n) & 0x7)) /* 0..5 */128#define MIPI_PD_RX 0xb0129#define MIPI_PD_TERM 0xb1130#define MIPI_PD_HSRX 0xb2131#define MIPI_PD_LPTX 0xb3132#define MIPI_PD_LPRX 0xb4133#define MIPI_PD_CK_LANE 0xb5134#define MIPI_FORCE_0 0xb6135#define MIPI_RST_CTRL 0xb7136#define MIPI_RST_NUM 0xb8137#define MIPI_DBG_SET(n) (0xc0 + ((n) & 0xf)) /* 0..9 */138#define MIPI_DBG_SEL 0xe0139#define MIPI_DBG_DATA 0xe1140#define MIPI_ATE_TEST_SEL 0xe2141#define MIPI_ATE_STATUS(n) (0xe3 + ((n) & 0x1)) /* 0..1 */142 143struct chipone {144 struct device *dev;145 struct regmap *regmap;146 struct i2c_client *client;147 struct drm_bridge bridge;148 struct drm_display_mode mode;149 struct drm_bridge *panel_bridge;150 struct mipi_dsi_device *dsi;151 struct gpio_desc *enable_gpio;152 struct regulator *vdd1;153 struct regulator *vdd2;154 struct regulator *vdd3;155 struct clk *refclk;156 unsigned long refclk_rate;157 bool interface_i2c;158};159 160static const struct regmap_range chipone_dsi_readable_ranges[] = {161 regmap_reg_range(VENDOR_ID, VERSION_ID),162 regmap_reg_range(FIRMWARE_VERSION, PLL_SSC_OFFSET(3)),163 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),164 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),165 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),166 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),167 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)),168 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),169 regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)),170 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)),171};172 173static const struct regmap_access_table chipone_dsi_readable_table = {174 .yes_ranges = chipone_dsi_readable_ranges,175 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_readable_ranges),176};177 178static const struct regmap_range chipone_dsi_writeable_ranges[] = {179 regmap_reg_range(CONFIG_FINISH, PLL_SSC_OFFSET(3)),180 regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),181 regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),182 regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),183 regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),184 regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)),185 regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),186 regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)),187 regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)),188};189 190static const struct regmap_access_table chipone_dsi_writeable_table = {191 .yes_ranges = chipone_dsi_writeable_ranges,192 .n_yes_ranges = ARRAY_SIZE(chipone_dsi_writeable_ranges),193};194 195static const struct regmap_config chipone_regmap_config = {196 .reg_bits = 8,197 .val_bits = 8,198 .rd_table = &chipone_dsi_readable_table,199 .wr_table = &chipone_dsi_writeable_table,200 .cache_type = REGCACHE_MAPLE,201 .max_register = MIPI_ATE_STATUS(1),202};203 204static int chipone_dsi_read(void *context,205 const void *reg, size_t reg_size,206 void *val, size_t val_size)207{208 struct mipi_dsi_device *dsi = context;209 const u16 reg16 = (val_size << 8) | *(u8 *)reg;210 int ret;211 212 ret = mipi_dsi_generic_read(dsi, ®16, 2, val, val_size);213 214 return ret == val_size ? 0 : -EINVAL;215}216 217static int chipone_dsi_write(void *context, const void *data, size_t count)218{219 struct mipi_dsi_device *dsi = context;220 221 return mipi_dsi_generic_write(dsi, data, 2);222}223 224static const struct regmap_bus chipone_dsi_regmap_bus = {225 .read = chipone_dsi_read,226 .write = chipone_dsi_write,227 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,228 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,229};230 231static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)232{233 return container_of(bridge, struct chipone, bridge);234}235 236static void chipone_readb(struct chipone *icn, u8 reg, u8 *val)237{238 int ret, pval;239 240 ret = regmap_read(icn->regmap, reg, &pval);241 242 *val = ret ? 0 : pval & 0xff;243}244 245static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)246{247 return regmap_write(icn->regmap, reg, val);248}249 250static void chipone_configure_pll(struct chipone *icn,251 const struct drm_display_mode *mode)252{253 unsigned int best_p = 0, best_m = 0, best_s = 0;254 unsigned int mode_clock = mode->clock * 1000;255 unsigned int delta, min_delta = 0xffffffff;256 unsigned int freq_p, freq_s, freq_out;257 unsigned int p_min, p_max;258 unsigned int p, m, s;259 unsigned int fin;260 bool best_p_pot;261 u8 ref_div;262 263 /*264 * DSI byte clock frequency (input into PLL) is calculated as:265 * DSI_CLK = HS clock / 4266 *267 * DPI pixel clock frequency (output from PLL) is mode clock.268 *269 * The chip contains fractional PLL which works as follows:270 * DPI_CLK = ((DSI_CLK / P) * M) / S271 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider272 * register PLL_REF_DIV[4] is extra 1:2 divider273 * M is integer multiplier, register PLL_INT(0) is multiplier274 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider275 *276 * It seems the PLL input clock after applying P pre-divider have277 * to be lower than 20 MHz.278 */279 if (icn->refclk)280 fin = icn->refclk_rate;281 else282 fin = icn->dsi->hs_rate / 4; /* in Hz */283 284 /* Minimum value of P predivider for PLL input in 5..20 MHz */285 p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U);286 p_max = clamp(fin / 5000000, 1U, 31U);287 288 for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */289 if (p > 16 && p & 1) /* P > 16 uses extra /2 */290 continue;291 freq_p = fin / p;292 if (freq_p == 0) /* Divider too high */293 break;294 295 for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */296 freq_s = freq_p / BIT(s + 1);297 if (freq_s == 0) /* Divider too high */298 break;299 300 m = mode_clock / freq_s;301 302 /* Multiplier is 8 bit */303 if (m > 0xff)304 continue;305 306 /* Limit PLL VCO frequency to 1 GHz */307 freq_out = (fin * m) / p;308 if (freq_out > 1000000000)309 continue;310 311 /* Apply post-divider */312 freq_out /= BIT(s + 1);313 314 delta = abs(mode_clock - freq_out);315 if (delta < min_delta) {316 best_p = p;317 best_m = m;318 best_s = s;319 min_delta = delta;320 }321 }322 }323 324 best_p_pot = !(best_p & 1);325 326 dev_dbg(icn->dev,327 "PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in(%s)=%d Hz ; DPI f_out=%d Hz\n",328 best_p >> best_p_pot, best_p_pot, best_m, best_s + 1,329 min_delta, icn->refclk ? "EXT" : "DSI", fin,330 (fin * best_m) / (best_p << (best_s + 1)));331 332 ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s);333 if (best_p_pot) /* Prefer /2 pre-divider */334 ref_div |= PLL_REF_DIV_Pe;335 336 /* Clock source selection either external clock or MIPI DSI clock lane */337 chipone_writeb(icn, PLL_CTRL(6),338 icn->refclk ? PLL_CTRL_6_EXTERNAL : PLL_CTRL_6_MIPI_CLK);339 chipone_writeb(icn, PLL_REF_DIV, ref_div);340 chipone_writeb(icn, PLL_INT(0), best_m);341}342 343static void chipone_atomic_enable(struct drm_bridge *bridge,344 struct drm_bridge_state *old_bridge_state)345{346 struct chipone *icn = bridge_to_chipone(bridge);347 struct drm_atomic_state *state = old_bridge_state->base.state;348 struct drm_display_mode *mode = &icn->mode;349 const struct drm_bridge_state *bridge_state;350 u16 hfp, hbp, hsync;351 u32 bus_flags;352 u8 pol, sys_ctrl_1, id[4];353 354 chipone_readb(icn, VENDOR_ID, id);355 chipone_readb(icn, DEVICE_ID_H, id + 1);356 chipone_readb(icn, DEVICE_ID_L, id + 2);357 chipone_readb(icn, VERSION_ID, id + 3);358 359 dev_dbg(icn->dev,360 "Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n",361 id[0], id[1], id[2], id[3]);362 363 if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) {364 dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");365 return;366 }367 368 /* Get the DPI flags from the bridge state. */369 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);370 bus_flags = bridge_state->output_bus_cfg.flags;371 372 if (icn->interface_i2c)373 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);374 else375 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);376 377 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);378 379 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);380 381 /*382 * lsb nibble: 2nd nibble of hdisplay383 * msb nibble: 2nd nibble of vdisplay384 */385 chipone_writeb(icn, VACTIVE_HACTIVE_HI,386 ((mode->hdisplay >> 8) & 0xf) |387 (((mode->vdisplay >> 8) & 0xf) << 4));388 389 hfp = mode->hsync_start - mode->hdisplay;390 hsync = mode->hsync_end - mode->hsync_start;391 hbp = mode->htotal - mode->hsync_end;392 393 chipone_writeb(icn, HFP_LI, hfp & 0xff);394 chipone_writeb(icn, HSYNC_LI, hsync & 0xff);395 chipone_writeb(icn, HBP_LI, hbp & 0xff);396 /* Top two bits of Horizontal Front porch/Sync/Back porch */397 chipone_writeb(icn, HFP_HSW_HBP_HI,398 HFP_HSW_HBP_HI_HFP(hfp) |399 HFP_HSW_HBP_HI_HS(hsync) |400 HFP_HSW_HBP_HI_HBP(hbp));401 402 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);403 404 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);405 406 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);407 408 /* dsi specific sequence */409 chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);410 chipone_writeb(icn, HFP_MIN, hfp & 0xff);411 412 /* DSI data lane count */413 chipone_writeb(icn, DSI_CTRL,414 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));415 416 chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);417 chipone_writeb(icn, PLL_CTRL(12), 0xff);418 chipone_writeb(icn, MIPI_PN_SWAP, 0x00);419 420 /* DPI HS/VS/DE polarity */421 pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) |422 ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) |423 ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0);424 chipone_writeb(icn, BIST_POL, pol);425 426 /* Configure PLL settings */427 chipone_configure_pll(icn, mode);428 429 chipone_writeb(icn, SYS_CTRL(0), 0x40);430 sys_ctrl_1 = 0x88;431 432 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)433 sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_0);434 else435 sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_1_2);436 437 chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1);438 439 /* icn6211 specific sequence */440 chipone_writeb(icn, MIPI_FORCE_0, 0x20);441 chipone_writeb(icn, PLL_CTRL(1), 0x20);442 chipone_writeb(icn, CONFIG_FINISH, 0x10);443 444 usleep_range(10000, 11000);445}446 447static void chipone_atomic_pre_enable(struct drm_bridge *bridge,448 struct drm_bridge_state *old_bridge_state)449{450 struct chipone *icn = bridge_to_chipone(bridge);451 int ret;452 453 if (icn->vdd1) {454 ret = regulator_enable(icn->vdd1);455 if (ret)456 DRM_DEV_ERROR(icn->dev,457 "failed to enable VDD1 regulator: %d\n", ret);458 }459 460 if (icn->vdd2) {461 ret = regulator_enable(icn->vdd2);462 if (ret)463 DRM_DEV_ERROR(icn->dev,464 "failed to enable VDD2 regulator: %d\n", ret);465 }466 467 if (icn->vdd3) {468 ret = regulator_enable(icn->vdd3);469 if (ret)470 DRM_DEV_ERROR(icn->dev,471 "failed to enable VDD3 regulator: %d\n", ret);472 }473 474 ret = clk_prepare_enable(icn->refclk);475 if (ret)476 DRM_DEV_ERROR(icn->dev,477 "failed to enable RECLK clock: %d\n", ret);478 479 gpiod_set_value(icn->enable_gpio, 1);480 481 usleep_range(10000, 11000);482}483 484static void chipone_atomic_post_disable(struct drm_bridge *bridge,485 struct drm_bridge_state *old_bridge_state)486{487 struct chipone *icn = bridge_to_chipone(bridge);488 489 clk_disable_unprepare(icn->refclk);490 491 if (icn->vdd1)492 regulator_disable(icn->vdd1);493 494 if (icn->vdd2)495 regulator_disable(icn->vdd2);496 497 if (icn->vdd3)498 regulator_disable(icn->vdd3);499 500 gpiod_set_value(icn->enable_gpio, 0);501}502 503static void chipone_mode_set(struct drm_bridge *bridge,504 const struct drm_display_mode *mode,505 const struct drm_display_mode *adjusted_mode)506{507 struct chipone *icn = bridge_to_chipone(bridge);508 509 drm_mode_copy(&icn->mode, adjusted_mode);510};511 512static int chipone_dsi_attach(struct chipone *icn)513{514 struct mipi_dsi_device *dsi = icn->dsi;515 struct device *dev = icn->dev;516 int dsi_lanes, ret;517 518 dsi_lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);519 520 /*521 * If the 'data-lanes' property does not exist in DT or is invalid,522 * default to previously hard-coded behavior, which was 4 data lanes.523 */524 if (dsi_lanes < 0)525 icn->dsi->lanes = 4;526 else527 icn->dsi->lanes = dsi_lanes;528 529 dsi->format = MIPI_DSI_FMT_RGB888;530 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |531 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;532 dsi->hs_rate = 500000000;533 dsi->lp_rate = 16000000;534 535 ret = mipi_dsi_attach(dsi);536 if (ret < 0)537 dev_err(icn->dev, "failed to attach dsi\n");538 539 return ret;540}541 542static int chipone_dsi_host_attach(struct chipone *icn)543{544 struct device *dev = icn->dev;545 struct device_node *host_node;546 struct device_node *endpoint;547 struct mipi_dsi_device *dsi;548 struct mipi_dsi_host *host;549 int ret = 0;550 551 const struct mipi_dsi_device_info info = {552 .type = "chipone",553 .channel = 0,554 .node = NULL,555 };556 557 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);558 host_node = of_graph_get_remote_port_parent(endpoint);559 of_node_put(endpoint);560 561 if (!host_node)562 return -EINVAL;563 564 host = of_find_mipi_dsi_host_by_node(host_node);565 of_node_put(host_node);566 if (!host)567 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");568 569 dsi = mipi_dsi_device_register_full(host, &info);570 if (IS_ERR(dsi)) {571 return dev_err_probe(dev, PTR_ERR(dsi),572 "failed to create dsi device\n");573 }574 575 icn->dsi = dsi;576 577 ret = chipone_dsi_attach(icn);578 if (ret < 0)579 mipi_dsi_device_unregister(dsi);580 581 return ret;582}583 584static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)585{586 struct chipone *icn = bridge_to_chipone(bridge);587 588 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);589}590 591#define MAX_INPUT_SEL_FORMATS 1592 593static u32 *594chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge,595 struct drm_bridge_state *bridge_state,596 struct drm_crtc_state *crtc_state,597 struct drm_connector_state *conn_state,598 u32 output_fmt,599 unsigned int *num_input_fmts)600{601 u32 *input_fmts;602 603 *num_input_fmts = 0;604 605 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),606 GFP_KERNEL);607 if (!input_fmts)608 return NULL;609 610 /* This is the DSI-end bus format */611 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;612 *num_input_fmts = 1;613 614 return input_fmts;615}616 617static const struct drm_bridge_funcs chipone_bridge_funcs = {618 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,619 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,620 .atomic_reset = drm_atomic_helper_bridge_reset,621 .atomic_pre_enable = chipone_atomic_pre_enable,622 .atomic_enable = chipone_atomic_enable,623 .atomic_post_disable = chipone_atomic_post_disable,624 .mode_set = chipone_mode_set,625 .attach = chipone_attach,626 .atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts,627};628 629static int chipone_parse_dt(struct chipone *icn)630{631 struct device *dev = icn->dev;632 int ret;633 634 icn->refclk = devm_clk_get_optional(dev, "refclk");635 if (IS_ERR(icn->refclk)) {636 ret = PTR_ERR(icn->refclk);637 DRM_DEV_ERROR(dev, "failed to get REFCLK clock: %d\n", ret);638 return ret;639 } else if (icn->refclk) {640 icn->refclk_rate = clk_get_rate(icn->refclk);641 if (icn->refclk_rate < 10000000 || icn->refclk_rate > 154000000) {642 DRM_DEV_ERROR(dev, "REFCLK out of range: %ld Hz\n",643 icn->refclk_rate);644 return -EINVAL;645 }646 }647 648 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");649 if (IS_ERR(icn->vdd1)) {650 ret = PTR_ERR(icn->vdd1);651 if (ret == -EPROBE_DEFER)652 return -EPROBE_DEFER;653 icn->vdd1 = NULL;654 DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret);655 }656 657 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");658 if (IS_ERR(icn->vdd2)) {659 ret = PTR_ERR(icn->vdd2);660 if (ret == -EPROBE_DEFER)661 return -EPROBE_DEFER;662 icn->vdd2 = NULL;663 DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret);664 }665 666 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");667 if (IS_ERR(icn->vdd3)) {668 ret = PTR_ERR(icn->vdd3);669 if (ret == -EPROBE_DEFER)670 return -EPROBE_DEFER;671 icn->vdd3 = NULL;672 DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret);673 }674 675 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);676 if (IS_ERR(icn->enable_gpio)) {677 DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");678 return PTR_ERR(icn->enable_gpio);679 }680 681 icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);682 if (IS_ERR(icn->panel_bridge))683 return PTR_ERR(icn->panel_bridge);684 685 return 0;686}687 688static int chipone_common_probe(struct device *dev, struct chipone **icnr)689{690 struct chipone *icn;691 int ret;692 693 icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);694 if (!icn)695 return -ENOMEM;696 697 icn->dev = dev;698 699 ret = chipone_parse_dt(icn);700 if (ret)701 return ret;702 703 icn->bridge.funcs = &chipone_bridge_funcs;704 icn->bridge.type = DRM_MODE_CONNECTOR_DPI;705 icn->bridge.of_node = dev->of_node;706 707 *icnr = icn;708 709 return ret;710}711 712static int chipone_dsi_probe(struct mipi_dsi_device *dsi)713{714 struct device *dev = &dsi->dev;715 struct chipone *icn;716 int ret;717 718 ret = chipone_common_probe(dev, &icn);719 if (ret)720 return ret;721 722 icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,723 dsi, &chipone_regmap_config);724 if (IS_ERR(icn->regmap))725 return PTR_ERR(icn->regmap);726 727 icn->interface_i2c = false;728 icn->dsi = dsi;729 730 mipi_dsi_set_drvdata(dsi, icn);731 732 drm_bridge_add(&icn->bridge);733 734 ret = chipone_dsi_attach(icn);735 if (ret)736 drm_bridge_remove(&icn->bridge);737 738 return ret;739}740 741static int chipone_i2c_probe(struct i2c_client *client)742{743 struct device *dev = &client->dev;744 struct chipone *icn;745 int ret;746 747 ret = chipone_common_probe(dev, &icn);748 if (ret)749 return ret;750 751 icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);752 if (IS_ERR(icn->regmap))753 return PTR_ERR(icn->regmap);754 755 icn->interface_i2c = true;756 icn->client = client;757 dev_set_drvdata(dev, icn);758 i2c_set_clientdata(client, icn);759 760 drm_bridge_add(&icn->bridge);761 762 return chipone_dsi_host_attach(icn);763}764 765static void chipone_dsi_remove(struct mipi_dsi_device *dsi)766{767 struct chipone *icn = mipi_dsi_get_drvdata(dsi);768 769 mipi_dsi_detach(dsi);770 drm_bridge_remove(&icn->bridge);771}772 773static const struct of_device_id chipone_of_match[] = {774 { .compatible = "chipone,icn6211", },775 { /* sentinel */ }776};777MODULE_DEVICE_TABLE(of, chipone_of_match);778 779static struct mipi_dsi_driver chipone_dsi_driver = {780 .probe = chipone_dsi_probe,781 .remove = chipone_dsi_remove,782 .driver = {783 .name = "chipone-icn6211",784 .of_match_table = chipone_of_match,785 },786};787 788static struct i2c_device_id chipone_i2c_id[] = {789 { "chipone,icn6211" },790 {},791};792MODULE_DEVICE_TABLE(i2c, chipone_i2c_id);793 794static struct i2c_driver chipone_i2c_driver = {795 .probe = chipone_i2c_probe,796 .id_table = chipone_i2c_id,797 .driver = {798 .name = "chipone-icn6211-i2c",799 .of_match_table = chipone_of_match,800 },801};802 803static int __init chipone_init(void)804{805 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))806 mipi_dsi_driver_register(&chipone_dsi_driver);807 808 return i2c_add_driver(&chipone_i2c_driver);809}810module_init(chipone_init);811 812static void __exit chipone_exit(void)813{814 i2c_del_driver(&chipone_i2c_driver);815 816 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))817 mipi_dsi_driver_unregister(&chipone_dsi_driver);818}819module_exit(chipone_exit);820 821MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");822MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");823MODULE_LICENSE("GPL");824