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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.4 * Copyright (c) 2019-2020. Linaro Limited.5 */6 7#include <linux/firmware.h>8#include <linux/gpio/consumer.h>9#include <linux/i2c.h>10#include <linux/interrupt.h>11#include <linux/module.h>12#include <linux/mutex.h>13#include <linux/of_graph.h>14#include <linux/platform_device.h>15#include <linux/regmap.h>16#include <linux/regulator/consumer.h>17#include <linux/wait.h>18#include <linux/workqueue.h>19 20#include <sound/hdmi-codec.h>21 22#include <drm/drm_atomic_helper.h>23#include <drm/drm_bridge.h>24#include <drm/drm_edid.h>25#include <drm/drm_mipi_dsi.h>26#include <drm/drm_of.h>27#include <drm/drm_print.h>28#include <drm/drm_probe_helper.h>29 30#define EDID_BLOCK_SIZE 12831#define EDID_NUM_BLOCKS 232 33#define FW_FILE "lt9611uxc_fw.bin"34 35struct lt9611uxc {36 struct device *dev;37 struct drm_bridge bridge;38 struct drm_bridge *next_bridge;39 40 struct regmap *regmap;41 /* Protects all accesses to registers by stopping the on-chip MCU */42 struct mutex ocm_lock;43 44 struct wait_queue_head wq;45 struct work_struct work;46 47 struct device_node *dsi0_node;48 struct device_node *dsi1_node;49 struct mipi_dsi_device *dsi0;50 struct mipi_dsi_device *dsi1;51 struct platform_device *audio_pdev;52 53 struct gpio_desc *reset_gpio;54 struct gpio_desc *enable_gpio;55 56 struct regulator_bulk_data supplies[2];57 58 struct i2c_client *client;59 60 bool hpd_supported;61 bool edid_read;62 /* can be accessed from different threads, so protect this with ocm_lock */63 bool hdmi_connected;64 uint8_t fw_version;65};66 67#define LT9611_PAGE_CONTROL 0xff68 69static const struct regmap_range_cfg lt9611uxc_ranges[] = {70 {71 .name = "register_range",72 .range_min = 0,73 .range_max = 0xd0ff,74 .selector_reg = LT9611_PAGE_CONTROL,75 .selector_mask = 0xff,76 .selector_shift = 0,77 .window_start = 0,78 .window_len = 0x100,79 },80};81 82static const struct regmap_config lt9611uxc_regmap_config = {83 .reg_bits = 8,84 .val_bits = 8,85 .max_register = 0xffff,86 .ranges = lt9611uxc_ranges,87 .num_ranges = ARRAY_SIZE(lt9611uxc_ranges),88};89 90struct lt9611uxc_mode {91 u16 hdisplay;92 u16 vdisplay;93 u8 vrefresh;94};95 96/*97 * This chip supports only a fixed set of modes.98 * Enumerate them here to check whether the mode is supported.99 */100static struct lt9611uxc_mode lt9611uxc_modes[] = {101 { 1920, 1080, 60 },102 { 1920, 1080, 30 },103 { 1920, 1080, 25 },104 { 1366, 768, 60 },105 { 1360, 768, 60 },106 { 1280, 1024, 60 },107 { 1280, 800, 60 },108 { 1280, 720, 60 },109 { 1280, 720, 50 },110 { 1280, 720, 30 },111 { 1152, 864, 60 },112 { 1024, 768, 60 },113 { 800, 600, 60 },114 { 720, 576, 50 },115 { 720, 480, 60 },116 { 640, 480, 60 },117};118 119static struct lt9611uxc *bridge_to_lt9611uxc(struct drm_bridge *bridge)120{121 return container_of(bridge, struct lt9611uxc, bridge);122}123 124static void lt9611uxc_lock(struct lt9611uxc *lt9611uxc)125{126 mutex_lock(<9611uxc->ocm_lock);127 regmap_write(lt9611uxc->regmap, 0x80ee, 0x01);128}129 130static void lt9611uxc_unlock(struct lt9611uxc *lt9611uxc)131{132 regmap_write(lt9611uxc->regmap, 0x80ee, 0x00);133 msleep(50);134 mutex_unlock(<9611uxc->ocm_lock);135}136 137static irqreturn_t lt9611uxc_irq_thread_handler(int irq, void *dev_id)138{139 struct lt9611uxc *lt9611uxc = dev_id;140 unsigned int irq_status = 0;141 unsigned int hpd_status = 0;142 143 lt9611uxc_lock(lt9611uxc);144 145 regmap_read(lt9611uxc->regmap, 0xb022, &irq_status);146 regmap_read(lt9611uxc->regmap, 0xb023, &hpd_status);147 if (irq_status)148 regmap_write(lt9611uxc->regmap, 0xb022, 0);149 150 if (irq_status & BIT(0)) {151 lt9611uxc->edid_read = !!(hpd_status & BIT(0));152 wake_up_all(<9611uxc->wq);153 }154 155 if (irq_status & BIT(1)) {156 lt9611uxc->hdmi_connected = hpd_status & BIT(1);157 schedule_work(<9611uxc->work);158 }159 160 lt9611uxc_unlock(lt9611uxc);161 162 return IRQ_HANDLED;163}164 165static void lt9611uxc_hpd_work(struct work_struct *work)166{167 struct lt9611uxc *lt9611uxc = container_of(work, struct lt9611uxc, work);168 bool connected;169 170 mutex_lock(<9611uxc->ocm_lock);171 connected = lt9611uxc->hdmi_connected;172 mutex_unlock(<9611uxc->ocm_lock);173 174 drm_bridge_hpd_notify(<9611uxc->bridge,175 connected ?176 connector_status_connected :177 connector_status_disconnected);178}179 180static void lt9611uxc_reset(struct lt9611uxc *lt9611uxc)181{182 gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1);183 msleep(20);184 185 gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 0);186 msleep(20);187 188 gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1);189 msleep(300);190}191 192static void lt9611uxc_assert_5v(struct lt9611uxc *lt9611uxc)193{194 if (!lt9611uxc->enable_gpio)195 return;196 197 gpiod_set_value_cansleep(lt9611uxc->enable_gpio, 1);198 msleep(20);199}200 201static int lt9611uxc_regulator_init(struct lt9611uxc *lt9611uxc)202{203 int ret;204 205 lt9611uxc->supplies[0].supply = "vdd";206 lt9611uxc->supplies[1].supply = "vcc";207 208 ret = devm_regulator_bulk_get(lt9611uxc->dev, 2, lt9611uxc->supplies);209 if (ret < 0)210 return ret;211 212 return regulator_set_load(lt9611uxc->supplies[0].consumer, 200000);213}214 215static int lt9611uxc_regulator_enable(struct lt9611uxc *lt9611uxc)216{217 int ret;218 219 ret = regulator_enable(lt9611uxc->supplies[0].consumer);220 if (ret < 0)221 return ret;222 223 usleep_range(1000, 10000); /* 50000 according to dtsi */224 225 ret = regulator_enable(lt9611uxc->supplies[1].consumer);226 if (ret < 0) {227 regulator_disable(lt9611uxc->supplies[0].consumer);228 return ret;229 }230 231 return 0;232}233 234static struct lt9611uxc_mode *lt9611uxc_find_mode(const struct drm_display_mode *mode)235{236 int i;237 238 for (i = 0; i < ARRAY_SIZE(lt9611uxc_modes); i++) {239 if (lt9611uxc_modes[i].hdisplay == mode->hdisplay &&240 lt9611uxc_modes[i].vdisplay == mode->vdisplay &&241 lt9611uxc_modes[i].vrefresh == drm_mode_vrefresh(mode)) {242 return <9611uxc_modes[i];243 }244 }245 246 return NULL;247}248 249static struct mipi_dsi_device *lt9611uxc_attach_dsi(struct lt9611uxc *lt9611uxc,250 struct device_node *dsi_node)251{252 const struct mipi_dsi_device_info info = { "lt9611uxc", 0, NULL };253 struct mipi_dsi_device *dsi;254 struct mipi_dsi_host *host;255 struct device *dev = lt9611uxc->dev;256 int ret;257 258 host = of_find_mipi_dsi_host_by_node(dsi_node);259 if (!host)260 return ERR_PTR(dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n"));261 262 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);263 if (IS_ERR(dsi)) {264 dev_err(dev, "failed to create dsi device\n");265 return dsi;266 }267 268 dsi->lanes = 4;269 dsi->format = MIPI_DSI_FMT_RGB888;270 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |271 MIPI_DSI_MODE_VIDEO_HSE;272 273 ret = devm_mipi_dsi_attach(dev, dsi);274 if (ret < 0) {275 dev_err(dev, "failed to attach dsi to host\n");276 return ERR_PTR(ret);277 }278 279 return dsi;280}281 282static int lt9611uxc_bridge_attach(struct drm_bridge *bridge,283 enum drm_bridge_attach_flags flags)284{285 struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge);286 287 return drm_bridge_attach(bridge->encoder, lt9611uxc->next_bridge,288 bridge, flags);289}290 291static enum drm_mode_status292lt9611uxc_bridge_mode_valid(struct drm_bridge *bridge,293 const struct drm_display_info *info,294 const struct drm_display_mode *mode)295{296 struct lt9611uxc_mode *lt9611uxc_mode;297 298 lt9611uxc_mode = lt9611uxc_find_mode(mode);299 300 return lt9611uxc_mode ? MODE_OK : MODE_BAD;301}302 303static void lt9611uxc_video_setup(struct lt9611uxc *lt9611uxc,304 const struct drm_display_mode *mode)305{306 u32 h_total, hactive, hsync_len, hfront_porch;307 u32 v_total, vactive, vsync_len, vfront_porch;308 309 h_total = mode->htotal;310 v_total = mode->vtotal;311 312 hactive = mode->hdisplay;313 hsync_len = mode->hsync_end - mode->hsync_start;314 hfront_porch = mode->hsync_start - mode->hdisplay;315 316 vactive = mode->vdisplay;317 vsync_len = mode->vsync_end - mode->vsync_start;318 vfront_porch = mode->vsync_start - mode->vdisplay;319 320 regmap_write(lt9611uxc->regmap, 0xd00d, (u8)(v_total / 256));321 regmap_write(lt9611uxc->regmap, 0xd00e, (u8)(v_total % 256));322 323 regmap_write(lt9611uxc->regmap, 0xd00f, (u8)(vactive / 256));324 regmap_write(lt9611uxc->regmap, 0xd010, (u8)(vactive % 256));325 326 regmap_write(lt9611uxc->regmap, 0xd011, (u8)(h_total / 256));327 regmap_write(lt9611uxc->regmap, 0xd012, (u8)(h_total % 256));328 329 regmap_write(lt9611uxc->regmap, 0xd013, (u8)(hactive / 256));330 regmap_write(lt9611uxc->regmap, 0xd014, (u8)(hactive % 256));331 332 regmap_write(lt9611uxc->regmap, 0xd015, (u8)(vsync_len % 256));333 334 regmap_update_bits(lt9611uxc->regmap, 0xd016, 0xf, (u8)(hsync_len / 256));335 regmap_write(lt9611uxc->regmap, 0xd017, (u8)(hsync_len % 256));336 337 regmap_update_bits(lt9611uxc->regmap, 0xd018, 0xf, (u8)(vfront_porch / 256));338 regmap_write(lt9611uxc->regmap, 0xd019, (u8)(vfront_porch % 256));339 340 regmap_update_bits(lt9611uxc->regmap, 0xd01a, 0xf, (u8)(hfront_porch / 256));341 regmap_write(lt9611uxc->regmap, 0xd01b, (u8)(hfront_porch % 256));342}343 344static void lt9611uxc_bridge_mode_set(struct drm_bridge *bridge,345 const struct drm_display_mode *mode,346 const struct drm_display_mode *adj_mode)347{348 struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge);349 350 lt9611uxc_lock(lt9611uxc);351 lt9611uxc_video_setup(lt9611uxc, mode);352 lt9611uxc_unlock(lt9611uxc);353}354 355static enum drm_connector_status lt9611uxc_bridge_detect(struct drm_bridge *bridge)356{357 struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge);358 unsigned int reg_val = 0;359 int ret;360 bool connected = true;361 362 lt9611uxc_lock(lt9611uxc);363 364 if (lt9611uxc->hpd_supported) {365 ret = regmap_read(lt9611uxc->regmap, 0xb023, ®_val);366 367 if (ret)368 dev_err(lt9611uxc->dev, "failed to read hpd status: %d\n", ret);369 else370 connected = reg_val & BIT(1);371 }372 lt9611uxc->hdmi_connected = connected;373 374 lt9611uxc_unlock(lt9611uxc);375 376 return connected ? connector_status_connected :377 connector_status_disconnected;378}379 380static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc)381{382 return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read,383 msecs_to_jiffies(500));384}385 386static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)387{388 struct lt9611uxc *lt9611uxc = data;389 int ret;390 391 if (len > EDID_BLOCK_SIZE)392 return -EINVAL;393 394 if (block >= EDID_NUM_BLOCKS)395 return -EINVAL;396 397 lt9611uxc_lock(lt9611uxc);398 399 regmap_write(lt9611uxc->regmap, 0xb00b, 0x10);400 401 regmap_write(lt9611uxc->regmap, 0xb00a, block * EDID_BLOCK_SIZE);402 403 ret = regmap_noinc_read(lt9611uxc->regmap, 0xb0b0, buf, len);404 if (ret)405 dev_err(lt9611uxc->dev, "edid read failed: %d\n", ret);406 407 lt9611uxc_unlock(lt9611uxc);408 409 return 0;410};411 412static const struct drm_edid *lt9611uxc_bridge_edid_read(struct drm_bridge *bridge,413 struct drm_connector *connector)414{415 struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge);416 int ret;417 418 ret = lt9611uxc_wait_for_edid(lt9611uxc);419 if (ret < 0) {420 dev_err(lt9611uxc->dev, "wait for EDID failed: %d\n", ret);421 return NULL;422 } else if (ret == 0) {423 dev_err(lt9611uxc->dev, "wait for EDID timeout\n");424 return NULL;425 }426 427 return drm_edid_read_custom(connector, lt9611uxc_get_edid_block, lt9611uxc);428}429 430static const struct drm_bridge_funcs lt9611uxc_bridge_funcs = {431 .attach = lt9611uxc_bridge_attach,432 .mode_valid = lt9611uxc_bridge_mode_valid,433 .mode_set = lt9611uxc_bridge_mode_set,434 .detect = lt9611uxc_bridge_detect,435 .edid_read = lt9611uxc_bridge_edid_read,436};437 438static int lt9611uxc_parse_dt(struct device *dev,439 struct lt9611uxc *lt9611uxc)440{441 lt9611uxc->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1);442 if (!lt9611uxc->dsi0_node) {443 dev_err(lt9611uxc->dev, "failed to get remote node for primary dsi\n");444 return -ENODEV;445 }446 447 lt9611uxc->dsi1_node = of_graph_get_remote_node(dev->of_node, 1, -1);448 449 return drm_of_find_panel_or_bridge(dev->of_node, 2, -1, NULL, <9611uxc->next_bridge);450}451 452static int lt9611uxc_gpio_init(struct lt9611uxc *lt9611uxc)453{454 struct device *dev = lt9611uxc->dev;455 456 lt9611uxc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);457 if (IS_ERR(lt9611uxc->reset_gpio)) {458 dev_err(dev, "failed to acquire reset gpio\n");459 return PTR_ERR(lt9611uxc->reset_gpio);460 }461 462 lt9611uxc->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);463 if (IS_ERR(lt9611uxc->enable_gpio)) {464 dev_err(dev, "failed to acquire enable gpio\n");465 return PTR_ERR(lt9611uxc->enable_gpio);466 }467 468 return 0;469}470 471static int lt9611uxc_read_device_rev(struct lt9611uxc *lt9611uxc)472{473 unsigned int rev0, rev1, rev2;474 int ret;475 476 lt9611uxc_lock(lt9611uxc);477 478 ret = regmap_read(lt9611uxc->regmap, 0x8100, &rev0);479 ret |= regmap_read(lt9611uxc->regmap, 0x8101, &rev1);480 ret |= regmap_read(lt9611uxc->regmap, 0x8102, &rev2);481 if (ret)482 dev_err(lt9611uxc->dev, "failed to read revision: %d\n", ret);483 else484 dev_info(lt9611uxc->dev, "LT9611 revision: 0x%02x.%02x.%02x\n", rev0, rev1, rev2);485 486 lt9611uxc_unlock(lt9611uxc);487 488 return ret;489}490 491static int lt9611uxc_read_version(struct lt9611uxc *lt9611uxc)492{493 unsigned int rev;494 int ret;495 496 lt9611uxc_lock(lt9611uxc);497 498 ret = regmap_read(lt9611uxc->regmap, 0xb021, &rev);499 if (ret)500 dev_err(lt9611uxc->dev, "failed to read revision: %d\n", ret);501 else502 dev_info(lt9611uxc->dev, "LT9611 version: 0x%02x\n", rev);503 504 lt9611uxc_unlock(lt9611uxc);505 506 return ret < 0 ? ret : rev;507}508 509static int lt9611uxc_hdmi_hw_params(struct device *dev, void *data,510 struct hdmi_codec_daifmt *fmt,511 struct hdmi_codec_params *hparms)512{513 /*514 * LT9611UXC will automatically detect rate and sample size, so no need515 * to setup anything here.516 */517 return 0;518}519 520static void lt9611uxc_audio_shutdown(struct device *dev, void *data)521{522}523 524static int lt9611uxc_hdmi_i2s_get_dai_id(struct snd_soc_component *component,525 struct device_node *endpoint)526{527 struct of_endpoint of_ep;528 int ret;529 530 ret = of_graph_parse_endpoint(endpoint, &of_ep);531 if (ret < 0)532 return ret;533 534 /*535 * HDMI sound should be located as reg = <2>536 * Then, it is sound port 0537 */538 if (of_ep.port == 2)539 return 0;540 541 return -EINVAL;542}543 544static const struct hdmi_codec_ops lt9611uxc_codec_ops = {545 .hw_params = lt9611uxc_hdmi_hw_params,546 .audio_shutdown = lt9611uxc_audio_shutdown,547 .get_dai_id = lt9611uxc_hdmi_i2s_get_dai_id,548};549 550static int lt9611uxc_audio_init(struct device *dev, struct lt9611uxc *lt9611uxc)551{552 struct hdmi_codec_pdata codec_data = {553 .ops = <9611uxc_codec_ops,554 .max_i2s_channels = 2,555 .i2s = 1,556 .data = lt9611uxc,557 };558 559 lt9611uxc->audio_pdev =560 platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,561 PLATFORM_DEVID_AUTO,562 &codec_data, sizeof(codec_data));563 564 return PTR_ERR_OR_ZERO(lt9611uxc->audio_pdev);565}566 567static void lt9611uxc_audio_exit(struct lt9611uxc *lt9611uxc)568{569 if (lt9611uxc->audio_pdev) {570 platform_device_unregister(lt9611uxc->audio_pdev);571 lt9611uxc->audio_pdev = NULL;572 }573}574 575#define LT9611UXC_FW_PAGE_SIZE 32576static void lt9611uxc_firmware_write_page(struct lt9611uxc *lt9611uxc, u16 addr, const u8 *buf)577{578 struct reg_sequence seq_write_prepare[] = {579 REG_SEQ0(0x805a, 0x04),580 REG_SEQ0(0x805a, 0x00),581 582 REG_SEQ0(0x805e, 0xdf),583 REG_SEQ0(0x805a, 0x20),584 REG_SEQ0(0x805a, 0x00),585 REG_SEQ0(0x8058, 0x21),586 };587 588 struct reg_sequence seq_write_addr[] = {589 REG_SEQ0(0x805b, (addr >> 16) & 0xff),590 REG_SEQ0(0x805c, (addr >> 8) & 0xff),591 REG_SEQ0(0x805d, addr & 0xff),592 REG_SEQ0(0x805a, 0x10),593 REG_SEQ0(0x805a, 0x00),594 };595 596 regmap_write(lt9611uxc->regmap, 0x8108, 0xbf);597 msleep(20);598 regmap_write(lt9611uxc->regmap, 0x8108, 0xff);599 msleep(20);600 regmap_multi_reg_write(lt9611uxc->regmap, seq_write_prepare, ARRAY_SIZE(seq_write_prepare));601 regmap_noinc_write(lt9611uxc->regmap, 0x8059, buf, LT9611UXC_FW_PAGE_SIZE);602 regmap_multi_reg_write(lt9611uxc->regmap, seq_write_addr, ARRAY_SIZE(seq_write_addr));603 msleep(20);604}605 606static void lt9611uxc_firmware_read_page(struct lt9611uxc *lt9611uxc, u16 addr, char *buf)607{608 struct reg_sequence seq_read_page[] = {609 REG_SEQ0(0x805a, 0xa0),610 REG_SEQ0(0x805a, 0x80),611 REG_SEQ0(0x805b, (addr >> 16) & 0xff),612 REG_SEQ0(0x805c, (addr >> 8) & 0xff),613 REG_SEQ0(0x805d, addr & 0xff),614 REG_SEQ0(0x805a, 0x90),615 REG_SEQ0(0x805a, 0x80),616 REG_SEQ0(0x8058, 0x21),617 };618 619 regmap_multi_reg_write(lt9611uxc->regmap, seq_read_page, ARRAY_SIZE(seq_read_page));620 regmap_noinc_read(lt9611uxc->regmap, 0x805f, buf, LT9611UXC_FW_PAGE_SIZE);621}622 623static char *lt9611uxc_firmware_read(struct lt9611uxc *lt9611uxc, size_t size)624{625 struct reg_sequence seq_read_setup[] = {626 REG_SEQ0(0x805a, 0x84),627 REG_SEQ0(0x805a, 0x80),628 };629 630 char *readbuf;631 u16 offset;632 633 readbuf = kzalloc(ALIGN(size, 32), GFP_KERNEL);634 if (!readbuf)635 return NULL;636 637 regmap_multi_reg_write(lt9611uxc->regmap, seq_read_setup, ARRAY_SIZE(seq_read_setup));638 639 for (offset = 0;640 offset < size;641 offset += LT9611UXC_FW_PAGE_SIZE)642 lt9611uxc_firmware_read_page(lt9611uxc, offset, &readbuf[offset]);643 644 return readbuf;645}646 647static int lt9611uxc_firmware_update(struct lt9611uxc *lt9611uxc)648{649 int ret;650 u16 offset;651 size_t remain;652 char *readbuf;653 const struct firmware *fw;654 655 struct reg_sequence seq_setup[] = {656 REG_SEQ0(0x805e, 0xdf),657 REG_SEQ0(0x8058, 0x00),658 REG_SEQ0(0x8059, 0x50),659 REG_SEQ0(0x805a, 0x10),660 REG_SEQ0(0x805a, 0x00),661 };662 663 664 struct reg_sequence seq_block_erase[] = {665 REG_SEQ0(0x805a, 0x04),666 REG_SEQ0(0x805a, 0x00),667 REG_SEQ0(0x805b, 0x00),668 REG_SEQ0(0x805c, 0x00),669 REG_SEQ0(0x805d, 0x00),670 REG_SEQ0(0x805a, 0x01),671 REG_SEQ0(0x805a, 0x00),672 };673 674 ret = request_firmware(&fw, FW_FILE, lt9611uxc->dev);675 if (ret < 0)676 return ret;677 678 dev_info(lt9611uxc->dev, "Updating firmware\n");679 lt9611uxc_lock(lt9611uxc);680 681 regmap_multi_reg_write(lt9611uxc->regmap, seq_setup, ARRAY_SIZE(seq_setup));682 683 /*684 * Need erase block 2 timess here. Sometimes, block erase can fail.685 * This is a workaroud.686 */687 regmap_multi_reg_write(lt9611uxc->regmap, seq_block_erase, ARRAY_SIZE(seq_block_erase));688 msleep(3000);689 regmap_multi_reg_write(lt9611uxc->regmap, seq_block_erase, ARRAY_SIZE(seq_block_erase));690 msleep(3000);691 692 for (offset = 0, remain = fw->size;693 remain >= LT9611UXC_FW_PAGE_SIZE;694 offset += LT9611UXC_FW_PAGE_SIZE, remain -= LT9611UXC_FW_PAGE_SIZE)695 lt9611uxc_firmware_write_page(lt9611uxc, offset, fw->data + offset);696 697 if (remain > 0) {698 char buf[LT9611UXC_FW_PAGE_SIZE];699 700 memset(buf, 0xff, LT9611UXC_FW_PAGE_SIZE);701 memcpy(buf, fw->data + offset, remain);702 lt9611uxc_firmware_write_page(lt9611uxc, offset, buf);703 }704 msleep(20);705 706 readbuf = lt9611uxc_firmware_read(lt9611uxc, fw->size);707 if (!readbuf) {708 ret = -ENOMEM;709 goto out;710 }711 712 if (!memcmp(readbuf, fw->data, fw->size)) {713 dev_err(lt9611uxc->dev, "Firmware update failed\n");714 print_hex_dump(KERN_ERR, "fw: ", DUMP_PREFIX_OFFSET, 16, 1, readbuf, fw->size, false);715 ret = -EINVAL;716 } else {717 dev_info(lt9611uxc->dev, "Firmware updates successfully\n");718 ret = 0;719 }720 kfree(readbuf);721 722out:723 lt9611uxc_unlock(lt9611uxc);724 lt9611uxc_reset(lt9611uxc);725 release_firmware(fw);726 727 return ret;728}729 730static ssize_t lt9611uxc_firmware_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len)731{732 struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev);733 int ret;734 735 ret = lt9611uxc_firmware_update(lt9611uxc);736 if (ret < 0)737 return ret;738 return len;739}740 741static ssize_t lt9611uxc_firmware_show(struct device *dev, struct device_attribute *attr, char *buf)742{743 struct lt9611uxc *lt9611uxc = dev_get_drvdata(dev);744 745 return sysfs_emit(buf, "%02x\n", lt9611uxc->fw_version);746}747 748static DEVICE_ATTR_RW(lt9611uxc_firmware);749 750static struct attribute *lt9611uxc_attrs[] = {751 &dev_attr_lt9611uxc_firmware.attr,752 NULL,753};754 755static const struct attribute_group lt9611uxc_attr_group = {756 .attrs = lt9611uxc_attrs,757};758 759static const struct attribute_group *lt9611uxc_attr_groups[] = {760 <9611uxc_attr_group,761 NULL,762};763 764static int lt9611uxc_probe(struct i2c_client *client)765{766 struct lt9611uxc *lt9611uxc;767 struct device *dev = &client->dev;768 int ret;769 bool fw_updated = false;770 771 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {772 dev_err(dev, "device doesn't support I2C\n");773 return -ENODEV;774 }775 776 lt9611uxc = devm_kzalloc(dev, sizeof(*lt9611uxc), GFP_KERNEL);777 if (!lt9611uxc)778 return -ENOMEM;779 780 lt9611uxc->dev = dev;781 lt9611uxc->client = client;782 mutex_init(<9611uxc->ocm_lock);783 784 lt9611uxc->regmap = devm_regmap_init_i2c(client, <9611uxc_regmap_config);785 if (IS_ERR(lt9611uxc->regmap)) {786 dev_err(lt9611uxc->dev, "regmap i2c init failed\n");787 return PTR_ERR(lt9611uxc->regmap);788 }789 790 ret = lt9611uxc_parse_dt(dev, lt9611uxc);791 if (ret) {792 dev_err(dev, "failed to parse device tree\n");793 return ret;794 }795 796 ret = lt9611uxc_gpio_init(lt9611uxc);797 if (ret < 0)798 goto err_of_put;799 800 ret = lt9611uxc_regulator_init(lt9611uxc);801 if (ret < 0)802 goto err_of_put;803 804 lt9611uxc_assert_5v(lt9611uxc);805 806 ret = lt9611uxc_regulator_enable(lt9611uxc);807 if (ret)808 goto err_of_put;809 810 lt9611uxc_reset(lt9611uxc);811 812 ret = lt9611uxc_read_device_rev(lt9611uxc);813 if (ret) {814 dev_err(dev, "failed to read chip rev\n");815 goto err_disable_regulators;816 }817 818retry:819 ret = lt9611uxc_read_version(lt9611uxc);820 if (ret < 0) {821 dev_err(dev, "failed to read FW version\n");822 goto err_disable_regulators;823 } else if (ret == 0) {824 if (!fw_updated) {825 fw_updated = true;826 dev_err(dev, "FW version 0, enforcing firmware update\n");827 ret = lt9611uxc_firmware_update(lt9611uxc);828 if (ret < 0)829 goto err_disable_regulators;830 else831 goto retry;832 } else {833 dev_err(dev, "FW version 0, update failed\n");834 ret = -EOPNOTSUPP;835 goto err_disable_regulators;836 }837 } else if (ret < 0x40) {838 dev_info(dev, "FW version 0x%x, HPD not supported\n", ret);839 } else {840 lt9611uxc->hpd_supported = true;841 }842 lt9611uxc->fw_version = ret;843 844 init_waitqueue_head(<9611uxc->wq);845 INIT_WORK(<9611uxc->work, lt9611uxc_hpd_work);846 847 ret = request_threaded_irq(client->irq, NULL,848 lt9611uxc_irq_thread_handler,849 IRQF_ONESHOT, "lt9611uxc", lt9611uxc);850 if (ret) {851 dev_err(dev, "failed to request irq\n");852 goto err_disable_regulators;853 }854 855 i2c_set_clientdata(client, lt9611uxc);856 857 lt9611uxc->bridge.funcs = <9611uxc_bridge_funcs;858 lt9611uxc->bridge.of_node = client->dev.of_node;859 lt9611uxc->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;860 if (lt9611uxc->hpd_supported)861 lt9611uxc->bridge.ops |= DRM_BRIDGE_OP_HPD;862 lt9611uxc->bridge.type = DRM_MODE_CONNECTOR_HDMIA;863 864 drm_bridge_add(<9611uxc->bridge);865 866 /* Attach primary DSI */867 lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node);868 if (IS_ERR(lt9611uxc->dsi0)) {869 ret = PTR_ERR(lt9611uxc->dsi0);870 goto err_remove_bridge;871 }872 873 /* Attach secondary DSI, if specified */874 if (lt9611uxc->dsi1_node) {875 lt9611uxc->dsi1 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi1_node);876 if (IS_ERR(lt9611uxc->dsi1)) {877 ret = PTR_ERR(lt9611uxc->dsi1);878 goto err_remove_bridge;879 }880 }881 882 return lt9611uxc_audio_init(dev, lt9611uxc);883 884err_remove_bridge:885 free_irq(client->irq, lt9611uxc);886 cancel_work_sync(<9611uxc->work);887 drm_bridge_remove(<9611uxc->bridge);888 889err_disable_regulators:890 regulator_bulk_disable(ARRAY_SIZE(lt9611uxc->supplies), lt9611uxc->supplies);891 892err_of_put:893 of_node_put(lt9611uxc->dsi1_node);894 of_node_put(lt9611uxc->dsi0_node);895 896 return ret;897}898 899static void lt9611uxc_remove(struct i2c_client *client)900{901 struct lt9611uxc *lt9611uxc = i2c_get_clientdata(client);902 903 free_irq(client->irq, lt9611uxc);904 cancel_work_sync(<9611uxc->work);905 lt9611uxc_audio_exit(lt9611uxc);906 drm_bridge_remove(<9611uxc->bridge);907 908 mutex_destroy(<9611uxc->ocm_lock);909 910 regulator_bulk_disable(ARRAY_SIZE(lt9611uxc->supplies), lt9611uxc->supplies);911 912 of_node_put(lt9611uxc->dsi1_node);913 of_node_put(lt9611uxc->dsi0_node);914}915 916static struct i2c_device_id lt9611uxc_id[] = {917 { "lontium,lt9611uxc", 0 },918 { /* sentinel */ }919};920 921static const struct of_device_id lt9611uxc_match_table[] = {922 { .compatible = "lontium,lt9611uxc" },923 { /* sentinel */ }924};925MODULE_DEVICE_TABLE(of, lt9611uxc_match_table);926 927static struct i2c_driver lt9611uxc_driver = {928 .driver = {929 .name = "lt9611uxc",930 .of_match_table = lt9611uxc_match_table,931 .dev_groups = lt9611uxc_attr_groups,932 },933 .probe = lt9611uxc_probe,934 .remove = lt9611uxc_remove,935 .id_table = lt9611uxc_id,936};937module_i2c_driver(lt9611uxc_driver);938 939MODULE_AUTHOR("Dmitry Baryshkov <dmitry.baryshkov@linaro.org>");940MODULE_DESCRIPTION("Lontium LT9611UXC DSI/HDMI bridge driver");941MODULE_LICENSE("GPL v2");942 943MODULE_FIRMWARE(FW_FILE);944