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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * DesignWare HDMI audio driver4 *5 * Written and tested against the Designware HDMI Tx found in iMX6.6 */7#include <linux/io.h>8#include <linux/interrupt.h>9#include <linux/module.h>10#include <linux/platform_device.h>11#include <linux/vmalloc.h>12#include <drm/bridge/dw_hdmi.h>13#include <drm/drm_edid.h>14 15#include <sound/asoundef.h>16#include <sound/core.h>17#include <sound/initval.h>18#include <sound/pcm.h>19#include <sound/pcm_drm_eld.h>20#include <sound/pcm_iec958.h>21 22#include "dw-hdmi-audio.h"23 24#define DRIVER_NAME "dw-hdmi-ahb-audio"25 26/* Provide some bits rather than bit offsets */27enum {28 HDMI_AHB_DMA_CONF0_SW_FIFO_RST = BIT(7),29 HDMI_AHB_DMA_CONF0_EN_HLOCK = BIT(3),30 HDMI_AHB_DMA_START_START = BIT(0),31 HDMI_AHB_DMA_STOP_STOP = BIT(0),32 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = BIT(5),33 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = BIT(4),34 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = BIT(3),35 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = BIT(2),36 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),37 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),38 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL =39 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR |40 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST |41 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY |42 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE |43 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL |44 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY,45 HDMI_IH_AHBDMAAUD_STAT0_ERROR = BIT(5),46 HDMI_IH_AHBDMAAUD_STAT0_LOST = BIT(4),47 HDMI_IH_AHBDMAAUD_STAT0_RETRY = BIT(3),48 HDMI_IH_AHBDMAAUD_STAT0_DONE = BIT(2),49 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),50 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),51 HDMI_IH_AHBDMAAUD_STAT0_ALL =52 HDMI_IH_AHBDMAAUD_STAT0_ERROR |53 HDMI_IH_AHBDMAAUD_STAT0_LOST |54 HDMI_IH_AHBDMAAUD_STAT0_RETRY |55 HDMI_IH_AHBDMAAUD_STAT0_DONE |56 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL |57 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY,58 HDMI_AHB_DMA_CONF0_INCR16 = 2 << 1,59 HDMI_AHB_DMA_CONF0_INCR8 = 1 << 1,60 HDMI_AHB_DMA_CONF0_INCR4 = 0,61 HDMI_AHB_DMA_CONF0_BURST_MODE = BIT(0),62 HDMI_AHB_DMA_MASK_DONE = BIT(7),63 64 HDMI_REVISION_ID = 0x0001,65 HDMI_IH_AHBDMAAUD_STAT0 = 0x0109,66 HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189,67 HDMI_AHB_DMA_CONF0 = 0x3600,68 HDMI_AHB_DMA_START = 0x3601,69 HDMI_AHB_DMA_STOP = 0x3602,70 HDMI_AHB_DMA_THRSLD = 0x3603,71 HDMI_AHB_DMA_STRADDR0 = 0x3604,72 HDMI_AHB_DMA_STPADDR0 = 0x3608,73 HDMI_AHB_DMA_MASK = 0x3614,74 HDMI_AHB_DMA_POL = 0x3615,75 HDMI_AHB_DMA_CONF1 = 0x3616,76 HDMI_AHB_DMA_BUFFPOL = 0x361a,77};78 79struct dw_hdmi_channel_conf {80 u8 conf1;81 u8 ca;82};83 84/*85 * The default mapping of ALSA channels to HDMI channels and speaker86 * allocation bits. Note that we can't do channel remapping here -87 * channels must be in the same order.88 *89 * Mappings for alsa-lib pcm/surround*.conf files:90 *91 * Front Sur4.0 Sur4.1 Sur5.0 Sur5.1 Sur7.192 * Channels 2 4 6 6 6 893 *94 * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:95 *96 * Number of ALSA channels97 * ALSA Channel 2 3 4 5 6 7 898 * 0 FL:0 = = = = = =99 * 1 FR:1 = = = = = =100 * 2 FC:3 RL:4 LFE:2 = = =101 * 3 RR:5 RL:4 FC:3 = =102 * 4 RR:5 RL:4 = =103 * 5 RR:5 = =104 * 6 RC:6 =105 * 7 RLC/FRC RLC/FRC106 */107static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {108 { 0x03, 0x00 }, /* FL,FR */109 { 0x0b, 0x02 }, /* FL,FR,FC */110 { 0x33, 0x08 }, /* FL,FR,RL,RR */111 { 0x37, 0x09 }, /* FL,FR,LFE,RL,RR */112 { 0x3f, 0x0b }, /* FL,FR,LFE,FC,RL,RR */113 { 0x7f, 0x0f }, /* FL,FR,LFE,FC,RL,RR,RC */114 { 0xff, 0x13 }, /* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */115};116 117struct snd_dw_hdmi {118 struct snd_card *card;119 struct snd_pcm *pcm;120 spinlock_t lock;121 struct dw_hdmi_audio_data data;122 struct snd_pcm_substream *substream;123 void (*reformat)(struct snd_dw_hdmi *, size_t, size_t);124 void *buf_src;125 void *buf_dst;126 dma_addr_t buf_addr;127 unsigned buf_offset;128 unsigned buf_period;129 unsigned buf_size;130 unsigned channels;131 u8 revision;132 u8 iec_offset;133 u8 cs[192][8];134};135 136static void dw_hdmi_writel(u32 val, void __iomem *ptr)137{138 writeb_relaxed(val, ptr);139 writeb_relaxed(val >> 8, ptr + 1);140 writeb_relaxed(val >> 16, ptr + 2);141 writeb_relaxed(val >> 24, ptr + 3);142}143 144/*145 * Convert to hardware format: The userspace buffer contains IEC958 samples,146 * with the PCUV bits in bits 31..28 and audio samples in bits 27..4. We147 * need these to be in bits 27..24, with the IEC B bit in bit 28, and audio148 * samples in 23..0.149 *150 * Default preamble in bits 3..0: 8 = block start, 4 = even 2 = odd151 *152 * Ideally, we could do with having the data properly formatted in userspace.153 */154static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw,155 size_t offset, size_t bytes)156{157 u32 *src = dw->buf_src + offset;158 u32 *dst = dw->buf_dst + offset;159 u32 *end = dw->buf_src + offset + bytes;160 161 do {162 u32 b, sample = *src++;163 164 b = (sample & 8) << (28 - 3);165 166 sample >>= 4;167 168 *dst++ = sample | b;169 } while (src < end);170}171 172static u32 parity(u32 sample)173{174 sample ^= sample >> 16;175 sample ^= sample >> 8;176 sample ^= sample >> 4;177 sample ^= sample >> 2;178 sample ^= sample >> 1;179 return (sample & 1) << 27;180}181 182static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw,183 size_t offset, size_t bytes)184{185 u32 *src = dw->buf_src + offset;186 u32 *dst = dw->buf_dst + offset;187 u32 *end = dw->buf_src + offset + bytes;188 189 do {190 unsigned i;191 u8 *cs;192 193 cs = dw->cs[dw->iec_offset++];194 if (dw->iec_offset >= 192)195 dw->iec_offset = 0;196 197 i = dw->channels;198 do {199 u32 sample = *src++;200 201 sample &= ~0xff000000;202 sample |= *cs++ << 24;203 sample |= parity(sample & ~0xf8000000);204 205 *dst++ = sample;206 } while (--i);207 } while (src < end);208}209 210static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw,211 struct snd_pcm_runtime *runtime)212{213 u8 cs[4];214 unsigned ch, i, j;215 216 snd_pcm_create_iec958_consumer(runtime, cs, sizeof(cs));217 218 memset(dw->cs, 0, sizeof(dw->cs));219 220 for (ch = 0; ch < 8; ch++) {221 cs[2] &= ~IEC958_AES2_CON_CHANNEL;222 cs[2] |= (ch + 1) << 4;223 224 for (i = 0; i < ARRAY_SIZE(cs); i++) {225 unsigned c = cs[i];226 227 for (j = 0; j < 8; j++, c >>= 1)228 dw->cs[i * 8 + j][ch] = (c & 1) << 2;229 }230 }231 dw->cs[0][0] |= BIT(4);232}233 234static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw)235{236 void __iomem *base = dw->data.base;237 unsigned offset = dw->buf_offset;238 unsigned period = dw->buf_period;239 u32 start, stop;240 241 dw->reformat(dw, offset, period);242 243 /* Clear all irqs before enabling irqs and starting DMA */244 writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL,245 base + HDMI_IH_AHBDMAAUD_STAT0);246 247 start = dw->buf_addr + offset;248 stop = start + period - 1;249 250 /* Setup the hardware start/stop addresses */251 dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0);252 dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0);253 254 writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK);255 writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START);256 257 offset += period;258 if (offset >= dw->buf_size)259 offset = 0;260 dw->buf_offset = offset;261}262 263static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw)264{265 /* Disable interrupts before disabling DMA */266 writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK);267 writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP);268}269 270static irqreturn_t snd_dw_hdmi_irq(int irq, void *data)271{272 struct snd_dw_hdmi *dw = data;273 struct snd_pcm_substream *substream;274 unsigned stat;275 276 stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);277 if (!stat)278 return IRQ_NONE;279 280 writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);281 282 substream = dw->substream;283 if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) {284 snd_pcm_period_elapsed(substream);285 286 spin_lock(&dw->lock);287 if (dw->substream)288 dw_hdmi_start_dma(dw);289 spin_unlock(&dw->lock);290 }291 292 return IRQ_HANDLED;293}294 295static const struct snd_pcm_hardware dw_hdmi_hw = {296 .info = SNDRV_PCM_INFO_INTERLEAVED |297 SNDRV_PCM_INFO_BLOCK_TRANSFER |298 SNDRV_PCM_INFO_MMAP |299 SNDRV_PCM_INFO_MMAP_VALID,300 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE |301 SNDRV_PCM_FMTBIT_S24_LE,302 .rates = SNDRV_PCM_RATE_32000 |303 SNDRV_PCM_RATE_44100 |304 SNDRV_PCM_RATE_48000 |305 SNDRV_PCM_RATE_88200 |306 SNDRV_PCM_RATE_96000 |307 SNDRV_PCM_RATE_176400 |308 SNDRV_PCM_RATE_192000,309 .channels_min = 2,310 .channels_max = 8,311 .buffer_bytes_max = 1024 * 1024,312 .period_bytes_min = 256,313 .period_bytes_max = 8192, /* ERR004323: must limit to 8k */314 .periods_min = 2,315 .periods_max = 16,316 .fifo_size = 0,317};318 319static int dw_hdmi_open(struct snd_pcm_substream *substream)320{321 struct snd_pcm_runtime *runtime = substream->runtime;322 struct snd_dw_hdmi *dw = substream->private_data;323 void __iomem *base = dw->data.base;324 u8 *eld;325 int ret;326 327 runtime->hw = dw_hdmi_hw;328 329 eld = dw->data.get_eld(dw->data.hdmi);330 if (eld) {331 ret = snd_pcm_hw_constraint_eld(runtime, eld);332 if (ret < 0)333 return ret;334 }335 336 ret = snd_pcm_limit_hw_rates(runtime);337 if (ret < 0)338 return ret;339 340 ret = snd_pcm_hw_constraint_integer(runtime,341 SNDRV_PCM_HW_PARAM_PERIODS);342 if (ret < 0)343 return ret;344 345 /* Limit the buffer size to the size of the preallocated buffer */346 ret = snd_pcm_hw_constraint_minmax(runtime,347 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,348 0, substream->dma_buffer.bytes);349 if (ret < 0)350 return ret;351 352 /* Clear FIFO */353 writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,354 base + HDMI_AHB_DMA_CONF0);355 356 /* Configure interrupt polarities */357 writeb_relaxed(~0, base + HDMI_AHB_DMA_POL);358 writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL);359 360 /* Keep interrupts masked, and clear any pending */361 writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK);362 writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0);363 364 ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED,365 "dw-hdmi-audio", dw);366 if (ret)367 return ret;368 369 /* Un-mute done interrupt */370 writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &371 ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE,372 base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);373 374 return 0;375}376 377static int dw_hdmi_close(struct snd_pcm_substream *substream)378{379 struct snd_dw_hdmi *dw = substream->private_data;380 381 /* Mute all interrupts */382 writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,383 dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);384 385 free_irq(dw->data.irq, dw);386 387 return 0;388}389 390static int dw_hdmi_hw_free(struct snd_pcm_substream *substream)391{392 struct snd_pcm_runtime *runtime = substream->runtime;393 394 vfree(runtime->dma_area);395 runtime->dma_area = NULL;396 return 0;397}398 399static int dw_hdmi_hw_params(struct snd_pcm_substream *substream,400 struct snd_pcm_hw_params *params)401{402 struct snd_pcm_runtime *runtime = substream->runtime;403 size_t size = params_buffer_bytes(params);404 405 /* Allocate the PCM runtime buffer, which is exposed to userspace. */406 if (runtime->dma_area) {407 if (runtime->dma_bytes >= size)408 return 0; /* already large enough */409 vfree(runtime->dma_area);410 }411 runtime->dma_area = vzalloc(size);412 if (!runtime->dma_area)413 return -ENOMEM;414 runtime->dma_bytes = size;415 return 1;416}417 418static struct page *dw_hdmi_get_page(struct snd_pcm_substream *substream,419 unsigned long offset)420{421 return vmalloc_to_page(substream->runtime->dma_area + offset);422}423 424static int dw_hdmi_prepare(struct snd_pcm_substream *substream)425{426 struct snd_pcm_runtime *runtime = substream->runtime;427 struct snd_dw_hdmi *dw = substream->private_data;428 u8 threshold, conf0, conf1, ca;429 430 /* Setup as per 3.0.5 FSL 4.1.0 BSP */431 switch (dw->revision) {432 case 0x0a:433 conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |434 HDMI_AHB_DMA_CONF0_INCR4;435 if (runtime->channels == 2)436 threshold = 126;437 else438 threshold = 124;439 break;440 case 0x1a:441 conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |442 HDMI_AHB_DMA_CONF0_INCR8;443 threshold = 128;444 break;445 default:446 /* NOTREACHED */447 return -EINVAL;448 }449 450 dw_hdmi_set_sample_rate(dw->data.hdmi, runtime->rate);451 452 /* Minimum number of bytes in the fifo. */453 runtime->hw.fifo_size = threshold * 32;454 455 conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK;456 conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1;457 ca = default_hdmi_channel_config[runtime->channels - 2].ca;458 459 writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);460 writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);461 writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);462 463 dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels);464 dw_hdmi_set_channel_allocation(dw->data.hdmi, ca);465 466 switch (runtime->format) {467 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:468 dw->reformat = dw_hdmi_reformat_iec958;469 break;470 case SNDRV_PCM_FORMAT_S24_LE:471 dw_hdmi_create_cs(dw, runtime);472 dw->reformat = dw_hdmi_reformat_s24;473 break;474 }475 dw->iec_offset = 0;476 dw->channels = runtime->channels;477 dw->buf_src = runtime->dma_area;478 dw->buf_dst = substream->dma_buffer.area;479 dw->buf_addr = substream->dma_buffer.addr;480 dw->buf_period = snd_pcm_lib_period_bytes(substream);481 dw->buf_size = snd_pcm_lib_buffer_bytes(substream);482 483 return 0;484}485 486static int dw_hdmi_trigger(struct snd_pcm_substream *substream, int cmd)487{488 struct snd_dw_hdmi *dw = substream->private_data;489 unsigned long flags;490 int ret = 0;491 492 switch (cmd) {493 case SNDRV_PCM_TRIGGER_START:494 spin_lock_irqsave(&dw->lock, flags);495 dw->buf_offset = 0;496 dw->substream = substream;497 dw_hdmi_start_dma(dw);498 dw_hdmi_audio_enable(dw->data.hdmi);499 spin_unlock_irqrestore(&dw->lock, flags);500 substream->runtime->delay = substream->runtime->period_size;501 break;502 503 case SNDRV_PCM_TRIGGER_STOP:504 spin_lock_irqsave(&dw->lock, flags);505 dw->substream = NULL;506 dw_hdmi_stop_dma(dw);507 dw_hdmi_audio_disable(dw->data.hdmi);508 spin_unlock_irqrestore(&dw->lock, flags);509 break;510 511 default:512 ret = -EINVAL;513 break;514 }515 516 return ret;517}518 519static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream)520{521 struct snd_pcm_runtime *runtime = substream->runtime;522 struct snd_dw_hdmi *dw = substream->private_data;523 524 /*525 * We are unable to report the exact hardware position as526 * reading the 32-bit DMA position using 8-bit reads is racy.527 */528 return bytes_to_frames(runtime, dw->buf_offset);529}530 531static const struct snd_pcm_ops snd_dw_hdmi_ops = {532 .open = dw_hdmi_open,533 .close = dw_hdmi_close,534 .ioctl = snd_pcm_lib_ioctl,535 .hw_params = dw_hdmi_hw_params,536 .hw_free = dw_hdmi_hw_free,537 .prepare = dw_hdmi_prepare,538 .trigger = dw_hdmi_trigger,539 .pointer = dw_hdmi_pointer,540 .page = dw_hdmi_get_page,541};542 543static int snd_dw_hdmi_probe(struct platform_device *pdev)544{545 const struct dw_hdmi_audio_data *data = pdev->dev.platform_data;546 struct device *dev = pdev->dev.parent;547 struct snd_dw_hdmi *dw;548 struct snd_card *card;549 struct snd_pcm *pcm;550 unsigned revision;551 int ret;552 553 writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,554 data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);555 revision = readb_relaxed(data->base + HDMI_REVISION_ID);556 if (revision != 0x0a && revision != 0x1a) {557 dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n",558 revision);559 return -ENXIO;560 }561 562 ret = snd_card_new(dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,563 THIS_MODULE, sizeof(struct snd_dw_hdmi), &card);564 if (ret < 0)565 return ret;566 567 strscpy(card->driver, DRIVER_NAME, sizeof(card->driver));568 strscpy(card->shortname, "DW-HDMI", sizeof(card->shortname));569 snprintf(card->longname, sizeof(card->longname),570 "%s rev 0x%02x, irq %d", card->shortname, revision,571 data->irq);572 573 dw = card->private_data;574 dw->card = card;575 dw->data = *data;576 dw->revision = revision;577 578 spin_lock_init(&dw->lock);579 580 ret = snd_pcm_new(card, "DW HDMI", 0, 1, 0, &pcm);581 if (ret < 0)582 goto err;583 584 dw->pcm = pcm;585 pcm->private_data = dw;586 strscpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));587 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dw_hdmi_ops);588 589 /*590 * To support 8-channel 96kHz audio reliably, we need 512k591 * to satisfy alsa with our restricted period (ERR004323).592 */593 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,594 dev, 128 * 1024, 1024 * 1024);595 596 ret = snd_card_register(card);597 if (ret < 0)598 goto err;599 600 platform_set_drvdata(pdev, dw);601 602 return 0;603 604err:605 snd_card_free(card);606 return ret;607}608 609static void snd_dw_hdmi_remove(struct platform_device *pdev)610{611 struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);612 613 snd_card_free(dw->card);614}615 616#if defined(CONFIG_PM_SLEEP) && defined(IS_NOT_BROKEN)617/*618 * This code is fine, but requires implementation in the dw_hdmi_trigger()619 * method which is currently missing as I have no way to test this.620 */621static int snd_dw_hdmi_suspend(struct device *dev)622{623 struct snd_dw_hdmi *dw = dev_get_drvdata(dev);624 625 snd_power_change_state(dw->card, SNDRV_CTL_POWER_D3cold);626 627 return 0;628}629 630static int snd_dw_hdmi_resume(struct device *dev)631{632 struct snd_dw_hdmi *dw = dev_get_drvdata(dev);633 634 snd_power_change_state(dw->card, SNDRV_CTL_POWER_D0);635 636 return 0;637}638 639static SIMPLE_DEV_PM_OPS(snd_dw_hdmi_pm, snd_dw_hdmi_suspend,640 snd_dw_hdmi_resume);641#define PM_OPS &snd_dw_hdmi_pm642#else643#define PM_OPS NULL644#endif645 646static struct platform_driver snd_dw_hdmi_driver = {647 .probe = snd_dw_hdmi_probe,648 .remove_new = snd_dw_hdmi_remove,649 .driver = {650 .name = DRIVER_NAME,651 .pm = PM_OPS,652 },653};654 655module_platform_driver(snd_dw_hdmi_driver);656 657MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");658MODULE_DESCRIPTION("Synopsis Designware HDMI AHB ALSA interface");659MODULE_LICENSE("GPL v2");660MODULE_ALIAS("platform:" DRIVER_NAME);661