brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * DesignWare High-Definition Multimedia Interface (HDMI) driver4 *5 * Copyright (C) 2013-2015 Mentor Graphics Inc.6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>8 */9#include <linux/clk.h>10#include <linux/delay.h>11#include <linux/err.h>12#include <linux/hdmi.h>13#include <linux/i2c.h>14#include <linux/irq.h>15#include <linux/module.h>16#include <linux/mutex.h>17#include <linux/of.h>18#include <linux/pinctrl/consumer.h>19#include <linux/regmap.h>20#include <linux/dma-mapping.h>21#include <linux/spinlock.h>22 23#include <media/cec-notifier.h>24 25#include <uapi/linux/media-bus-format.h>26#include <uapi/linux/videodev2.h>27 28#include <drm/bridge/dw_hdmi.h>29#include <drm/display/drm_hdmi_helper.h>30#include <drm/display/drm_scdc_helper.h>31#include <drm/drm_atomic.h>32#include <drm/drm_atomic_helper.h>33#include <drm/drm_bridge.h>34#include <drm/drm_edid.h>35#include <drm/drm_of.h>36#include <drm/drm_print.h>37#include <drm/drm_probe_helper.h>38 39#include "dw-hdmi-audio.h"40#include "dw-hdmi-cec.h"41#include "dw-hdmi.h"42 43#define DDC_CI_ADDR		0x3744#define DDC_SEGMENT_ADDR	0x3045 46#define HDMI_EDID_LEN		51247 48/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */49#define SCDC_MIN_SOURCE_VERSION	0x150 51#define HDMI14_MAX_TMDSCLK	34000000052 53static const u16 csc_coeff_default[3][4] = {54	{ 0x2000, 0x0000, 0x0000, 0x0000 },55	{ 0x0000, 0x2000, 0x0000, 0x0000 },56	{ 0x0000, 0x0000, 0x2000, 0x0000 }57};58 59static const u16 csc_coeff_rgb_out_eitu601[3][4] = {60	{ 0x2000, 0x6926, 0x74fd, 0x010e },61	{ 0x2000, 0x2cdd, 0x0000, 0x7e9a },62	{ 0x2000, 0x0000, 0x38b4, 0x7e3b }63};64 65static const u16 csc_coeff_rgb_out_eitu709[3][4] = {66	{ 0x2000, 0x7106, 0x7a02, 0x00a7 },67	{ 0x2000, 0x3264, 0x0000, 0x7e6d },68	{ 0x2000, 0x0000, 0x3b61, 0x7e25 }69};70 71static const u16 csc_coeff_rgb_in_eitu601[3][4] = {72	{ 0x2591, 0x1322, 0x074b, 0x0000 },73	{ 0x6535, 0x2000, 0x7acc, 0x0200 },74	{ 0x6acd, 0x7534, 0x2000, 0x0200 }75};76 77static const u16 csc_coeff_rgb_in_eitu709[3][4] = {78	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },79	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },80	{ 0x6756, 0x78ab, 0x2000, 0x0200 }81};82 83static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {84	{ 0x1b7c, 0x0000, 0x0000, 0x0020 },85	{ 0x0000, 0x1b7c, 0x0000, 0x0020 },86	{ 0x0000, 0x0000, 0x1b7c, 0x0020 }87};88 89struct hdmi_vmode {90	bool mdataenablepolarity;91 92	unsigned int mpixelclock;93	unsigned int mpixelrepetitioninput;94	unsigned int mpixelrepetitionoutput;95	unsigned int mtmdsclock;96};97 98struct hdmi_data_info {99	unsigned int enc_in_bus_format;100	unsigned int enc_out_bus_format;101	unsigned int enc_in_encoding;102	unsigned int enc_out_encoding;103	unsigned int pix_repet_factor;104	unsigned int hdcp_enable;105	struct hdmi_vmode video_mode;106	bool rgb_limited_range;107};108 109struct dw_hdmi_i2c {110	struct i2c_adapter	adap;111 112	struct mutex		lock;	/* used to serialize data transfers */113	struct completion	cmp;114	u8			stat;115 116	u8			slave_reg;117	bool			is_regaddr;118	bool			is_segment;119};120 121struct dw_hdmi_phy_data {122	enum dw_hdmi_phy_type type;123	const char *name;124	unsigned int gen;125	bool has_svsret;126	int (*configure)(struct dw_hdmi *hdmi,127			 const struct dw_hdmi_plat_data *pdata,128			 unsigned long mpixelclock);129};130 131struct dw_hdmi {132	struct drm_connector connector;133	struct drm_bridge bridge;134	struct drm_bridge *next_bridge;135 136	unsigned int version;137 138	struct platform_device *audio;139	struct platform_device *cec;140	struct device *dev;141	struct dw_hdmi_i2c *i2c;142 143	struct hdmi_data_info hdmi_data;144	const struct dw_hdmi_plat_data *plat_data;145 146	int vic;147 148	u8 edid[HDMI_EDID_LEN];149 150	struct {151		const struct dw_hdmi_phy_ops *ops;152		const char *name;153		void *data;154		bool enabled;155	} phy;156 157	struct drm_display_mode previous_mode;158 159	struct i2c_adapter *ddc;160	void __iomem *regs;161	bool sink_is_hdmi;162	bool sink_has_audio;163 164	struct pinctrl *pinctrl;165	struct pinctrl_state *default_state;166	struct pinctrl_state *unwedge_state;167 168	struct mutex mutex;		/* for state below and previous_mode */169	enum drm_connector_force force;	/* mutex-protected force state */170	struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */171	bool disabled;			/* DRM has disabled our bridge */172	bool bridge_is_on;		/* indicates the bridge is on */173	bool rxsense;			/* rxsense state */174	u8 phy_mask;			/* desired phy int mask settings */175	u8 mc_clkdis;			/* clock disable register */176 177	spinlock_t audio_lock;178	struct mutex audio_mutex;179	unsigned int sample_non_pcm;180	unsigned int sample_width;181	unsigned int sample_rate;182	unsigned int channels;183	unsigned int audio_cts;184	unsigned int audio_n;185	bool audio_enable;186 187	unsigned int reg_shift;188	struct regmap *regm;189	void (*enable_audio)(struct dw_hdmi *hdmi);190	void (*disable_audio)(struct dw_hdmi *hdmi);191 192	struct mutex cec_notifier_mutex;193	struct cec_notifier *cec_notifier;194 195	hdmi_codec_plugged_cb plugged_cb;196	struct device *codec_dev;197	enum drm_connector_status last_connector_result;198};199 200#define HDMI_IH_PHY_STAT0_RX_SENSE \201	(HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \202	 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)203 204#define HDMI_PHY_RX_SENSE \205	(HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \206	 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)207 208static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)209{210	regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);211}212 213static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)214{215	unsigned int val = 0;216 217	regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);218 219	return val;220}221 222static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)223{224	if (hdmi->plugged_cb && hdmi->codec_dev)225		hdmi->plugged_cb(hdmi->codec_dev, plugged);226}227 228int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,229			   struct device *codec_dev)230{231	bool plugged;232 233	mutex_lock(&hdmi->mutex);234	hdmi->plugged_cb = fn;235	hdmi->codec_dev = codec_dev;236	plugged = hdmi->last_connector_result == connector_status_connected;237	handle_plugged_change(hdmi, plugged);238	mutex_unlock(&hdmi->mutex);239 240	return 0;241}242EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);243 244static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)245{246	regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);247}248 249static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,250			     u8 shift, u8 mask)251{252	hdmi_modb(hdmi, data << shift, mask, reg);253}254 255static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)256{257	hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,258		    HDMI_PHY_I2CM_INT_ADDR);259 260	hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |261		    HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,262		    HDMI_PHY_I2CM_CTLINT_ADDR);263 264	/* Software reset */265	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);266 267	/* Set Standard Mode speed (determined to be 100KHz on iMX6) */268	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);269 270	/* Set done, not acknowledged and arbitration interrupt polarities */271	hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);272	hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,273		    HDMI_I2CM_CTLINT);274 275	/* Clear DONE and ERROR interrupts */276	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,277		    HDMI_IH_I2CM_STAT0);278 279	/* Mute DONE and ERROR interrupts */280	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,281		    HDMI_IH_MUTE_I2CM_STAT0);282}283 284static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)285{286	/* If no unwedge state then give up */287	if (!hdmi->unwedge_state)288		return false;289 290	dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");291 292	/*293	 * This is a huge hack to workaround a problem where the dw_hdmi i2c294	 * bus could sometimes get wedged.  Once wedged there doesn't appear295	 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)296	 * other than pulsing the SDA line.297	 *298	 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)299	 * by:300	 * 1. Remux the pin as a GPIO output, driven low.301	 * 2. Wait a little while.  1 ms seems to work, but we'll do 10.302	 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.303	 *304	 * At the moment of remuxing, the line will still be low due to its305	 * recent stint as an output, but then it will be pulled high by the306	 * (presumed) external pullup.  dw_hdmi seems to see this as a rising307	 * edge and that seems to get it out of its jam.308	 *309	 * This wedging was only ever seen on one TV, and only on one of310	 * its HDMI ports.  It happened when the TV was powered on while the311	 * device was plugged in.  A scope trace shows the TV bringing both SDA312	 * and SCL low, then bringing them both back up at roughly the same313	 * time.  Presumably this confuses dw_hdmi because it saw activity but314	 * no real STOP (maybe it thinks there's another master on the bus?).315	 * Giving it a clean rising edge of SDA while SCL is already high316	 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out317	 * of its stupor.318	 *319	 * Note that after coming back alive, transfers seem to immediately320	 * resume, so if we unwedge due to a timeout we should wait a little321	 * longer for our transfer to finish, since it might have just started322	 * now.323	 */324	pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);325	msleep(10);326	pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);327 328	return true;329}330 331static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)332{333	struct dw_hdmi_i2c *i2c = hdmi->i2c;334	int stat;335 336	stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);337	if (!stat) {338		/* If we can't unwedge, return timeout */339		if (!dw_hdmi_i2c_unwedge(hdmi))340			return -EAGAIN;341 342		/* We tried to unwedge; give it another chance */343		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);344		if (!stat)345			return -EAGAIN;346	}347 348	/* Check for error condition on the bus */349	if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)350		return -EIO;351 352	return 0;353}354 355static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,356			    unsigned char *buf, unsigned int length)357{358	struct dw_hdmi_i2c *i2c = hdmi->i2c;359	int ret;360 361	if (!i2c->is_regaddr) {362		dev_dbg(hdmi->dev, "set read register address to 0\n");363		i2c->slave_reg = 0x00;364		i2c->is_regaddr = true;365	}366 367	while (length--) {368		reinit_completion(&i2c->cmp);369 370		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);371		if (i2c->is_segment)372			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,373				    HDMI_I2CM_OPERATION);374		else375			hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,376				    HDMI_I2CM_OPERATION);377 378		ret = dw_hdmi_i2c_wait(hdmi);379		if (ret)380			return ret;381 382		*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);383	}384	i2c->is_segment = false;385 386	return 0;387}388 389static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,390			     unsigned char *buf, unsigned int length)391{392	struct dw_hdmi_i2c *i2c = hdmi->i2c;393	int ret;394 395	if (!i2c->is_regaddr) {396		/* Use the first write byte as register address */397		i2c->slave_reg = buf[0];398		length--;399		buf++;400		i2c->is_regaddr = true;401	}402 403	while (length--) {404		reinit_completion(&i2c->cmp);405 406		hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);407		hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);408		hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,409			    HDMI_I2CM_OPERATION);410 411		ret = dw_hdmi_i2c_wait(hdmi);412		if (ret)413			return ret;414	}415 416	return 0;417}418 419static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,420			    struct i2c_msg *msgs, int num)421{422	struct dw_hdmi *hdmi = i2c_get_adapdata(adap);423	struct dw_hdmi_i2c *i2c = hdmi->i2c;424	u8 addr = msgs[0].addr;425	int i, ret = 0;426 427	if (addr == DDC_CI_ADDR)428		/*429		 * The internal I2C controller does not support the multi-byte430		 * read and write operations needed for DDC/CI.431		 * TOFIX: Blacklist the DDC/CI address until we filter out432		 * unsupported I2C operations.433		 */434		return -EOPNOTSUPP;435 436	dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);437 438	for (i = 0; i < num; i++) {439		if (msgs[i].len == 0) {440			dev_dbg(hdmi->dev,441				"unsupported transfer %d/%d, no data\n",442				i + 1, num);443			return -EOPNOTSUPP;444		}445	}446 447	mutex_lock(&i2c->lock);448 449	/* Unmute DONE and ERROR interrupts */450	hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);451 452	/* Set slave device address taken from the first I2C message */453	hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);454 455	/* Set slave device register address on transfer */456	i2c->is_regaddr = false;457 458	/* Set segment pointer for I2C extended read mode operation */459	i2c->is_segment = false;460 461	for (i = 0; i < num; i++) {462		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",463			i + 1, num, msgs[i].len, msgs[i].flags);464		if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {465			i2c->is_segment = true;466			hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);467			hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);468		} else {469			if (msgs[i].flags & I2C_M_RD)470				ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,471						       msgs[i].len);472			else473				ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,474							msgs[i].len);475		}476		if (ret < 0)477			break;478	}479 480	if (!ret)481		ret = num;482 483	/* Mute DONE and ERROR interrupts */484	hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,485		    HDMI_IH_MUTE_I2CM_STAT0);486 487	mutex_unlock(&i2c->lock);488 489	return ret;490}491 492static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)493{494	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;495}496 497static const struct i2c_algorithm dw_hdmi_algorithm = {498	.master_xfer	= dw_hdmi_i2c_xfer,499	.functionality	= dw_hdmi_i2c_func,500};501 502static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)503{504	struct i2c_adapter *adap;505	struct dw_hdmi_i2c *i2c;506	int ret;507 508	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);509	if (!i2c)510		return ERR_PTR(-ENOMEM);511 512	mutex_init(&i2c->lock);513	init_completion(&i2c->cmp);514 515	adap = &i2c->adap;516	adap->owner = THIS_MODULE;517	adap->dev.parent = hdmi->dev;518	adap->algo = &dw_hdmi_algorithm;519	strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));520	i2c_set_adapdata(adap, hdmi);521 522	ret = i2c_add_adapter(adap);523	if (ret) {524		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);525		devm_kfree(hdmi->dev, i2c);526		return ERR_PTR(ret);527	}528 529	hdmi->i2c = i2c;530 531	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);532 533	return adap;534}535 536static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,537			   unsigned int n)538{539	/* Must be set/cleared first */540	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);541 542	/* nshift factor = 0 */543	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);544 545	/* Use automatic CTS generation mode when CTS is not set */546	if (cts)547		hdmi_writeb(hdmi, ((cts >> 16) &548				   HDMI_AUD_CTS3_AUDCTS19_16_MASK) |549				  HDMI_AUD_CTS3_CTS_MANUAL,550			    HDMI_AUD_CTS3);551	else552		hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);553	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);554	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);555 556	hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);557	hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);558	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);559}560 561static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)562{563	unsigned int n = (128 * freq) / 1000;564	unsigned int mult = 1;565 566	while (freq > 48000) {567		mult *= 2;568		freq /= 2;569	}570 571	switch (freq) {572	case 32000:573		if (pixel_clk == 25175000)574			n = 4576;575		else if (pixel_clk == 27027000)576			n = 4096;577		else if (pixel_clk == 74176000 || pixel_clk == 148352000)578			n = 11648;579		else if (pixel_clk == 297000000)580			n = 3072;581		else582			n = 4096;583		n *= mult;584		break;585 586	case 44100:587		if (pixel_clk == 25175000)588			n = 7007;589		else if (pixel_clk == 74176000)590			n = 17836;591		else if (pixel_clk == 148352000)592			n = 8918;593		else if (pixel_clk == 297000000)594			n = 4704;595		else596			n = 6272;597		n *= mult;598		break;599 600	case 48000:601		if (pixel_clk == 25175000)602			n = 6864;603		else if (pixel_clk == 27027000)604			n = 6144;605		else if (pixel_clk == 74176000)606			n = 11648;607		else if (pixel_clk == 148352000)608			n = 5824;609		else if (pixel_clk == 297000000)610			n = 5120;611		else612			n = 6144;613		n *= mult;614		break;615 616	default:617		break;618	}619 620	return n;621}622 623/*624 * When transmitting IEC60958 linear PCM audio, these registers allow to625 * configure the channel status information of all the channel status626 * bits in the IEC60958 frame. For the moment this configuration is only627 * used when the I2S audio interface, General Purpose Audio (GPA),628 * or AHB audio DMA (AHBAUDDMA) interface is active629 * (for S/PDIF interface this information comes from the stream).630 */631void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,632				u8 *channel_status)633{634	/*635	 * Set channel status register for frequency and word length.636	 * Use default values for other registers.637	 */638	hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);639	hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);640}641EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);642 643static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,644	unsigned long pixel_clk, unsigned int sample_rate)645{646	unsigned long ftdms = pixel_clk;647	unsigned int n, cts;648	u8 config3;649	u64 tmp;650 651	n = hdmi_compute_n(sample_rate, pixel_clk);652 653	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);654 655	/* Compute CTS when using internal AHB audio or General Parallel audio*/656	if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {657		/*658		 * Compute the CTS value from the N value.  Note that CTS and N659		 * can be up to 20 bits in total, so we need 64-bit math.  Also660		 * note that our TDMS clock is not fully accurate; it is661		 * accurate to kHz.  This can introduce an unnecessary remainder662		 * in the calculation below, so we don't try to warn about that.663		 */664		tmp = (u64)ftdms * n;665		do_div(tmp, 128 * sample_rate);666		cts = tmp;667 668		dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",669			__func__, sample_rate,670			ftdms / 1000000, (ftdms / 1000) % 1000,671			n, cts);672	} else {673		cts = 0;674	}675 676	spin_lock_irq(&hdmi->audio_lock);677	hdmi->audio_n = n;678	hdmi->audio_cts = cts;679	hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);680	spin_unlock_irq(&hdmi->audio_lock);681}682 683static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)684{685	mutex_lock(&hdmi->audio_mutex);686	hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);687	mutex_unlock(&hdmi->audio_mutex);688}689 690static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)691{692	mutex_lock(&hdmi->audio_mutex);693	hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,694				 hdmi->sample_rate);695	mutex_unlock(&hdmi->audio_mutex);696}697 698void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)699{700	mutex_lock(&hdmi->audio_mutex);701	hdmi->sample_width = width;702	mutex_unlock(&hdmi->audio_mutex);703}704EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width);705 706void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)707{708	mutex_lock(&hdmi->audio_mutex);709	hdmi->sample_non_pcm = non_pcm;710	mutex_unlock(&hdmi->audio_mutex);711}712EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm);713 714void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)715{716	mutex_lock(&hdmi->audio_mutex);717	hdmi->sample_rate = rate;718	hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,719				 hdmi->sample_rate);720	mutex_unlock(&hdmi->audio_mutex);721}722EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);723 724void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)725{726	u8 layout;727 728	mutex_lock(&hdmi->audio_mutex);729	hdmi->channels = cnt;730 731	/*732	 * For >2 channel PCM audio, we need to select layout 1733	 * and set an appropriate channel map.734	 */735	if (cnt > 2)736		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;737	else738		layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;739 740	hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,741		  HDMI_FC_AUDSCONF);742 743	/* Set the audio infoframes channel count */744	hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,745		  HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);746 747	mutex_unlock(&hdmi->audio_mutex);748}749EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);750 751void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)752{753	mutex_lock(&hdmi->audio_mutex);754 755	hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);756 757	mutex_unlock(&hdmi->audio_mutex);758}759EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);760 761static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)762{763	if (enable)764		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;765	else766		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;767	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);768}769 770static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)771{772	if (!hdmi->curr_conn)773		return NULL;774 775	return hdmi->curr_conn->eld;776}777 778static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)779{780	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;781	int sample_freq = 0x2, org_sample_freq = 0xD;782	int ch_mask = BIT(hdmi->channels) - 1;783 784	switch (hdmi->sample_rate) {785	case 32000:786		sample_freq = 0x03;787		org_sample_freq = 0x0C;788		break;789	case 44100:790		sample_freq = 0x00;791		org_sample_freq = 0x0F;792		break;793	case 48000:794		sample_freq = 0x02;795		org_sample_freq = 0x0D;796		break;797	case 88200:798		sample_freq = 0x08;799		org_sample_freq = 0x07;800		break;801	case 96000:802		sample_freq = 0x0A;803		org_sample_freq = 0x05;804		break;805	case 176400:806		sample_freq = 0x0C;807		org_sample_freq = 0x03;808		break;809	case 192000:810		sample_freq = 0x0E;811		org_sample_freq = 0x01;812		break;813	default:814		break;815	}816 817	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);818	hdmi_enable_audio_clk(hdmi, true);819 820	hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);821	hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);822	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);823	hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);824	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);825	hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);826	hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);827	hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);828 829	hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);830	hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);831	hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);832 833	hdmi_modb(hdmi,  0x3, 0x3, HDMI_FC_DATAUTO3);834 835	/* hbr */836	if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&837	    hdmi->sample_width == 32 && hdmi->sample_non_pcm)838		hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);839 840	if (pdata->enable_audio)841		pdata->enable_audio(hdmi,842				    hdmi->channels,843				    hdmi->sample_width,844				    hdmi->sample_rate,845				    hdmi->sample_non_pcm);846}847 848static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)849{850	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;851 852	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);853 854	hdmi_modb(hdmi,  0, 0x3, HDMI_FC_DATAUTO3);855	if (pdata->disable_audio)856		pdata->disable_audio(hdmi);857 858	hdmi_enable_audio_clk(hdmi, false);859}860 861static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)862{863	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);864}865 866static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)867{868	hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);869}870 871static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)872{873	hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);874	hdmi_enable_audio_clk(hdmi, true);875}876 877static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)878{879	hdmi_enable_audio_clk(hdmi, false);880}881 882void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)883{884	unsigned long flags;885 886	spin_lock_irqsave(&hdmi->audio_lock, flags);887	hdmi->audio_enable = true;888	if (hdmi->enable_audio)889		hdmi->enable_audio(hdmi);890	spin_unlock_irqrestore(&hdmi->audio_lock, flags);891}892EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);893 894void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)895{896	unsigned long flags;897 898	spin_lock_irqsave(&hdmi->audio_lock, flags);899	hdmi->audio_enable = false;900	if (hdmi->disable_audio)901		hdmi->disable_audio(hdmi);902	spin_unlock_irqrestore(&hdmi->audio_lock, flags);903}904EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);905 906static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)907{908	switch (bus_format) {909	case MEDIA_BUS_FMT_RGB888_1X24:910	case MEDIA_BUS_FMT_RGB101010_1X30:911	case MEDIA_BUS_FMT_RGB121212_1X36:912	case MEDIA_BUS_FMT_RGB161616_1X48:913		return true;914 915	default:916		return false;917	}918}919 920static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)921{922	switch (bus_format) {923	case MEDIA_BUS_FMT_YUV8_1X24:924	case MEDIA_BUS_FMT_YUV10_1X30:925	case MEDIA_BUS_FMT_YUV12_1X36:926	case MEDIA_BUS_FMT_YUV16_1X48:927		return true;928 929	default:930		return false;931	}932}933 934static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)935{936	switch (bus_format) {937	case MEDIA_BUS_FMT_UYVY8_1X16:938	case MEDIA_BUS_FMT_UYVY10_1X20:939	case MEDIA_BUS_FMT_UYVY12_1X24:940		return true;941 942	default:943		return false;944	}945}946 947static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)948{949	switch (bus_format) {950	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:951	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:952	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:953	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:954		return true;955 956	default:957		return false;958	}959}960 961static int hdmi_bus_fmt_color_depth(unsigned int bus_format)962{963	switch (bus_format) {964	case MEDIA_BUS_FMT_RGB888_1X24:965	case MEDIA_BUS_FMT_YUV8_1X24:966	case MEDIA_BUS_FMT_UYVY8_1X16:967	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:968		return 8;969 970	case MEDIA_BUS_FMT_RGB101010_1X30:971	case MEDIA_BUS_FMT_YUV10_1X30:972	case MEDIA_BUS_FMT_UYVY10_1X20:973	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:974		return 10;975 976	case MEDIA_BUS_FMT_RGB121212_1X36:977	case MEDIA_BUS_FMT_YUV12_1X36:978	case MEDIA_BUS_FMT_UYVY12_1X24:979	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:980		return 12;981 982	case MEDIA_BUS_FMT_RGB161616_1X48:983	case MEDIA_BUS_FMT_YUV16_1X48:984	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:985		return 16;986 987	default:988		return 0;989	}990}991 992/*993 * this submodule is responsible for the video data synchronization.994 * for example, for RGB 4:4:4 input, the data map is defined as995 *			pin{47~40} <==> R[7:0]996 *			pin{31~24} <==> G[7:0]997 *			pin{15~8}  <==> B[7:0]998 */999static void hdmi_video_sample(struct dw_hdmi *hdmi)1000{1001	int color_format = 0;1002	u8 val;1003 1004	switch (hdmi->hdmi_data.enc_in_bus_format) {1005	case MEDIA_BUS_FMT_RGB888_1X24:1006		color_format = 0x01;1007		break;1008	case MEDIA_BUS_FMT_RGB101010_1X30:1009		color_format = 0x03;1010		break;1011	case MEDIA_BUS_FMT_RGB121212_1X36:1012		color_format = 0x05;1013		break;1014	case MEDIA_BUS_FMT_RGB161616_1X48:1015		color_format = 0x07;1016		break;1017 1018	case MEDIA_BUS_FMT_YUV8_1X24:1019	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:1020		color_format = 0x09;1021		break;1022	case MEDIA_BUS_FMT_YUV10_1X30:1023	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:1024		color_format = 0x0B;1025		break;1026	case MEDIA_BUS_FMT_YUV12_1X36:1027	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:1028		color_format = 0x0D;1029		break;1030	case MEDIA_BUS_FMT_YUV16_1X48:1031	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:1032		color_format = 0x0F;1033		break;1034 1035	case MEDIA_BUS_FMT_UYVY8_1X16:1036		color_format = 0x16;1037		break;1038	case MEDIA_BUS_FMT_UYVY10_1X20:1039		color_format = 0x14;1040		break;1041	case MEDIA_BUS_FMT_UYVY12_1X24:1042		color_format = 0x12;1043		break;1044 1045	default:1046		return;1047	}1048 1049	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |1050		((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &1051		HDMI_TX_INVID0_VIDEO_MAPPING_MASK);1052	hdmi_writeb(hdmi, val, HDMI_TX_INVID0);1053 1054	/* Enable TX stuffing: When DE is inactive, fix the output data to 0 */1055	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |1056		HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |1057		HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;1058	hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);1059	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);1060	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);1061	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);1062	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);1063	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);1064	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);1065}1066 1067static int is_color_space_conversion(struct dw_hdmi *hdmi)1068{1069	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;1070	bool is_input_rgb, is_output_rgb;1071 1072	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);1073	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);1074 1075	return (is_input_rgb != is_output_rgb) ||1076	       (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);1077}1078 1079static int is_color_space_decimation(struct dw_hdmi *hdmi)1080{1081	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))1082		return 0;1083 1084	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||1085	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))1086		return 1;1087 1088	return 0;1089}1090 1091static int is_color_space_interpolation(struct dw_hdmi *hdmi)1092{1093	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))1094		return 0;1095 1096	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||1097	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))1098		return 1;1099 1100	return 0;1101}1102 1103static bool is_csc_needed(struct dw_hdmi *hdmi)1104{1105	return is_color_space_conversion(hdmi) ||1106	       is_color_space_decimation(hdmi) ||1107	       is_color_space_interpolation(hdmi);1108}1109 1110static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)1111{1112	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;1113	bool is_input_rgb, is_output_rgb;1114	unsigned i;1115	u32 csc_scale = 1;1116 1117	is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);1118	is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);1119 1120	if (!is_input_rgb && is_output_rgb) {1121		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)1122			csc_coeff = &csc_coeff_rgb_out_eitu601;1123		else1124			csc_coeff = &csc_coeff_rgb_out_eitu709;1125	} else if (is_input_rgb && !is_output_rgb) {1126		if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)1127			csc_coeff = &csc_coeff_rgb_in_eitu601;1128		else1129			csc_coeff = &csc_coeff_rgb_in_eitu709;1130		csc_scale = 0;1131	} else if (is_input_rgb && is_output_rgb &&1132		   hdmi->hdmi_data.rgb_limited_range) {1133		csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;1134	}1135 1136	/* The CSC registers are sequential, alternating MSB then LSB */1137	for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {1138		u16 coeff_a = (*csc_coeff)[0][i];1139		u16 coeff_b = (*csc_coeff)[1][i];1140		u16 coeff_c = (*csc_coeff)[2][i];1141 1142		hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);1143		hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);1144		hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);1145		hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);1146		hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);1147		hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);1148	}1149 1150	hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,1151		  HDMI_CSC_SCALE);1152}1153 1154static void hdmi_video_csc(struct dw_hdmi *hdmi)1155{1156	int color_depth = 0;1157	int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;1158	int decimation = 0;1159 1160	/* YCC422 interpolation to 444 mode */1161	if (is_color_space_interpolation(hdmi))1162		interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;1163	else if (is_color_space_decimation(hdmi))1164		decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;1165 1166	switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {1167	case 8:1168		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;1169		break;1170	case 10:1171		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;1172		break;1173	case 12:1174		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;1175		break;1176	case 16:1177		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;1178		break;1179 1180	default:1181		return;1182	}1183 1184	/* Configure the CSC registers */1185	hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);1186	hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,1187		  HDMI_CSC_SCALE);1188 1189	dw_hdmi_update_csc_coeffs(hdmi);1190}1191 1192/*1193 * HDMI video packetizer is used to packetize the data.1194 * for example, if input is YCC422 mode or repeater is used,1195 * data should be repacked this module can be bypassed.1196 */1197static void hdmi_video_packetize(struct dw_hdmi *hdmi)1198{1199	unsigned int color_depth = 0;1200	unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;1201	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;1202	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;1203	u8 val, vp_conf;1204	u8 clear_gcp_auto = 0;1205 1206 1207	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||1208	    hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||1209	    hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {1210		switch (hdmi_bus_fmt_color_depth(1211					hdmi->hdmi_data.enc_out_bus_format)) {1212		case 8:1213			color_depth = 4;1214			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;1215			clear_gcp_auto = 1;1216			break;1217		case 10:1218			color_depth = 5;1219			break;1220		case 12:1221			color_depth = 6;1222			break;1223		case 16:1224			color_depth = 7;1225			break;1226		default:1227			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;1228		}1229	} else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {1230		switch (hdmi_bus_fmt_color_depth(1231					hdmi->hdmi_data.enc_out_bus_format)) {1232		case 0:1233		case 8:1234			remap_size = HDMI_VP_REMAP_YCC422_16bit;1235			clear_gcp_auto = 1;1236			break;1237		case 10:1238			remap_size = HDMI_VP_REMAP_YCC422_20bit;1239			break;1240		case 12:1241			remap_size = HDMI_VP_REMAP_YCC422_24bit;1242			break;1243 1244		default:1245			return;1246		}1247		output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;1248	} else {1249		return;1250	}1251 1252	/* set the packetizer registers */1253	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &1254		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |1255		((hdmi_data->pix_repet_factor <<1256		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &1257		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);1258	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);1259 1260	/* HDMI1.4b specification section 6.5.3:1261	 * Source shall only send GCPs with non-zero CD to sinks1262	 * that indicate support for Deep Color.1263	 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).1264	 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.1265	 */1266	val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);1267	if (clear_gcp_auto == 1)1268		val &= ~HDMI_FC_DATAUTO3_GCP_AUTO;1269	else1270		val |= HDMI_FC_DATAUTO3_GCP_AUTO;1271	hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);1272 1273	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,1274		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);1275 1276	/* Data from pixel repeater block */1277	if (hdmi_data->pix_repet_factor > 1) {1278		vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |1279			  HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;1280	} else { /* data from packetizer block */1281		vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |1282			  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;1283	}1284 1285	hdmi_modb(hdmi, vp_conf,1286		  HDMI_VP_CONF_PR_EN_MASK |1287		  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);1288 1289	hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,1290		  HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);1291 1292	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);1293 1294	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {1295		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |1296			  HDMI_VP_CONF_PP_EN_ENABLE |1297			  HDMI_VP_CONF_YCC422_EN_DISABLE;1298	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {1299		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |1300			  HDMI_VP_CONF_PP_EN_DISABLE |1301			  HDMI_VP_CONF_YCC422_EN_ENABLE;1302	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {1303		vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |1304			  HDMI_VP_CONF_PP_EN_DISABLE |1305			  HDMI_VP_CONF_YCC422_EN_DISABLE;1306	} else {1307		return;1308	}1309 1310	hdmi_modb(hdmi, vp_conf,1311		  HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |1312		  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);1313 1314	hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |1315			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,1316		  HDMI_VP_STUFF_PP_STUFFING_MASK |1317		  HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);1318 1319	hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,1320		  HDMI_VP_CONF);1321}1322 1323/* -----------------------------------------------------------------------------1324 * Synopsys PHY Handling1325 */1326 1327static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,1328				       unsigned char bit)1329{1330	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,1331		  HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);1332}1333 1334static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)1335{1336	u32 val;1337 1338	while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {1339		if (msec-- == 0)1340			return false;1341		udelay(1000);1342	}1343	hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);1344 1345	return true;1346}1347 1348void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,1349			   unsigned char addr)1350{1351	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);1352	hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);1353	hdmi_writeb(hdmi, (unsigned char)(data >> 8),1354		    HDMI_PHY_I2CM_DATAO_1_ADDR);1355	hdmi_writeb(hdmi, (unsigned char)(data >> 0),1356		    HDMI_PHY_I2CM_DATAO_0_ADDR);1357	hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,1358		    HDMI_PHY_I2CM_OPERATION_ADDR);1359	hdmi_phy_wait_i2c_done(hdmi, 1000);1360}1361EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);1362 1363/* Filter out invalid setups to avoid configuring SCDC and scrambling */1364static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,1365				 const struct drm_display_info *display)1366{1367	/* Completely disable SCDC support for older controllers */1368	if (hdmi->version < 0x200a)1369		return false;1370 1371	/* Disable if no DDC bus */1372	if (!hdmi->ddc)1373		return false;1374 1375	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */1376	if (!display->hdmi.scdc.supported ||1377	    !display->hdmi.scdc.scrambling.supported)1378		return false;1379 1380	/*1381	 * Disable if display only support low TMDS rates and scrambling1382	 * for low rates is not supported either1383	 */1384	if (!display->hdmi.scdc.scrambling.low_rates &&1385	    display->max_tmds_clock <= 340000)1386		return false;1387 1388	return true;1389}1390 1391/*1392 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:1393 * - The Source shall suspend transmission of the TMDS clock and data1394 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it1395 * from a 0 to a 1 or from a 1 to a 01396 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from1397 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming1398 * transmission of TMDS clock and data1399 *1400 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()1401 * helper should called right before enabling the TMDS Clock and Data in1402 * the PHY configuration callback.1403 */1404void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,1405				       const struct drm_display_info *display)1406{1407	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;1408 1409	/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */1410	if (dw_hdmi_support_scdc(hdmi, display)) {1411		if (mtmdsclock > HDMI14_MAX_TMDSCLK)1412			drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1);1413		else1414			drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0);1415	}1416}1417EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);1418 1419static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)1420{1421	hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,1422			 HDMI_PHY_CONF0_PDZ_OFFSET,1423			 HDMI_PHY_CONF0_PDZ_MASK);1424}1425 1426static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)1427{1428	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,1429			 HDMI_PHY_CONF0_ENTMDS_OFFSET,1430			 HDMI_PHY_CONF0_ENTMDS_MASK);1431}1432 1433static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)1434{1435	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,1436			 HDMI_PHY_CONF0_SVSRET_OFFSET,1437			 HDMI_PHY_CONF0_SVSRET_MASK);1438}1439 1440void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)1441{1442	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,1443			 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,1444			 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);1445}1446EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);1447 1448void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)1449{1450	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,1451			 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,1452			 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);1453}1454EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);1455 1456static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)1457{1458	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,1459			 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,1460			 HDMI_PHY_CONF0_SELDATAENPOL_MASK);1461}1462 1463static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)1464{1465	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,1466			 HDMI_PHY_CONF0_SELDIPIF_OFFSET,1467			 HDMI_PHY_CONF0_SELDIPIF_MASK);1468}1469 1470void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)1471{1472	/* PHY reset. The reset signal is active low on Gen1 PHYs. */1473	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);1474	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);1475}1476EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);1477 1478void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)1479{1480	/* PHY reset. The reset signal is active high on Gen2 PHYs. */1481	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);1482	hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);1483}1484EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);1485 1486void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)1487{1488	hdmi_phy_test_clear(hdmi, 1);1489	hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);1490	hdmi_phy_test_clear(hdmi, 0);1491}1492EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);1493 1494static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)1495{1496	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;1497	unsigned int i;1498	u16 val;1499 1500	if (phy->gen == 1) {1501		dw_hdmi_phy_enable_tmds(hdmi, 0);1502		dw_hdmi_phy_enable_powerdown(hdmi, true);1503		return;1504	}1505 1506	dw_hdmi_phy_gen2_txpwron(hdmi, 0);1507 1508	/*1509	 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went1510	 * to low power mode.1511	 */1512	for (i = 0; i < 5; ++i) {1513		val = hdmi_readb(hdmi, HDMI_PHY_STAT0);1514		if (!(val & HDMI_PHY_TX_PHY_LOCK))1515			break;1516 1517		usleep_range(1000, 2000);1518	}1519 1520	if (val & HDMI_PHY_TX_PHY_LOCK)1521		dev_warn(hdmi->dev, "PHY failed to power down\n");1522	else1523		dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);1524 1525	dw_hdmi_phy_gen2_pddq(hdmi, 1);1526}1527 1528static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)1529{1530	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;1531	unsigned int i;1532	u8 val;1533 1534	if (phy->gen == 1) {1535		dw_hdmi_phy_enable_powerdown(hdmi, false);1536 1537		/* Toggle TMDS enable. */1538		dw_hdmi_phy_enable_tmds(hdmi, 0);1539		dw_hdmi_phy_enable_tmds(hdmi, 1);1540		return 0;1541	}1542 1543	dw_hdmi_phy_gen2_txpwron(hdmi, 1);1544	dw_hdmi_phy_gen2_pddq(hdmi, 0);1545 1546	/* Wait for PHY PLL lock */1547	for (i = 0; i < 5; ++i) {1548		val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;1549		if (val)1550			break;1551 1552		usleep_range(1000, 2000);1553	}1554 1555	if (!val) {1556		dev_err(hdmi->dev, "PHY PLL failed to lock\n");1557		return -ETIMEDOUT;1558	}1559 1560	dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);1561	return 0;1562}1563 1564/*1565 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available1566 * information the DWC MHL PHY has the same register layout and is thus also1567 * supported by this function.1568 */1569static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,1570		const struct dw_hdmi_plat_data *pdata,1571		unsigned long mpixelclock)1572{1573	const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;1574	const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;1575	const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;1576 1577	/* TOFIX Will need 420 specific PHY configuration tables */1578 1579	/* PLL/MPLL Cfg - always match on final entry */1580	for (; mpll_config->mpixelclock != ~0UL; mpll_config++)1581		if (mpixelclock <= mpll_config->mpixelclock)1582			break;1583 1584	for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)1585		if (mpixelclock <= curr_ctrl->mpixelclock)1586			break;1587 1588	for (; phy_config->mpixelclock != ~0UL; phy_config++)1589		if (mpixelclock <= phy_config->mpixelclock)1590			break;1591 1592	if (mpll_config->mpixelclock == ~0UL ||1593	    curr_ctrl->mpixelclock == ~0UL ||1594	    phy_config->mpixelclock == ~0UL)1595		return -EINVAL;1596 1597	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,1598			      HDMI_3D_TX_PHY_CPCE_CTRL);1599	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,1600			      HDMI_3D_TX_PHY_GMPCTRL);1601	dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],1602			      HDMI_3D_TX_PHY_CURRCTRL);1603 1604	dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);1605	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,1606			      HDMI_3D_TX_PHY_MSM_CTRL);1607 1608	dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);1609	dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,1610			      HDMI_3D_TX_PHY_CKSYMTXCTRL);1611	dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,1612			      HDMI_3D_TX_PHY_VLEVCTRL);1613 1614	/* Override and disable clock termination. */1615	dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,1616			      HDMI_3D_TX_PHY_CKCALCTRL);1617 1618	return 0;1619}1620 1621static int hdmi_phy_configure(struct dw_hdmi *hdmi,1622			      const struct drm_display_info *display)1623{1624	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;1625	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;1626	unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;1627	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;1628	int ret;1629 1630	dw_hdmi_phy_power_off(hdmi);1631 1632	dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);1633 1634	/* Leave low power consumption mode by asserting SVSRET. */1635	if (phy->has_svsret)1636		dw_hdmi_phy_enable_svsret(hdmi, 1);1637 1638	dw_hdmi_phy_gen2_reset(hdmi);1639 1640	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);1641 1642	dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);1643 1644	/* Write to the PHY as configured by the platform */1645	if (pdata->configure_phy)1646		ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);1647	else1648		ret = phy->configure(hdmi, pdata, mpixelclock);1649	if (ret) {1650		dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",1651			mpixelclock);1652		return ret;1653	}1654 1655	/* Wait for resuming transmission of TMDS clock and data */1656	if (mtmdsclock > HDMI14_MAX_TMDSCLK)1657		msleep(100);1658 1659	return dw_hdmi_phy_power_on(hdmi);1660}1661 1662static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,1663			    const struct drm_display_info *display,1664			    const struct drm_display_mode *mode)1665{1666	int i, ret;1667 1668	/* HDMI Phy spec says to do the phy initialization sequence twice */1669	for (i = 0; i < 2; i++) {1670		dw_hdmi_phy_sel_data_en_pol(hdmi, 1);1671		dw_hdmi_phy_sel_interface_control(hdmi, 0);1672 1673		ret = hdmi_phy_configure(hdmi, display);1674		if (ret)1675			return ret;1676	}1677 1678	return 0;1679}1680 1681static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)1682{1683	dw_hdmi_phy_power_off(hdmi);1684}1685 1686enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,1687					       void *data)1688{1689	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?1690		connector_status_connected : connector_status_disconnected;1691}1692EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);1693 1694void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,1695			    bool force, bool disabled, bool rxsense)1696{1697	u8 old_mask = hdmi->phy_mask;1698 1699	if (force || disabled || !rxsense)1700		hdmi->phy_mask |= HDMI_PHY_RX_SENSE;1701	else1702		hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;1703 1704	if (old_mask != hdmi->phy_mask)1705		hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);1706}1707EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);1708 1709void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)1710{1711	/*1712	 * Configure the PHY RX SENSE and HPD interrupts polarities and clear1713	 * any pending interrupt.1714	 */1715	hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);1716	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,1717		    HDMI_IH_PHY_STAT0);1718 1719	/* Enable cable hot plug irq. */1720	hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);1721 1722	/* Clear and unmute interrupts. */1723	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,1724		    HDMI_IH_PHY_STAT0);1725	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),1726		    HDMI_IH_MUTE_PHY_STAT0);1727}1728EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);1729 1730static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {1731	.init = dw_hdmi_phy_init,1732	.disable = dw_hdmi_phy_disable,1733	.read_hpd = dw_hdmi_phy_read_hpd,1734	.update_hpd = dw_hdmi_phy_update_hpd,1735	.setup_hpd = dw_hdmi_phy_setup_hpd,1736};1737 1738/* -----------------------------------------------------------------------------1739 * HDMI TX Setup1740 */1741 1742static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)1743{1744	u8 de;1745 1746	if (hdmi->hdmi_data.video_mode.mdataenablepolarity)1747		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;1748	else1749		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;1750 1751	/* disable rx detect */1752	hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,1753		  HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);1754 1755	hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);1756 1757	hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,1758		  HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);1759}1760 1761static void hdmi_config_AVI(struct dw_hdmi *hdmi,1762			    const struct drm_connector *connector,1763			    const struct drm_display_mode *mode)1764{1765	struct hdmi_avi_infoframe frame;1766	u8 val;1767 1768	/* Initialise info frame from DRM mode */1769	drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);1770 1771	if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {1772		drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,1773						   hdmi->hdmi_data.rgb_limited_range ?1774						   HDMI_QUANTIZATION_RANGE_LIMITED :1775						   HDMI_QUANTIZATION_RANGE_FULL);1776	} else {1777		frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;1778		frame.ycc_quantization_range =1779			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;1780	}1781 1782	if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))1783		frame.colorspace = HDMI_COLORSPACE_YUV444;1784	else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))1785		frame.colorspace = HDMI_COLORSPACE_YUV422;1786	else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))1787		frame.colorspace = HDMI_COLORSPACE_YUV420;1788	else1789		frame.colorspace = HDMI_COLORSPACE_RGB;1790 1791	/* Set up colorimetry */1792	if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {1793		switch (hdmi->hdmi_data.enc_out_encoding) {1794		case V4L2_YCBCR_ENC_601:1795			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)1796				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;1797			else1798				frame.colorimetry = HDMI_COLORIMETRY_ITU_601;1799			frame.extended_colorimetry =1800					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;1801			break;1802		case V4L2_YCBCR_ENC_709:1803			if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)1804				frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;1805			else1806				frame.colorimetry = HDMI_COLORIMETRY_ITU_709;1807			frame.extended_colorimetry =1808					HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;1809			break;1810		default: /* Carries no data */1811			frame.colorimetry = HDMI_COLORIMETRY_ITU_601;1812			frame.extended_colorimetry =1813					HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;1814			break;1815		}1816	} else {1817		frame.colorimetry = HDMI_COLORIMETRY_NONE;1818		frame.extended_colorimetry =1819			HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;1820	}1821 1822	/*1823	 * The Designware IP uses a different byte format from standard1824	 * AVI info frames, though generally the bits are in the correct1825	 * bytes.1826	 */1827 1828	/*1829	 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,1830	 * scan info in bits 4,5 rather than 0,1 and active aspect present in1831	 * bit 6 rather than 4.1832	 */1833	val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);1834	if (frame.active_aspect & 15)1835		val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;1836	if (frame.top_bar || frame.bottom_bar)1837		val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;1838	if (frame.left_bar || frame.right_bar)1839		val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;1840	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);1841 1842	/* AVI data byte 2 differences: none */1843	val = ((frame.colorimetry & 0x3) << 6) |1844	      ((frame.picture_aspect & 0x3) << 4) |1845	      (frame.active_aspect & 0xf);1846	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);1847 1848	/* AVI data byte 3 differences: none */1849	val = ((frame.extended_colorimetry & 0x7) << 4) |1850	      ((frame.quantization_range & 0x3) << 2) |1851	      (frame.nups & 0x3);1852	if (frame.itc)1853		val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;1854	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);1855 1856	/* AVI data byte 4 differences: none */1857	val = frame.video_code & 0x7f;1858	hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);1859 1860	/* AVI Data Byte 5- set up input and output pixel repetition */1861	val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<1862		HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &1863		HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |1864		((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<1865		HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &1866		HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);1867	hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);1868 1869	/*1870	 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,1871	 * ycc range in bits 2,3 rather than 6,71872	 */1873	val = ((frame.ycc_quantization_range & 0x3) << 2) |1874	      (frame.content_type & 0x3);1875	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);1876 1877	/* AVI Data Bytes 6-13 */1878	hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);1879	hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);1880	hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);1881	hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);1882	hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);1883	hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);1884	hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);1885	hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);1886}1887 1888static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,1889						  const struct drm_connector *connector,1890						  const struct drm_display_mode *mode)1891{1892	struct hdmi_vendor_infoframe frame;1893	u8 buffer[10];1894	ssize_t err;1895 1896	err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector,1897							  mode);1898	if (err < 0)1899		/*1900		 * Going into that statement does not means vendor infoframe1901		 * fails. It just informed us that vendor infoframe is not1902		 * needed for the selected mode. Only 4k or stereoscopic 3D1903		 * mode requires vendor infoframe. So just simply return.1904		 */1905		return;1906 1907	err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));1908	if (err < 0) {1909		dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",1910			err);1911		return;1912	}1913	hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,1914			HDMI_FC_DATAUTO0_VSD_MASK);1915 1916	/* Set the length of HDMI vendor specific InfoFrame payload */1917	hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);1918 1919	/* Set 24bit IEEE Registration Identifier */1920	hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);1921	hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);1922	hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);1923 1924	/* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */1925	hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);1926	hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);1927 1928	if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)1929		hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);1930 1931	/* Packet frame interpolation */1932	hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);1933 1934	/* Auto packets per frame and line spacing */1935	hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);1936 1937	/* Configures the Frame Composer On RDRB mode */1938	hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,1939			HDMI_FC_DATAUTO0_VSD_MASK);1940}1941 1942static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,1943				      const struct drm_connector *connector)1944{1945	const struct drm_connector_state *conn_state = connector->state;1946	struct hdmi_drm_infoframe frame;1947	u8 buffer[30];1948	ssize_t err;1949	int i;1950 1951	if (!hdmi->plat_data->use_drm_infoframe)1952		return;1953 1954	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,1955		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);1956 1957	err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);1958	if (err < 0)1959		return;1960 1961	err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));1962	if (err < 0) {1963		dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);1964		return;1965	}1966 1967	hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);1968	hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);1969 1970	for (i = 0; i < frame.length; i++)1971		hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);1972 1973	hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);1974	hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,1975		  HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);1976}1977 1978static void hdmi_av_composer(struct dw_hdmi *hdmi,1979			     const struct drm_display_info *display,1980			     const struct drm_display_mode *mode)1981{1982	u8 inv_val, bytes;1983	const struct drm_hdmi_info *hdmi_info = &display->hdmi;1984	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;1985	int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;1986	unsigned int vdisplay, hdisplay;1987 1988	vmode->mpixelclock = mode->clock * 1000;1989 1990	dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);1991 1992	vmode->mtmdsclock = vmode->mpixelclock;1993 1994	if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {1995		switch (hdmi_bus_fmt_color_depth(1996				hdmi->hdmi_data.enc_out_bus_format)) {1997		case 16:1998			vmode->mtmdsclock = vmode->mpixelclock * 2;1999			break;2000		case 12:2001			vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;2002			break;2003		case 10:2004			vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;2005			break;2006		}2007	}2008 2009	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))2010		vmode->mtmdsclock /= 2;2011 2012	dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);2013 2014	/* Set up HDMI_FC_INVIDCONF */2015	inv_val = (hdmi->hdmi_data.hdcp_enable ||2016		   (dw_hdmi_support_scdc(hdmi, display) &&2017		    (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||2018		     hdmi_info->scdc.scrambling.low_rates)) ?2019		HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :2020		HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);2021 2022	inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?2023		HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :2024		HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;2025 2026	inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?2027		HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :2028		HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;2029 2030	inv_val |= (vmode->mdataenablepolarity ?2031		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :2032		HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);2033 2034	if (hdmi->vic == 39)2035		inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;2036	else2037		inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?2038			HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :2039			HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;2040 2041	inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?2042		HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :2043		HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;2044 2045	inv_val |= hdmi->sink_is_hdmi ?2046		HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :2047		HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;2048 2049	hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);2050 2051	hdisplay = mode->hdisplay;2052	hblank = mode->htotal - mode->hdisplay;2053	h_de_hs = mode->hsync_start - mode->hdisplay;2054	hsync_len = mode->hsync_end - mode->hsync_start;2055 2056	/*2057	 * When we're setting a YCbCr420 mode, we need2058	 * to adjust the horizontal timing to suit.2059	 */2060	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {2061		hdisplay /= 2;2062		hblank /= 2;2063		h_de_hs /= 2;2064		hsync_len /= 2;2065	}2066 2067	vdisplay = mode->vdisplay;2068	vblank = mode->vtotal - mode->vdisplay;2069	v_de_vs = mode->vsync_start - mode->vdisplay;2070	vsync_len = mode->vsync_end - mode->vsync_start;2071 2072	/*2073	 * When we're setting an interlaced mode, we need2074	 * to adjust the vertical timing to suit.2075	 */2076	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {2077		vdisplay /= 2;2078		vblank /= 2;2079		v_de_vs /= 2;2080		vsync_len /= 2;2081	}2082 2083	/* Scrambling Control */2084	if (dw_hdmi_support_scdc(hdmi, display)) {2085		if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||2086		    hdmi_info->scdc.scrambling.low_rates) {2087			/*2088			 * HDMI2.0 Specifies the following procedure:2089			 * After the Source Device has determined that2090			 * SCDC_Present is set (=1), the Source Device should2091			 * write the accurate Version of the Source Device2092			 * to the Source Version field in the SCDCS.2093			 * Source Devices compliant shall set the2094			 * Source Version = 1.2095			 */2096			drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,2097				       &bytes);2098			drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,2099				min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));2100 2101			/* Enabled Scrambling in the Sink */2102			drm_scdc_set_scrambling(hdmi->curr_conn, 1);2103 2104			/*2105			 * To activate the scrambler feature, you must ensure2106			 * that the quasi-static configuration bit2107			 * fc_invidconf.HDCP_keepout is set at configuration2108			 * time, before the required mc_swrstzreq.tmdsswrst_req2109			 * reset request is issued.2110			 */2111			hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,2112				    HDMI_MC_SWRSTZ);2113			hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);2114		} else {2115			hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);2116			hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,2117				    HDMI_MC_SWRSTZ);2118			drm_scdc_set_scrambling(hdmi->curr_conn, 0);2119		}2120	}2121 2122	/* Set up horizontal active pixel width */2123	hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);2124	hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);2125 2126	/* Set up vertical active lines */2127	hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);2128	hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);2129 2130	/* Set up horizontal blanking pixel region width */2131	hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);2132	hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);2133 2134	/* Set up vertical blanking pixel region width */2135	hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);2136 2137	/* Set up HSYNC active edge delay width (in pixel clks) */2138	hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);2139	hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);2140 2141	/* Set up VSYNC active edge delay (in lines) */2142	hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);2143 2144	/* Set up HSYNC active pulse width (in pixel clks) */2145	hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);2146	hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);2147 2148	/* Set up VSYNC active edge delay (in lines) */2149	hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);2150}2151 2152/* HDMI Initialization Step B.4 */2153static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)2154{2155	/* control period minimum duration */2156	hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);2157	hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);2158	hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);2159 2160	/* Set to fill TMDS data channels */2161	hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);2162	hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);2163	hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);2164 2165	/* Enable pixel clock and tmds data path */2166	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |2167			   HDMI_MC_CLKDIS_CSCCLK_DISABLE |2168			   HDMI_MC_CLKDIS_AUDCLK_DISABLE |2169			   HDMI_MC_CLKDIS_PREPCLK_DISABLE |2170			   HDMI_MC_CLKDIS_TMDSCLK_DISABLE;2171	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;2172	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);2173 2174	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;2175	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);2176 2177	/* Enable csc path */2178	if (is_csc_needed(hdmi)) {2179		hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;2180		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);2181 2182		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,2183			    HDMI_MC_FLOWCTRL);2184	} else {2185		hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;2186		hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);2187 2188		hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,2189			    HDMI_MC_FLOWCTRL);2190	}2191}2192 2193/* Workaround to clear the overflow condition */2194static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)2195{2196	unsigned int count;2197	unsigned int i;2198	u8 val;2199 2200	/*2201	 * Under some circumstances the Frame Composer arithmetic unit can miss2202	 * an FC register write due to being busy processing the previous one.2203	 * The issue can be worked around by issuing a TMDS software reset and2204	 * then write one of the FC registers several times.2205	 *2206	 * The number of iterations matters and depends on the HDMI TX revision2207	 * (and possibly on the platform).2208	 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others.2209	 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a),2210	 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a)2211	 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround2212	 * with a single iteration.2213	 */2214 2215	switch (hdmi->version) {2216	case 0x130a:2217		count = 4;2218		break;2219	default:2220		count = 1;2221		break;2222	}2223 2224	/* TMDS software reset */2225	hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);2226 2227	val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);2228	for (i = 0; i < count; i++)2229		hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);2230}2231 2232static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)2233{2234	hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,2235		    HDMI_IH_MUTE_FC_STAT2);2236}2237 2238static int dw_hdmi_setup(struct dw_hdmi *hdmi,2239			 const struct drm_connector *connector,2240			 const struct drm_display_mode *mode)2241{2242	int ret;2243 2244	hdmi_disable_overflow_interrupts(hdmi);2245 2246	hdmi->vic = drm_match_cea_mode(mode);2247 2248	if (!hdmi->vic) {2249		dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");2250	} else {2251		dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);2252	}2253 2254	if ((hdmi->vic == 6) || (hdmi->vic == 7) ||2255	    (hdmi->vic == 21) || (hdmi->vic == 22) ||2256	    (hdmi->vic == 2) || (hdmi->vic == 3) ||2257	    (hdmi->vic == 17) || (hdmi->vic == 18))2258		hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;2259	else2260		hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;2261 2262	hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;2263	hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;2264 2265	if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)2266		hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;2267 2268	/* TOFIX: Get input encoding from plat data or fallback to none */2269	if (hdmi->plat_data->input_bus_encoding)2270		hdmi->hdmi_data.enc_in_encoding =2271			hdmi->plat_data->input_bus_encoding;2272	else2273		hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;2274 2275	if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)2276		hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;2277 2278	hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&2279		drm_default_rgb_quant_range(mode) ==2280		HDMI_QUANTIZATION_RANGE_LIMITED;2281 2282	hdmi->hdmi_data.pix_repet_factor = 0;2283	hdmi->hdmi_data.hdcp_enable = 0;2284	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;2285 2286	/* HDMI Initialization Step B.1 */2287	hdmi_av_composer(hdmi, &connector->display_info, mode);2288 2289	/* HDMI Initializateion Step B.2 */2290	ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,2291				  &connector->display_info,2292				  &hdmi->previous_mode);2293	if (ret)2294		return ret;2295	hdmi->phy.enabled = true;2296 2297	/* HDMI Initialization Step B.3 */2298	dw_hdmi_enable_video_path(hdmi);2299 2300	if (hdmi->sink_has_audio) {2301		dev_dbg(hdmi->dev, "sink has audio support\n");2302 2303		/* HDMI Initialization Step E - Configure audio */2304		hdmi_clk_regenerator_update_pixel_clock(hdmi);2305		hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);2306	}2307 2308	/* not for DVI mode */2309	if (hdmi->sink_is_hdmi) {2310		dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);2311 2312		/* HDMI Initialization Step F - Configure AVI InfoFrame */2313		hdmi_config_AVI(hdmi, connector, mode);2314		hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);2315		hdmi_config_drm_infoframe(hdmi, connector);2316	} else {2317		dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);2318	}2319 2320	hdmi_video_packetize(hdmi);2321	hdmi_video_csc(hdmi);2322	hdmi_video_sample(hdmi);2323	hdmi_tx_hdcp_config(hdmi);2324 2325	dw_hdmi_clear_overflow(hdmi);2326 2327	return 0;2328}2329 2330static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)2331{2332	u8 ih_mute;2333 2334	/*2335	 * Boot up defaults are:2336	 * HDMI_IH_MUTE   = 0x03 (disabled)2337	 * HDMI_IH_MUTE_* = 0x00 (enabled)2338	 *2339	 * Disable top level interrupt bits in HDMI block2340	 */2341	ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |2342		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |2343		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;2344 2345	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);2346 2347	/* by default mask all interrupts */2348	hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);2349	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);2350	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);2351	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);2352	hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);2353	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);2354	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);2355	hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);2356	hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);2357	hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);2358	hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);2359	hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);2360	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);2361	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);2362 2363	/* Disable interrupts in the IH_MUTE_* registers */2364	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);2365	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);2366	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);2367	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);2368	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);2369	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);2370	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);2371	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);2372	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);2373	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);2374 2375	/* Enable top level interrupt bits in HDMI block */2376	ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |2377		    HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);2378	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);2379}2380 2381static void dw_hdmi_poweron(struct dw_hdmi *hdmi)2382{2383	hdmi->bridge_is_on = true;2384 2385	/*2386	 * The curr_conn field is guaranteed to be valid here, as this function2387	 * is only be called when !hdmi->disabled.2388	 */2389	dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);2390}2391 2392static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)2393{2394	if (hdmi->phy.enabled) {2395		hdmi->phy.ops->disable(hdmi, hdmi->phy.data);2396		hdmi->phy.enabled = false;2397	}2398 2399	hdmi->bridge_is_on = false;2400}2401 2402static void dw_hdmi_update_power(struct dw_hdmi *hdmi)2403{2404	int force = hdmi->force;2405 2406	if (hdmi->disabled) {2407		force = DRM_FORCE_OFF;2408	} else if (force == DRM_FORCE_UNSPECIFIED) {2409		if (hdmi->rxsense)2410			force = DRM_FORCE_ON;2411		else2412			force = DRM_FORCE_OFF;2413	}2414 2415	if (force == DRM_FORCE_OFF) {2416		if (hdmi->bridge_is_on)2417			dw_hdmi_poweroff(hdmi);2418	} else {2419		if (!hdmi->bridge_is_on)2420			dw_hdmi_poweron(hdmi);2421	}2422}2423 2424/*2425 * Adjust the detection of RXSENSE according to whether we have a forced2426 * connection mode enabled, or whether we have been disabled.  There is2427 * no point processing RXSENSE interrupts if we have a forced connection2428 * state, or DRM has us disabled.2429 *2430 * We also disable rxsense interrupts when we think we're disconnected2431 * to avoid floating TDMS signals giving false rxsense interrupts.2432 *2433 * Note: we still need to listen for HPD interrupts even when DRM has us2434 * disabled so that we can detect a connect event.2435 */2436static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)2437{2438	if (hdmi->phy.ops->update_hpd)2439		hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,2440					  hdmi->force, hdmi->disabled,2441					  hdmi->rxsense);2442}2443 2444static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)2445{2446	enum drm_connector_status result;2447 2448	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);2449	hdmi->last_connector_result = result;2450 2451	return result;2452}2453 2454static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi,2455						struct drm_connector *connector)2456{2457	const struct drm_edid *drm_edid;2458	const struct edid *edid;2459 2460	if (!hdmi->ddc)2461		return NULL;2462 2463	drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);2464	if (!drm_edid) {2465		dev_dbg(hdmi->dev, "failed to get edid\n");2466		return NULL;2467	}2468 2469	/*2470	 * FIXME: This should use connector->display_info.is_hdmi and2471	 * connector->display_info.has_audio from a path that has read the EDID2472	 * and called drm_edid_connector_update().2473	 */2474	edid = drm_edid_raw(drm_edid);2475 2476	dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",2477		edid->width_cm, edid->height_cm);2478 2479	hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);2480	hdmi->sink_has_audio = drm_detect_monitor_audio(edid);2481 2482	return drm_edid;2483}2484 2485/* -----------------------------------------------------------------------------2486 * DRM Connector Operations2487 */2488 2489static enum drm_connector_status2490dw_hdmi_connector_detect(struct drm_connector *connector, bool force)2491{2492	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,2493					     connector);2494	return dw_hdmi_detect(hdmi);2495}2496 2497static int dw_hdmi_connector_get_modes(struct drm_connector *connector)2498{2499	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,2500					     connector);2501	const struct drm_edid *drm_edid;2502	int ret;2503 2504	drm_edid = dw_hdmi_edid_read(hdmi, connector);2505 2506	drm_edid_connector_update(connector, drm_edid);2507	cec_notifier_set_phys_addr(hdmi->cec_notifier,2508				   connector->display_info.source_physical_address);2509	ret = drm_edid_connector_add_modes(connector);2510	drm_edid_free(drm_edid);2511 2512	return ret;2513}2514 2515static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,2516					  struct drm_atomic_state *state)2517{2518	struct drm_connector_state *old_state =2519		drm_atomic_get_old_connector_state(state, connector);2520	struct drm_connector_state *new_state =2521		drm_atomic_get_new_connector_state(state, connector);2522	struct drm_crtc *crtc = new_state->crtc;2523	struct drm_crtc_state *crtc_state;2524 2525	if (!crtc)2526		return 0;2527 2528	if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {2529		crtc_state = drm_atomic_get_crtc_state(state, crtc);2530		if (IS_ERR(crtc_state))2531			return PTR_ERR(crtc_state);2532 2533		crtc_state->mode_changed = true;2534	}2535 2536	return 0;2537}2538 2539static void dw_hdmi_connector_force(struct drm_connector *connector)2540{2541	struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,2542					     connector);2543 2544	mutex_lock(&hdmi->mutex);2545	hdmi->force = connector->force;2546	dw_hdmi_update_power(hdmi);2547	dw_hdmi_update_phy_mask(hdmi);2548	mutex_unlock(&hdmi->mutex);2549}2550 2551static const struct drm_connector_funcs dw_hdmi_connector_funcs = {2552	.fill_modes = drm_helper_probe_single_connector_modes,2553	.detect = dw_hdmi_connector_detect,2554	.destroy = drm_connector_cleanup,2555	.force = dw_hdmi_connector_force,2556	.reset = drm_atomic_helper_connector_reset,2557	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,2558	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,2559};2560 2561static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {2562	.get_modes = dw_hdmi_connector_get_modes,2563	.atomic_check = dw_hdmi_connector_atomic_check,2564};2565 2566static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)2567{2568	struct drm_connector *connector = &hdmi->connector;2569	struct cec_connector_info conn_info;2570	struct cec_notifier *notifier;2571 2572	if (hdmi->version >= 0x200a)2573		connector->ycbcr_420_allowed =2574			hdmi->plat_data->ycbcr_420_allowed;2575	else2576		connector->ycbcr_420_allowed = false;2577 2578	connector->interlace_allowed = 1;2579	connector->polled = DRM_CONNECTOR_POLL_HPD;2580 2581	drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);2582 2583	drm_connector_init_with_ddc(hdmi->bridge.dev, connector,2584				    &dw_hdmi_connector_funcs,2585				    DRM_MODE_CONNECTOR_HDMIA,2586				    hdmi->ddc);2587 2588	/*2589	 * drm_connector_attach_max_bpc_property() requires the2590	 * connector to have a state.2591	 */2592	drm_atomic_helper_connector_reset(connector);2593 2594	drm_connector_attach_max_bpc_property(connector, 8, 16);2595 2596	if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)2597		drm_connector_attach_hdr_output_metadata_property(connector);2598 2599	drm_connector_attach_encoder(connector, hdmi->bridge.encoder);2600 2601	cec_fill_conn_info_from_drm(&conn_info, connector);2602 2603	notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);2604	if (!notifier)2605		return -ENOMEM;2606 2607	mutex_lock(&hdmi->cec_notifier_mutex);2608	hdmi->cec_notifier = notifier;2609	mutex_unlock(&hdmi->cec_notifier_mutex);2610 2611	return 0;2612}2613 2614/* -----------------------------------------------------------------------------2615 * DRM Bridge Operations2616 */2617 2618/*2619 * Possible output formats :2620 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,2621 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,2622 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,2623 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,2624 * - MEDIA_BUS_FMT_YUV16_1X48,2625 * - MEDIA_BUS_FMT_RGB161616_1X48,2626 * - MEDIA_BUS_FMT_UYVY12_1X24,2627 * - MEDIA_BUS_FMT_YUV12_1X36,2628 * - MEDIA_BUS_FMT_RGB121212_1X36,2629 * - MEDIA_BUS_FMT_UYVY10_1X20,2630 * - MEDIA_BUS_FMT_YUV10_1X30,2631 * - MEDIA_BUS_FMT_RGB101010_1X30,2632 * - MEDIA_BUS_FMT_UYVY8_1X16,2633 * - MEDIA_BUS_FMT_YUV8_1X24,2634 * - MEDIA_BUS_FMT_RGB888_1X24,2635 */2636 2637/* Can return a maximum of 11 possible output formats for a mode/connector */2638#define MAX_OUTPUT_SEL_FORMATS	112639 2640static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,2641					struct drm_bridge_state *bridge_state,2642					struct drm_crtc_state *crtc_state,2643					struct drm_connector_state *conn_state,2644					unsigned int *num_output_fmts)2645{2646	struct drm_connector *conn = conn_state->connector;2647	struct drm_display_info *info = &conn->display_info;2648	struct drm_display_mode *mode = &crtc_state->mode;2649	u8 max_bpc = conn_state->max_requested_bpc;2650	bool is_hdmi2_sink = info->hdmi.scdc.supported ||2651			     (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);2652	u32 *output_fmts;2653	unsigned int i = 0;2654 2655	*num_output_fmts = 0;2656 2657	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),2658			      GFP_KERNEL);2659	if (!output_fmts)2660		return NULL;2661 2662	/* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */2663	if (list_is_singular(&bridge->encoder->bridge_chain) ||2664	    list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {2665		*num_output_fmts = 1;2666		output_fmts[0] = MEDIA_BUS_FMT_FIXED;2667 2668		return output_fmts;2669	}2670 2671	/*2672	 * If the current mode enforces 4:2:0, force the output but format2673	 * to 4:2:0 and do not add the YUV422/444/RGB formats2674	 */2675	if (conn->ycbcr_420_allowed &&2676	    (drm_mode_is_420_only(info, mode) ||2677	     (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {2678 2679		/* Order bus formats from 16bit to 8bit if supported */2680		if (max_bpc >= 16 && info->bpc == 16 &&2681		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))2682			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;2683 2684		if (max_bpc >= 12 && info->bpc >= 12 &&2685		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))2686			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;2687 2688		if (max_bpc >= 10 && info->bpc >= 10 &&2689		    (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))2690			output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;2691 2692		/* Default 8bit fallback */2693		output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;2694 2695		if (drm_mode_is_420_only(info, mode)) {2696			*num_output_fmts = i;2697			return output_fmts;2698		}2699	}2700 2701	/*2702	 * Order bus formats from 16bit to 8bit and from YUV422 to RGB2703	 * if supported. In any case the default RGB888 format is added2704	 */2705 2706	/* Default 8bit RGB fallback */2707	output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;2708 2709	if (max_bpc >= 16 && info->bpc == 16) {2710		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)2711			output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;2712 2713		output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;2714	}2715 2716	if (max_bpc >= 12 && info->bpc >= 12) {2717		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)2718			output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;2719 2720		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)2721			output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;2722 2723		output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;2724	}2725 2726	if (max_bpc >= 10 && info->bpc >= 10) {2727		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)2728			output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;2729 2730		if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)2731			output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;2732 2733		output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;2734	}2735 2736	if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)2737		output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;2738 2739	if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)2740		output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;2741 2742	*num_output_fmts = i;2743 2744	return output_fmts;2745}2746 2747/*2748 * Possible input formats :2749 * - MEDIA_BUS_FMT_RGB888_1X242750 * - MEDIA_BUS_FMT_YUV8_1X242751 * - MEDIA_BUS_FMT_UYVY8_1X162752 * - MEDIA_BUS_FMT_UYYVYY8_0_5X242753 * - MEDIA_BUS_FMT_RGB101010_1X302754 * - MEDIA_BUS_FMT_YUV10_1X302755 * - MEDIA_BUS_FMT_UYVY10_1X202756 * - MEDIA_BUS_FMT_UYYVYY10_0_5X302757 * - MEDIA_BUS_FMT_RGB121212_1X362758 * - MEDIA_BUS_FMT_YUV12_1X362759 * - MEDIA_BUS_FMT_UYVY12_1X242760 * - MEDIA_BUS_FMT_UYYVYY12_0_5X362761 * - MEDIA_BUS_FMT_RGB161616_1X482762 * - MEDIA_BUS_FMT_YUV16_1X482763 * - MEDIA_BUS_FMT_UYYVYY16_0_5X482764 */2765 2766/* Can return a maximum of 3 possible input formats for an output format */2767#define MAX_INPUT_SEL_FORMATS	32768 2769static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,2770					struct drm_bridge_state *bridge_state,2771					struct drm_crtc_state *crtc_state,2772					struct drm_connector_state *conn_state,2773					u32 output_fmt,2774					unsigned int *num_input_fmts)2775{2776	u32 *input_fmts;2777	unsigned int i = 0;2778 2779	*num_input_fmts = 0;2780 2781	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),2782			     GFP_KERNEL);2783	if (!input_fmts)2784		return NULL;2785 2786	switch (output_fmt) {2787	/* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */2788	case MEDIA_BUS_FMT_FIXED:2789		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;2790		break;2791	/* 8bit */2792	case MEDIA_BUS_FMT_RGB888_1X24:2793		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;2794		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;2795		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;2796		break;2797	case MEDIA_BUS_FMT_YUV8_1X24:2798		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;2799		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;2800		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;2801		break;2802	case MEDIA_BUS_FMT_UYVY8_1X16:2803		input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;2804		input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;2805		input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;2806		break;2807 2808	/* 10bit */2809	case MEDIA_BUS_FMT_RGB101010_1X30:2810		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;2811		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;2812		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;2813		break;2814	case MEDIA_BUS_FMT_YUV10_1X30:2815		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;2816		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;2817		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;2818		break;2819	case MEDIA_BUS_FMT_UYVY10_1X20:2820		input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;2821		input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;2822		input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;2823		break;2824 2825	/* 12bit */2826	case MEDIA_BUS_FMT_RGB121212_1X36:2827		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;2828		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;2829		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;2830		break;2831	case MEDIA_BUS_FMT_YUV12_1X36:2832		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;2833		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;2834		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;2835		break;2836	case MEDIA_BUS_FMT_UYVY12_1X24:2837		input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;2838		input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;2839		input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;2840		break;2841 2842	/* 16bit */2843	case MEDIA_BUS_FMT_RGB161616_1X48:2844		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;2845		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;2846		break;2847	case MEDIA_BUS_FMT_YUV16_1X48:2848		input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;2849		input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;2850		break;2851 2852	/*YUV 4:2:0 */2853	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:2854	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:2855	case MEDIA_BUS_FMT_UYYVYY12_0_5X36:2856	case MEDIA_BUS_FMT_UYYVYY16_0_5X48:2857		input_fmts[i++] = output_fmt;2858		break;2859	}2860 2861	*num_input_fmts = i;2862 2863	if (*num_input_fmts == 0) {2864		kfree(input_fmts);2865		input_fmts = NULL;2866	}2867 2868	return input_fmts;2869}2870 2871static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,2872				       struct drm_bridge_state *bridge_state,2873				       struct drm_crtc_state *crtc_state,2874				       struct drm_connector_state *conn_state)2875{2876	struct dw_hdmi *hdmi = bridge->driver_private;2877 2878	hdmi->hdmi_data.enc_out_bus_format =2879			bridge_state->output_bus_cfg.format;2880 2881	hdmi->hdmi_data.enc_in_bus_format =2882			bridge_state->input_bus_cfg.format;2883 2884	dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",2885		bridge_state->input_bus_cfg.format,2886		bridge_state->output_bus_cfg.format);2887 2888	return 0;2889}2890 2891static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,2892				 enum drm_bridge_attach_flags flags)2893{2894	struct dw_hdmi *hdmi = bridge->driver_private;2895 2896	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)2897		return drm_bridge_attach(bridge->encoder, hdmi->next_bridge,2898					 bridge, flags);2899 2900	return dw_hdmi_connector_create(hdmi);2901}2902 2903static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)2904{2905	struct dw_hdmi *hdmi = bridge->driver_private;2906 2907	mutex_lock(&hdmi->cec_notifier_mutex);2908	cec_notifier_conn_unregister(hdmi->cec_notifier);2909	hdmi->cec_notifier = NULL;2910	mutex_unlock(&hdmi->cec_notifier_mutex);2911}2912 2913static enum drm_mode_status2914dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,2915			  const struct drm_display_info *info,2916			  const struct drm_display_mode *mode)2917{2918	struct dw_hdmi *hdmi = bridge->driver_private;2919	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;2920	enum drm_mode_status mode_status = MODE_OK;2921 2922	/* We don't support double-clocked modes */2923	if (mode->flags & DRM_MODE_FLAG_DBLCLK)2924		return MODE_BAD;2925 2926	if (pdata->mode_valid)2927		mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,2928						mode);2929 2930	return mode_status;2931}2932 2933static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,2934				    const struct drm_display_mode *orig_mode,2935				    const struct drm_display_mode *mode)2936{2937	struct dw_hdmi *hdmi = bridge->driver_private;2938 2939	mutex_lock(&hdmi->mutex);2940 2941	/* Store the display mode for plugin/DKMS poweron events */2942	drm_mode_copy(&hdmi->previous_mode, mode);2943 2944	mutex_unlock(&hdmi->mutex);2945}2946 2947static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,2948					  struct drm_bridge_state *old_state)2949{2950	struct dw_hdmi *hdmi = bridge->driver_private;2951 2952	mutex_lock(&hdmi->mutex);2953	hdmi->disabled = true;2954	hdmi->curr_conn = NULL;2955	dw_hdmi_update_power(hdmi);2956	dw_hdmi_update_phy_mask(hdmi);2957	handle_plugged_change(hdmi, false);2958	mutex_unlock(&hdmi->mutex);2959}2960 2961static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,2962					 struct drm_bridge_state *old_state)2963{2964	struct dw_hdmi *hdmi = bridge->driver_private;2965	struct drm_atomic_state *state = old_state->base.state;2966	struct drm_connector *connector;2967 2968	connector = drm_atomic_get_new_connector_for_encoder(state,2969							     bridge->encoder);2970 2971	mutex_lock(&hdmi->mutex);2972	hdmi->disabled = false;2973	hdmi->curr_conn = connector;2974	dw_hdmi_update_power(hdmi);2975	dw_hdmi_update_phy_mask(hdmi);2976	handle_plugged_change(hdmi, true);2977	mutex_unlock(&hdmi->mutex);2978}2979 2980static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)2981{2982	struct dw_hdmi *hdmi = bridge->driver_private;2983 2984	return dw_hdmi_detect(hdmi);2985}2986 2987static const struct drm_edid *dw_hdmi_bridge_edid_read(struct drm_bridge *bridge,2988						       struct drm_connector *connector)2989{2990	struct dw_hdmi *hdmi = bridge->driver_private;2991 2992	return dw_hdmi_edid_read(hdmi, connector);2993}2994 2995static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {2996	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,2997	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,2998	.atomic_reset = drm_atomic_helper_bridge_reset,2999	.attach = dw_hdmi_bridge_attach,3000	.detach = dw_hdmi_bridge_detach,3001	.atomic_check = dw_hdmi_bridge_atomic_check,3002	.atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,3003	.atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,3004	.atomic_enable = dw_hdmi_bridge_atomic_enable,3005	.atomic_disable = dw_hdmi_bridge_atomic_disable,3006	.mode_set = dw_hdmi_bridge_mode_set,3007	.mode_valid = dw_hdmi_bridge_mode_valid,3008	.detect = dw_hdmi_bridge_detect,3009	.edid_read = dw_hdmi_bridge_edid_read,3010};3011 3012/* -----------------------------------------------------------------------------3013 * IRQ Handling3014 */3015 3016static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)3017{3018	struct dw_hdmi_i2c *i2c = hdmi->i2c;3019	unsigned int stat;3020 3021	stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);3022	if (!stat)3023		return IRQ_NONE;3024 3025	hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);3026 3027	i2c->stat = stat;3028 3029	complete(&i2c->cmp);3030 3031	return IRQ_HANDLED;3032}3033 3034static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)3035{3036	struct dw_hdmi *hdmi = dev_id;3037	u8 intr_stat;3038	irqreturn_t ret = IRQ_NONE;3039 3040	if (hdmi->i2c)3041		ret = dw_hdmi_i2c_irq(hdmi);3042 3043	intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);3044	if (intr_stat) {3045		hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);3046		return IRQ_WAKE_THREAD;3047	}3048 3049	return ret;3050}3051 3052void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)3053{3054	mutex_lock(&hdmi->mutex);3055 3056	if (!hdmi->force) {3057		/*3058		 * If the RX sense status indicates we're disconnected,3059		 * clear the software rxsense status.3060		 */3061		if (!rx_sense)3062			hdmi->rxsense = false;3063 3064		/*3065		 * Only set the software rxsense status when both3066		 * rxsense and hpd indicates we're connected.3067		 * This avoids what seems to be bad behaviour in3068		 * at least iMX6S versions of the phy.3069		 */3070		if (hpd)3071			hdmi->rxsense = true;3072 3073		dw_hdmi_update_power(hdmi);3074		dw_hdmi_update_phy_mask(hdmi);3075	}3076	mutex_unlock(&hdmi->mutex);3077}3078EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);3079 3080static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)3081{3082	struct dw_hdmi *hdmi = dev_id;3083	u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;3084	enum drm_connector_status status = connector_status_unknown;3085 3086	intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);3087	phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);3088	phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);3089 3090	phy_pol_mask = 0;3091	if (intr_stat & HDMI_IH_PHY_STAT0_HPD)3092		phy_pol_mask |= HDMI_PHY_HPD;3093	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)3094		phy_pol_mask |= HDMI_PHY_RX_SENSE0;3095	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)3096		phy_pol_mask |= HDMI_PHY_RX_SENSE1;3097	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)3098		phy_pol_mask |= HDMI_PHY_RX_SENSE2;3099	if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)3100		phy_pol_mask |= HDMI_PHY_RX_SENSE3;3101 3102	if (phy_pol_mask)3103		hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);3104 3105	/*3106	 * RX sense tells us whether the TDMS transmitters are detecting3107	 * load - in other words, there's something listening on the3108	 * other end of the link.  Use this to decide whether we should3109	 * power on the phy as HPD may be toggled by the sink to merely3110	 * ask the source to re-read the EDID.3111	 */3112	if (intr_stat &3113	    (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {3114		dw_hdmi_setup_rx_sense(hdmi,3115				       phy_stat & HDMI_PHY_HPD,3116				       phy_stat & HDMI_PHY_RX_SENSE);3117 3118		if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {3119			mutex_lock(&hdmi->cec_notifier_mutex);3120			cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);3121			mutex_unlock(&hdmi->cec_notifier_mutex);3122		}3123 3124		if (phy_stat & HDMI_PHY_HPD)3125			status = connector_status_connected;3126 3127		if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE)))3128			status = connector_status_disconnected;3129	}3130 3131	if (status != connector_status_unknown) {3132		dev_dbg(hdmi->dev, "EVENT=%s\n",3133			status == connector_status_connected ?3134			"plugin" : "plugout");3135 3136		if (hdmi->bridge.dev) {3137			drm_helper_hpd_irq_event(hdmi->bridge.dev);3138			drm_bridge_hpd_notify(&hdmi->bridge, status);3139		}3140	}3141 3142	hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);3143	hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),3144		    HDMI_IH_MUTE_PHY_STAT0);3145 3146	return IRQ_HANDLED;3147}3148 3149static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {3150	{3151		.type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,3152		.name = "DWC HDMI TX PHY",3153		.gen = 1,3154	}, {3155		.type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,3156		.name = "DWC MHL PHY + HEAC PHY",3157		.gen = 2,3158		.has_svsret = true,3159		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,3160	}, {3161		.type = DW_HDMI_PHY_DWC_MHL_PHY,3162		.name = "DWC MHL PHY",3163		.gen = 2,3164		.has_svsret = true,3165		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,3166	}, {3167		.type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,3168		.name = "DWC HDMI 3D TX PHY + HEAC PHY",3169		.gen = 2,3170		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,3171	}, {3172		.type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,3173		.name = "DWC HDMI 3D TX PHY",3174		.gen = 2,3175		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,3176	}, {3177		.type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,3178		.name = "DWC HDMI 2.0 TX PHY",3179		.gen = 2,3180		.has_svsret = true,3181		.configure = hdmi_phy_configure_dwc_hdmi_3d_tx,3182	}, {3183		.type = DW_HDMI_PHY_VENDOR_PHY,3184		.name = "Vendor PHY",3185	}3186};3187 3188static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)3189{3190	unsigned int i;3191	u8 phy_type;3192 3193	phy_type = hdmi->plat_data->phy_force_vendor ?3194				DW_HDMI_PHY_VENDOR_PHY :3195				hdmi_readb(hdmi, HDMI_CONFIG2_ID);3196 3197	if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {3198		/* Vendor PHYs require support from the glue layer. */3199		if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {3200			dev_err(hdmi->dev,3201				"Vendor HDMI PHY not supported by glue layer\n");3202			return -ENODEV;3203		}3204 3205		hdmi->phy.ops = hdmi->plat_data->phy_ops;3206		hdmi->phy.data = hdmi->plat_data->phy_data;3207		hdmi->phy.name = hdmi->plat_data->phy_name;3208		return 0;3209	}3210 3211	/* Synopsys PHYs are handled internally. */3212	for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {3213		if (dw_hdmi_phys[i].type == phy_type) {3214			hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;3215			hdmi->phy.name = dw_hdmi_phys[i].name;3216			hdmi->phy.data = (void *)&dw_hdmi_phys[i];3217 3218			if (!dw_hdmi_phys[i].configure &&3219			    !hdmi->plat_data->configure_phy) {3220				dev_err(hdmi->dev, "%s requires platform support\n",3221					hdmi->phy.name);3222				return -ENODEV;3223			}3224 3225			return 0;3226		}3227	}3228 3229	dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);3230	return -ENODEV;3231}3232 3233static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)3234{3235	mutex_lock(&hdmi->mutex);3236	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;3237	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);3238	mutex_unlock(&hdmi->mutex);3239}3240 3241static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)3242{3243	mutex_lock(&hdmi->mutex);3244	hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;3245	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);3246	mutex_unlock(&hdmi->mutex);3247}3248 3249static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {3250	.write = hdmi_writeb,3251	.read = hdmi_readb,3252	.enable = dw_hdmi_cec_enable,3253	.disable = dw_hdmi_cec_disable,3254};3255 3256static const struct regmap_config hdmi_regmap_8bit_config = {3257	.reg_bits	= 32,3258	.val_bits	= 8,3259	.reg_stride	= 1,3260	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR,3261};3262 3263static const struct regmap_config hdmi_regmap_32bit_config = {3264	.reg_bits	= 32,3265	.val_bits	= 32,3266	.reg_stride	= 4,3267	.max_register	= HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,3268};3269 3270static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)3271{3272	initialize_hdmi_ih_mutes(hdmi);3273 3274	/*3275	 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.3276	 * Even if we are using a separate i2c adapter doing this doesn't3277	 * hurt.3278	 */3279	dw_hdmi_i2c_init(hdmi);3280 3281	if (hdmi->phy.ops->setup_hpd)3282		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);3283}3284 3285/* -----------------------------------------------------------------------------3286 * Probe/remove API, used from platforms based on the DRM bridge API.3287 */3288 3289static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi)3290{3291	struct device_node *remote;3292 3293	if (!hdmi->plat_data->output_port)3294		return 0;3295 3296 3297	remote = of_graph_get_remote_node(hdmi->dev->of_node,3298					  hdmi->plat_data->output_port,3299					  -1);3300	if (!remote)3301		return -ENODEV;3302 3303	hdmi->next_bridge = of_drm_find_bridge(remote);3304	of_node_put(remote);3305	if (!hdmi->next_bridge)3306		return -EPROBE_DEFER;3307 3308	return 0;3309}3310 3311bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)3312{3313	return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format);3314}3315EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420);3316 3317struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,3318			      const struct dw_hdmi_plat_data *plat_data)3319{3320	struct device *dev = &pdev->dev;3321	struct device_node *np = dev->of_node;3322	struct platform_device_info pdevinfo;3323	struct device_node *ddc_node;3324	struct dw_hdmi_cec_data cec;3325	struct dw_hdmi *hdmi;3326	struct clk *clk;3327	struct resource *iores = NULL;3328	int irq;3329	int ret;3330	u32 val = 1;3331	u8 prod_id0;3332	u8 prod_id1;3333	u8 config0;3334	u8 config3;3335 3336	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);3337	if (!hdmi)3338		return ERR_PTR(-ENOMEM);3339 3340	hdmi->plat_data = plat_data;3341	hdmi->dev = dev;3342	hdmi->sample_rate = 48000;3343	hdmi->channels = 2;3344	hdmi->disabled = true;3345	hdmi->rxsense = true;3346	hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);3347	hdmi->mc_clkdis = 0x7f;3348	hdmi->last_connector_result = connector_status_disconnected;3349 3350	mutex_init(&hdmi->mutex);3351	mutex_init(&hdmi->audio_mutex);3352	mutex_init(&hdmi->cec_notifier_mutex);3353	spin_lock_init(&hdmi->audio_lock);3354 3355	ret = dw_hdmi_parse_dt(hdmi);3356	if (ret < 0)3357		return ERR_PTR(ret);3358 3359	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);3360	if (ddc_node) {3361		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);3362		of_node_put(ddc_node);3363		if (!hdmi->ddc) {3364			dev_dbg(hdmi->dev, "failed to read ddc node\n");3365			return ERR_PTR(-EPROBE_DEFER);3366		}3367 3368	} else {3369		dev_dbg(hdmi->dev, "no ddc property found\n");3370	}3371 3372	if (!plat_data->regm) {3373		const struct regmap_config *reg_config;3374 3375		of_property_read_u32(np, "reg-io-width", &val);3376		switch (val) {3377		case 4:3378			reg_config = &hdmi_regmap_32bit_config;3379			hdmi->reg_shift = 2;3380			break;3381		case 1:3382			reg_config = &hdmi_regmap_8bit_config;3383			break;3384		default:3385			dev_err(dev, "reg-io-width must be 1 or 4\n");3386			return ERR_PTR(-EINVAL);3387		}3388 3389		iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);3390		hdmi->regs = devm_ioremap_resource(dev, iores);3391		if (IS_ERR(hdmi->regs)) {3392			ret = PTR_ERR(hdmi->regs);3393			goto err_res;3394		}3395 3396		hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);3397		if (IS_ERR(hdmi->regm)) {3398			dev_err(dev, "Failed to configure regmap\n");3399			ret = PTR_ERR(hdmi->regm);3400			goto err_res;3401		}3402	} else {3403		hdmi->regm = plat_data->regm;3404	}3405 3406	clk = devm_clk_get_enabled(hdmi->dev, "isfr");3407	if (IS_ERR(clk)) {3408		ret = PTR_ERR(clk);3409		dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);3410		goto err_res;3411	}3412 3413	clk = devm_clk_get_enabled(hdmi->dev, "iahb");3414	if (IS_ERR(clk)) {3415		ret = PTR_ERR(clk);3416		dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);3417		goto err_res;3418	}3419 3420	clk = devm_clk_get_optional_enabled(hdmi->dev, "cec");3421	if (IS_ERR(clk)) {3422		ret = PTR_ERR(clk);3423		if (ret != -EPROBE_DEFER)3424			dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",3425				ret);3426		goto err_res;3427	}3428 3429	/* Product and revision IDs */3430	hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)3431		      | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);3432	prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);3433	prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);3434 3435	if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||3436	    (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {3437		dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",3438			hdmi->version, prod_id0, prod_id1);3439		ret = -ENODEV;3440		goto err_res;3441	}3442 3443	ret = dw_hdmi_detect_phy(hdmi);3444	if (ret < 0)3445		goto err_res;3446 3447	dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",3448		 hdmi->version >> 12, hdmi->version & 0xfff,3449		 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",3450		 hdmi->phy.name);3451 3452	dw_hdmi_init_hw(hdmi);3453 3454	irq = platform_get_irq(pdev, 0);3455	if (irq < 0) {3456		ret = irq;3457		goto err_res;3458	}3459 3460	ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,3461					dw_hdmi_irq, IRQF_SHARED,3462					dev_name(dev), hdmi);3463	if (ret)3464		goto err_res;3465 3466	/*3467	 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator3468	 * N and cts values before enabling phy3469	 */3470	hdmi_init_clk_regenerator(hdmi);3471 3472	/* If DDC bus is not specified, try to register HDMI I2C bus */3473	if (!hdmi->ddc) {3474		/* Look for (optional) stuff related to unwedging */3475		hdmi->pinctrl = devm_pinctrl_get(dev);3476		if (!IS_ERR(hdmi->pinctrl)) {3477			hdmi->unwedge_state =3478				pinctrl_lookup_state(hdmi->pinctrl, "unwedge");3479			hdmi->default_state =3480				pinctrl_lookup_state(hdmi->pinctrl, "default");3481 3482			if (IS_ERR(hdmi->default_state) ||3483			    IS_ERR(hdmi->unwedge_state)) {3484				if (!IS_ERR(hdmi->unwedge_state))3485					dev_warn(dev,3486						 "Unwedge requires default pinctrl\n");3487				hdmi->default_state = NULL;3488				hdmi->unwedge_state = NULL;3489			}3490		}3491 3492		hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);3493		if (IS_ERR(hdmi->ddc))3494			hdmi->ddc = NULL;3495	}3496 3497	hdmi->bridge.driver_private = hdmi;3498	hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;3499	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID3500			 | DRM_BRIDGE_OP_HPD;3501	hdmi->bridge.interlace_allowed = true;3502	hdmi->bridge.ddc = hdmi->ddc;3503	hdmi->bridge.of_node = pdev->dev.of_node;3504	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;3505 3506	memset(&pdevinfo, 0, sizeof(pdevinfo));3507	pdevinfo.parent = dev;3508	pdevinfo.id = PLATFORM_DEVID_AUTO;3509 3510	config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);3511	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);3512 3513	if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {3514		struct dw_hdmi_audio_data audio;3515 3516		audio.phys = iores->start;3517		audio.base = hdmi->regs;3518		audio.irq = irq;3519		audio.hdmi = hdmi;3520		audio.get_eld = hdmi_audio_get_eld;3521		hdmi->enable_audio = dw_hdmi_ahb_audio_enable;3522		hdmi->disable_audio = dw_hdmi_ahb_audio_disable;3523 3524		pdevinfo.name = "dw-hdmi-ahb-audio";3525		pdevinfo.data = &audio;3526		pdevinfo.size_data = sizeof(audio);3527		pdevinfo.dma_mask = DMA_BIT_MASK(32);3528		hdmi->audio = platform_device_register_full(&pdevinfo);3529	} else if (config0 & HDMI_CONFIG0_I2S) {3530		struct dw_hdmi_i2s_audio_data audio;3531 3532		audio.hdmi	= hdmi;3533		audio.get_eld	= hdmi_audio_get_eld;3534		audio.write	= hdmi_writeb;3535		audio.read	= hdmi_readb;3536		hdmi->enable_audio = dw_hdmi_i2s_audio_enable;3537		hdmi->disable_audio = dw_hdmi_i2s_audio_disable;3538 3539		pdevinfo.name = "dw-hdmi-i2s-audio";3540		pdevinfo.data = &audio;3541		pdevinfo.size_data = sizeof(audio);3542		pdevinfo.dma_mask = DMA_BIT_MASK(32);3543		hdmi->audio = platform_device_register_full(&pdevinfo);3544	} else if (iores && config3 & HDMI_CONFIG3_GPAUD) {3545		struct dw_hdmi_audio_data audio;3546 3547		audio.phys = iores->start;3548		audio.base = hdmi->regs;3549		audio.irq = irq;3550		audio.hdmi = hdmi;3551		audio.get_eld = hdmi_audio_get_eld;3552 3553		hdmi->enable_audio = dw_hdmi_gp_audio_enable;3554		hdmi->disable_audio = dw_hdmi_gp_audio_disable;3555 3556		pdevinfo.name = "dw-hdmi-gp-audio";3557		pdevinfo.id = PLATFORM_DEVID_NONE;3558		pdevinfo.data = &audio;3559		pdevinfo.size_data = sizeof(audio);3560		pdevinfo.dma_mask = DMA_BIT_MASK(32);3561		hdmi->audio = platform_device_register_full(&pdevinfo);3562	}3563 3564	if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {3565		cec.hdmi = hdmi;3566		cec.ops = &dw_hdmi_cec_ops;3567		cec.irq = irq;3568 3569		pdevinfo.name = "dw-hdmi-cec";3570		pdevinfo.data = &cec;3571		pdevinfo.size_data = sizeof(cec);3572		pdevinfo.dma_mask = 0;3573 3574		hdmi->cec = platform_device_register_full(&pdevinfo);3575	}3576 3577	drm_bridge_add(&hdmi->bridge);3578 3579	return hdmi;3580 3581err_res:3582	i2c_put_adapter(hdmi->ddc);3583 3584	return ERR_PTR(ret);3585}3586EXPORT_SYMBOL_GPL(dw_hdmi_probe);3587 3588void dw_hdmi_remove(struct dw_hdmi *hdmi)3589{3590	drm_bridge_remove(&hdmi->bridge);3591 3592	if (hdmi->audio && !IS_ERR(hdmi->audio))3593		platform_device_unregister(hdmi->audio);3594	if (!IS_ERR(hdmi->cec))3595		platform_device_unregister(hdmi->cec);3596 3597	/* Disable all interrupts */3598	hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);3599 3600	if (hdmi->i2c)3601		i2c_del_adapter(&hdmi->i2c->adap);3602	else3603		i2c_put_adapter(hdmi->ddc);3604}3605EXPORT_SYMBOL_GPL(dw_hdmi_remove);3606 3607/* -----------------------------------------------------------------------------3608 * Bind/unbind API, used from platforms based on the component framework.3609 */3610struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,3611			     struct drm_encoder *encoder,3612			     const struct dw_hdmi_plat_data *plat_data)3613{3614	struct dw_hdmi *hdmi;3615	int ret;3616 3617	hdmi = dw_hdmi_probe(pdev, plat_data);3618	if (IS_ERR(hdmi))3619		return hdmi;3620 3621	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);3622	if (ret) {3623		dw_hdmi_remove(hdmi);3624		return ERR_PTR(ret);3625	}3626 3627	return hdmi;3628}3629EXPORT_SYMBOL_GPL(dw_hdmi_bind);3630 3631void dw_hdmi_unbind(struct dw_hdmi *hdmi)3632{3633	dw_hdmi_remove(hdmi);3634}3635EXPORT_SYMBOL_GPL(dw_hdmi_unbind);3636 3637void dw_hdmi_resume(struct dw_hdmi *hdmi)3638{3639	dw_hdmi_init_hw(hdmi);3640}3641EXPORT_SYMBOL_GPL(dw_hdmi_resume);3642 3643MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");3644MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");3645MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");3646MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");3647MODULE_DESCRIPTION("DW HDMI transmitter driver");3648MODULE_LICENSE("GPL");3649MODULE_ALIAS("platform:dw-hdmi");3650