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1#ifndef STATE_XML2#define STATE_XML3 4/* Autogenerated file, DO NOT EDIT manually!5 6This file was generated by the rules-ng-ng headergen tool in this git repository:7http://0x04.net/cgit/index.cgi/rules-ng-ng8git clone git://0x04.net/rules-ng-ng9 10The rules-ng-ng source files this header was generated from are:11- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)12- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)13- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)14- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)15- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)16- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)17- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)18- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)19- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)20 21Copyright (C) 2012-2024 by the following authors:22- Wladimir J. van der Laan <laanwj@gmail.com>23- Christian Gmeiner <christian.gmeiner@gmail.com>24- Lucas Stach <l.stach@pengutronix.de>25- Russell King <rmk@arm.linux.org.uk>26 27Permission is hereby granted, free of charge, to any person obtaining a28copy of this software and associated documentation files (the "Software"),29to deal in the Software without restriction, including without limitation30the rights to use, copy, modify, merge, publish, distribute, sub license,31and/or sell copies of the Software, and to permit persons to whom the32Software is furnished to do so, subject to the following conditions:33 34The above copyright notice and this permission notice (including the35next paragraph) shall be included in all copies or substantial portions36of the Software.37 38THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR39IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,40FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL41THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER42LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING43FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER44DEALINGS IN THE SOFTWARE.45*/46 47 48#define VARYING_COMPONENT_USE_UNUSED 0x0000000049#define VARYING_COMPONENT_USE_USED 0x0000000150#define VARYING_COMPONENT_USE_POINTCOORD_X 0x0000000251#define VARYING_COMPONENT_USE_POINTCOORD_Y 0x0000000352#define FE_DATA_TYPE_BYTE 0x0000000053#define FE_DATA_TYPE_UNSIGNED_BYTE 0x0000000154#define FE_DATA_TYPE_SHORT 0x0000000255#define FE_DATA_TYPE_UNSIGNED_SHORT 0x0000000356#define FE_DATA_TYPE_INT 0x0000000457#define FE_DATA_TYPE_UNSIGNED_INT 0x0000000558#define FE_DATA_TYPE_INT_2_10_10_10_REV 0x0000000659#define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x0000000760#define FE_DATA_TYPE_FLOAT 0x0000000861#define FE_DATA_TYPE_HALF_FLOAT 0x0000000962#define FE_DATA_TYPE_FIXED 0x0000000b63#define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c64#define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d65#define FE_DATA_TYPE_BYTE_I 0x0000000e66#define FE_DATA_TYPE_SHORT_I 0x0000000f67#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff68#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 069#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)70#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff000071#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 1672#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK)73#define VIVS_FE 0x0000000074 75#define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0))76#define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x0000000477#define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x0000001078#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f79#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 080#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)81#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x0000003082#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 483#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)84#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x0000008085#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x0000070086#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT 887#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)88#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x0000300089#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT 1290#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK)91#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c00092#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 1493#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x0000000094#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x0000400095#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x0000800096#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff000097#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 1698#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)99#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000100#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT 24101#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)102 103#define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640104 105#define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644106 107#define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648108#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003109#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0110#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000111#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001112#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002113#define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100114 115#define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c116 117#define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650118 119#define VIVS_FE_COMMAND_ADDRESS 0x00000654120 121#define VIVS_FE_COMMAND_CONTROL 0x00000658122#define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff123#define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0124#define VIVS_FE_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)125#define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000126 127#define VIVS_FE_DMA_STATUS 0x0000065c128 129#define VIVS_FE_DMA_DEBUG_STATE 0x00000660130#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f131#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0132#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000133#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001134#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002135#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003136#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004137#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005138#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006139#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007140#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008141#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009142#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a143#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b144#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c145#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d146#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e147#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f148#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010149#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011150#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012151#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013152#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014153#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015154#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300155#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT 8156#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000157#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100158#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200159#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300160#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00161#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT 10162#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000163#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400164#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800165#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000166#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT 12167#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000168#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000169#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000170#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000171#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT 14172#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000173#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000174#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000175#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000176#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT 16177#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000178#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000179#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000180 181#define VIVS_FE_DMA_ADDRESS 0x00000664182 183#define VIVS_FE_DMA_LOW 0x00000668184 185#define VIVS_FE_DMA_HIGH 0x0000066c186 187#define VIVS_FE_AUTO_FLUSH 0x00000670188 189#define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674190 191#define VIVS_FE_UNK00678 0x00000678192 193#define VIVS_FE_UNK0067C 0x0000067c194 195#define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))196#define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004197#define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008198 199#define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0))200 201#define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0))202 203#define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))204#define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004205#define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010206 207#define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0))208 209#define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0))210 211#define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0))212 213#define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))214 215#define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4216#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001217#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002218#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00219#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8220#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK)221#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000222#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16223#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK)224 225#define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))226#define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004227#define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002228 229#define VIVS_FE_HALTI5_UNK007D8 0x000007d8230 231#define VIVS_FE_DESC_START 0x000007dc232 233#define VIVS_FE_DESC_END 0x000007e0234 235#define VIVS_FE_DESC_AVAIL 0x000007e4236#define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f237#define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0238#define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)239 240#define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8241 242#define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4243 244#define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8245 246#define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc247 248#define VIVS_GL 0x00000000249 250#define VIVS_GL_PIPE_SELECT 0x00003800251#define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001252#define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0253#define VIVS_GL_PIPE_SELECT_PIPE(x) (((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)254 255#define VIVS_GL_EVENT 0x00003804256#define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f257#define VIVS_GL_EVENT_EVENT_ID__SHIFT 0258#define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)259#define VIVS_GL_EVENT_FROM_FE 0x00000020260#define VIVS_GL_EVENT_FROM_PE 0x00000040261#define VIVS_GL_EVENT_FROM_BLT 0x00000080262#define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00263#define VIVS_GL_EVENT_SOURCE__SHIFT 8264#define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)265 266#define VIVS_GL_SEMAPHORE_TOKEN 0x00003808267#define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f268#define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0269#define VIVS_GL_SEMAPHORE_TOKEN_FROM(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)270#define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00271#define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8272#define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)273#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000274#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28275#define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)276 277#define VIVS_GL_FLUSH_CACHE 0x0000380c278#define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001279#define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002280#define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004281#define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008282#define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010283#define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020284#define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040285#define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400286#define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800287#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000288#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000289#define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000290 291#define VIVS_GL_FLUSH_MMU 0x00003810292#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001293#define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002294#define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004295#define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008296#define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010297 298#define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814299#define VIVS_GL_VERTEX_ELEMENT_CONFIG_UNK0 0x00000001300#define VIVS_GL_VERTEX_ELEMENT_CONFIG_REUSE 0x00000010301 302#define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818303#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003304#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0305#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000306#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001307#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002308#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008309#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0310#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT 4311#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)312#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100313#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000314#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT 12315#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)316#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000317#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000318#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT 16319#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)320#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000321 322#define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c323#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff324#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0325#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)326 327#define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820328 329#define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824330 331#define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0))332#define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004333#define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002334#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003335#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0336#define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)337#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c338#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT 2339#define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)340#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030341#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT 4342#define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)343#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0344#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT 6345#define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)346#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300347#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT 8348#define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)349#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00350#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT 10351#define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)352#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000353#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT 12354#define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)355#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000356#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT 14357#define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)358#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000359#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT 16360#define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)361#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000362#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT 18363#define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)364#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000365#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT 20366#define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)367#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000368#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT 22369#define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)370#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000371#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT 24372#define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)373#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000374#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT 26375#define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)376#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000377#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT 28378#define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)379#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000380#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30381#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)382 383#define VIVS_GL_UNK0382C 0x0000382c384 385#define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830386 387#define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834388 389#define VIVS_GL_UNK03838 0x00003838390 391#define VIVS_GL_API_MODE 0x0000384c392#define VIVS_GL_API_MODE_OPENGL 0x00000000393#define VIVS_GL_API_MODE_OPENVG 0x00000001394#define VIVS_GL_API_MODE_OPENCL 0x00000002395 396#define VIVS_GL_CONTEXT_POINTER 0x00003850397 398#define VIVS_GL_UNK03854 0x00003854399 400#define VIVS_GL_BUG_FIXES 0x00003860401 402#define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868403 404#define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c405 406#define VIVS_GL_USC_CONTROL 0x00003884407#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007408#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0409#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK)410#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00411#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8412#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK)413#define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000414#define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16415#define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK)416 417#define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888418#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f419#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0420#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK)421#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00422#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8423#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK)424#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000425#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16426#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK)427#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000428#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24429#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK)430 431#define VIVS_GL_GS_UNK0388C 0x0000388c432 433#define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898434 435#define VIVS_GL_SHADER_INDEX 0x0000389c436 437#define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0))438#define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004439#define VIVS_GL_GS_UNK038A0__LEN 0x00000008440 441#define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0))442#define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004443#define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010444 445#define VIVS_GL_SECURITY_UNK3900 0x00003900446 447#define VIVS_GL_SECURITY_UNK3904 0x00003904448 449#define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908450#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007451#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0452#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK)453 454#define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0))455#define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004456#define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004457#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff458#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0459#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK)460 461#define VIVS_GL_NN_CONFIG 0x00003930462#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003463#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0464#define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK)465#define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004466#define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008467#define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010468#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060469#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5470#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK)471#define VIVS_GL_NN_CONFIG_UNK7 0x00000080472#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00473#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8474#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK)475#define VIVS_GL_NN_CONFIG_UNK12 0x00001000476 477#define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938478 479#define VIVS_GL_OCB_REMAP_START 0x0000393c480 481#define VIVS_GL_OCB_REMAP_END 0x00003940482 483#define VIVS_GL_TP_CONFIG 0x0000394c484 485#define VIVS_GL_UNK03950 0x00003950486 487#define VIVS_GL_UNK03A00 0x00003a00488#define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007489#define VIVS_GL_UNK03A00_UNK0__SHIFT 0490#define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK)491 492#define VIVS_GL_UNK03A04 0x00003a04493 494#define VIVS_GL_UNK03A08 0x00003a08495 496#define VIVS_GL_UNK03A0C 0x00003a0c497 498#define VIVS_GL_UNK03A10 0x00003a10499 500#define VIVS_GL_STALL_TOKEN 0x00003c00501#define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f502#define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0503#define VIVS_GL_STALL_TOKEN_FROM(x) (((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)504#define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00505#define VIVS_GL_STALL_TOKEN_TO__SHIFT 8506#define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)507#define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000508#define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000509 510#define VIVS_NFE 0x00000000511 512#define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))513#define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004514#define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010515 516#define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0))517 518#define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0))519 520#define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0))521 522#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))523 524#define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))525#define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004526#define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020527 528#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0))529#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f530#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0531#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)532#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030533#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4534#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)535#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700536#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8537#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)538#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000539#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12540#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)541#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000542#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14543#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000544#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000545#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000546#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16547#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)548 549#define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0))550 551#define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0))552 553#define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0))554 555#define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0))556 557#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0))558#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff559#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0560#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)561#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800562 563#define VIVS_DUMMY 0x00000000564 565#define VIVS_DUMMY_DUMMY 0x0003fffc566 567#define VIVS_WD 0x00000000568 569#define VIVS_WD_UNK18404 0x00018404570#define VIVS_WD_UNK18404_UNK0__MASK 0x00000003571#define VIVS_WD_UNK18404_UNK0__SHIFT 0572#define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK)573 574 575#endif /* STATE_XML */576