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1#ifndef STATE_HI_XML2#define STATE_HI_XML3 4/* Autogenerated file, DO NOT EDIT manually!5 6This file was generated by the rules-ng-ng headergen tool in this git repository:7http://0x04.net/cgit/index.cgi/rules-ng-ng8git clone git://0x04.net/rules-ng-ng9 10The rules-ng-ng source files this header was generated from are:11- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)12- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)13- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)14- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)15- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)16- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)17- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)18- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)19- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)20 21Copyright (C) 2012-2023 by the following authors:22- Wladimir J. van der Laan <laanwj@gmail.com>23- Christian Gmeiner <christian.gmeiner@gmail.com>24- Lucas Stach <l.stach@pengutronix.de>25- Russell King <rmk@arm.linux.org.uk>26 27Permission is hereby granted, free of charge, to any person obtaining a28copy of this software and associated documentation files (the "Software"),29to deal in the Software without restriction, including without limitation30the rights to use, copy, modify, merge, publish, distribute, sub license,31and/or sell copies of the Software, and to permit persons to whom the32Software is furnished to do so, subject to the following conditions:33 34The above copyright notice and this permission notice (including the35next paragraph) shall be included in all copies or substantial portions36of the Software.37 38THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR39IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,40FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL41THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER42LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING43FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER44DEALINGS IN THE SOFTWARE.45*/46 47 48#define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x0000000149#define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x0000000250#define MMU_EXCEPTION_WRITE_VIOLATION 0x0000000351#define MMU_EXCEPTION_OUT_OF_BOUND 0x0000000452#define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x0000000553#define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x0000000654#define VIVS_HI 0x0000000055 56#define VIVS_HI_CLOCK_CONTROL 0x0000000057#define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x0000000158#define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x0000000259#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc60#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 261#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK)62#define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x0000020063#define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x0000040064#define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x0000080065#define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x0000100066#define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x0001000067#define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x0002000068#define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x0004000069#define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x0008000070#define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f0000071#define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 2072#define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK)73 74#define VIVS_HI_IDLE_STATE 0x0000000475#define VIVS_HI_IDLE_STATE_FE 0x0000000176#define VIVS_HI_IDLE_STATE_DE 0x0000000277#define VIVS_HI_IDLE_STATE_PE 0x0000000478#define VIVS_HI_IDLE_STATE_SH 0x0000000879#define VIVS_HI_IDLE_STATE_PA 0x0000001080#define VIVS_HI_IDLE_STATE_SE 0x0000002081#define VIVS_HI_IDLE_STATE_RA 0x0000004082#define VIVS_HI_IDLE_STATE_TX 0x0000008083#define VIVS_HI_IDLE_STATE_VG 0x0000010084#define VIVS_HI_IDLE_STATE_IM 0x0000020085#define VIVS_HI_IDLE_STATE_FP 0x0000040086#define VIVS_HI_IDLE_STATE_TS 0x0000080087#define VIVS_HI_IDLE_STATE_BL 0x0000100088#define VIVS_HI_IDLE_STATE_ASYNCFE 0x0000200089#define VIVS_HI_IDLE_STATE_MC 0x0000400090#define VIVS_HI_IDLE_STATE_PPA 0x0000800091#define VIVS_HI_IDLE_STATE_WD 0x0001000092#define VIVS_HI_IDLE_STATE_NN 0x0002000093#define VIVS_HI_IDLE_STATE_TP 0x0004000094#define VIVS_HI_IDLE_STATE_AXI_LP 0x8000000095 96#define VIVS_HI_AXI_CONFIG 0x0000000897#define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f98#define VIVS_HI_AXI_CONFIG_AWID__SHIFT 099#define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK)100#define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0101#define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4102#define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK)103#define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00104#define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8105#define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK)106#define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000107#define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12108#define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK)109 110#define VIVS_HI_AXI_STATUS 0x0000000c111#define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f112#define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0113#define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK)114#define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0115#define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4116#define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK)117#define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100118#define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200119 120#define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010121#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff122#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0123#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)124#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000125#define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000126 127#define VIVS_HI_INTR_ENBL 0x00000014128#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff129#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0130#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK)131 132#define VIVS_HI_CHIP_IDENTITY 0x00000018133#define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000134#define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24135#define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK)136#define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000137#define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16138#define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK)139#define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000140#define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12141#define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK)142 143#define VIVS_HI_CHIP_FEATURE 0x0000001c144 145#define VIVS_HI_CHIP_MODEL 0x00000020146 147#define VIVS_HI_CHIP_REV 0x00000024148 149#define VIVS_HI_CHIP_DATE 0x00000028150 151#define VIVS_HI_CHIP_TIME 0x0000002c152 153#define VIVS_HI_CHIP_CUSTOMER_ID 0x00000030154 155#define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034156 157#define VIVS_HI_CACHE_CONTROL 0x00000038158 159#define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c160 161#define VIVS_HI_PROFILE_READ_BYTES8 0x00000040162 163#define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044164 165#define VIVS_HI_CHIP_SPECS 0x00000048166#define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f167#define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0168#define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK)169#define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0170#define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4171#define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK)172#define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00173#define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8174#define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK)175#define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000176#define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12177#define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK)178#define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000179#define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20180#define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK)181#define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000182#define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25183#define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK)184#define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000185#define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28186#define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK)187 188#define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c189 190#define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050191 192#define VIVS_HI_PROFILE_READ_BURSTS 0x00000058193 194#define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c195 196#define VIVS_HI_PROFILE_READ_LASTS 0x00000060197 198#define VIVS_HI_GP_OUT0 0x00000064199 200#define VIVS_HI_GP_OUT1 0x00000068201 202#define VIVS_HI_GP_OUT2 0x0000006c203 204#define VIVS_HI_AXI_CONTROL 0x00000070205#define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001206 207#define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074208 209#define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078210 211#define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c212 213#define VIVS_HI_CHIP_SPECS_2 0x00000080214#define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff215#define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0216#define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK)217#define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00218#define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8219#define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK)220#define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000221#define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16222#define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK)223 224#define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084225 226#define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088227 228#define VIVS_HI_CHIP_SPECS_3 0x0000008c229#define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0230#define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4231#define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK)232#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007233#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0234#define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK)235 236#define VIVS_HI_COMPRESSION_FLAGS 0x00000090237#define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040238 239#define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094240 241#define VIVS_HI_CHIP_SPECS_4 0x0000009c242#define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000243#define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12244#define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK)245 246#define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0247 248#define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8249 250#define VIVS_HI_BLT_INTR 0x000000d4251 252#define VIVS_HI_CHIP_ECO_ID 0x000000e8253 254#define VIVS_HI_AUXBIT 0x000000ec255 256#define VIVS_PM 0x00000000257 258#define VIVS_PM_POWER_CONTROLS 0x00000100259#define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001260#define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002261#define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004262#define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0263#define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4264#define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK)265#define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000266#define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16267#define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK)268 269#define VIVS_PM_MODULE_CONTROLS 0x00000104270#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001271#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002272#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004273#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008274#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010275#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020276#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040277#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080278#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU 0x00000400279#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000280#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000281#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN 0x00400000282 283#define VIVS_PM_MODULE_STATUS 0x00000108284#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001285#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002286#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004287#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008288#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010289#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020290#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040291#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080292 293#define VIVS_PM_PULSE_EATER 0x0000010c294#define VIVS_PM_PULSE_EATER_DISABLE 0x00000001295#define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00296#define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8297#define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK)298#define VIVS_PM_PULSE_EATER_UNK16 0x00010000299#define VIVS_PM_PULSE_EATER_UNK17 0x00020000300#define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000301#define VIVS_PM_PULSE_EATER_UNK19 0x00080000302#define VIVS_PM_PULSE_EATER_UNK20 0x00100000303#define VIVS_PM_PULSE_EATER_UNK22 0x00400000304#define VIVS_PM_PULSE_EATER_UNK23 0x00800000305 306#define VIVS_MMUv2 0x00000000307 308#define VIVS_MMUv2_SAFE_ADDRESS 0x00000180309 310#define VIVS_MMUv2_CONFIGURATION 0x00000184311#define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001312#define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0313#define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000314#define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001315#define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008316#define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010317#define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4318#define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010319#define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080320#define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100321#define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00322#define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10323#define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK)324 325#define VIVS_MMUv2_STATUS 0x00000188326#define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x0000000f327#define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0328#define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK)329#define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x000000f0330#define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4331#define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK)332#define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000f00333#define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8334#define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK)335#define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x0000f000336#define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12337#define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK)338 339#define VIVS_MMUv2_CONTROL 0x0000018c340#define VIVS_MMUv2_CONTROL_ENABLE 0x00000001341 342#define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0))343#define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004344#define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004345 346#define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4347 348#define VIVS_MMUv2_PTA_CONFIG 0x000001ac349#define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff350#define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0351#define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK)352#define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000353 354#define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0))355#define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004356#define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008357 358#define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380359 360#define VIVS_MMUv2_SEC_STATUS 0x00000384361#define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003362#define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0363#define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK)364#define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030365#define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4366#define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK)367#define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300368#define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8369#define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK)370#define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000371#define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12372#define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK)373 374#define VIVS_MMUv2_SEC_CONTROL 0x00000388375#define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001376 377#define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c378 379#define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390380 381#define VIVS_MMUv2_PTA_CONTROL 0x00000394382#define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001383 384#define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398385 386#define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c387 388#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0389#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff390#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0391#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK)392#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000393#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000394#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16395#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK)396#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000397 398#define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4399#define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff400#define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0401#define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK)402#define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000403 404#define VIVS_MMUv2_AHB_CONTROL 0x000003a8405#define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001406#define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002407 408#define VIVS_MC 0x00000000409 410#define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400411 412#define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404413 414#define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408415 416#define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c417 418#define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410419 420#define VIVS_MC_DEBUG_MEMORY 0x00000414421#define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008422#define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000423#define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000424 425#define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418426 427#define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c428 429#define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420430 431#define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424432 433#define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428434 435#define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c436 437#define VIVS_MC_MEMORY_FLUSH 0x00000430438 439#define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438440 441#define VIVS_MC_DEBUG_READ0 0x0000043c442 443#define VIVS_MC_DEBUG_READ1 0x00000440444 445#define VIVS_MC_DEBUG_WRITE 0x00000444446 447#define VIVS_MC_PROFILE_RA_READ 0x00000448448 449#define VIVS_MC_PROFILE_TX_READ 0x0000044c450 451#define VIVS_MC_PROFILE_FE_READ 0x00000450452 453#define VIVS_MC_PROFILE_PE_READ 0x00000454454 455#define VIVS_MC_PROFILE_DE_READ 0x00000458456 457#define VIVS_MC_PROFILE_SH_READ 0x0000045c458 459#define VIVS_MC_PROFILE_PA_READ 0x00000460460 461#define VIVS_MC_PROFILE_SE_READ 0x00000464462 463#define VIVS_MC_PROFILE_MC_READ 0x00000468464 465#define VIVS_MC_PROFILE_HI_READ 0x0000046c466 467#define VIVS_MC_PROFILE_CONFIG0 0x00000470468#define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff469#define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0470#define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT 0x0000000a471#define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT 0x0000000b472#define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT 0x0000000c473#define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f474#define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_LK_COUNT 0x00000010475#define VIVS_MC_PROFILE_CONFIG0_FE_STALL_COUNT 0x00000011476#define VIVS_MC_PROFILE_CONFIG0_FE_PROCESS_COUNT 0x00000012477#define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00478#define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8479#define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00480#define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000481#define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16482#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000483#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000484#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000485#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000486#define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000487#define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000488#define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000489#define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24490#define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000491#define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000492#define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000493#define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000494#define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000495#define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000496#define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000497#define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000498#define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000499#define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000500 501#define VIVS_MC_PROFILE_CONFIG1 0x00000474502#define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff503#define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0504#define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003505#define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004506#define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005507#define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006508#define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007509#define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008510#define VIVS_MC_PROFILE_CONFIG1_PA_DROPED_PRIM_COUNTER 0x00000009511#define VIVS_MC_PROFILE_CONFIG1_PA_FRUSTUM_CLIPPED_PRIM_COUNTER 0x0000000a512#define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f513#define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00514#define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8515#define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000516#define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100517#define VIVS_MC_PROFILE_CONFIG1_SE_TRIVIAL_REJECTED_LINE_COUNT 0x00000400518#define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00519#define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000520#define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16521#define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000522#define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000523#define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000524#define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000525#define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000526#define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000527#define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000528#define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000529#define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_HZ_CACHE_MISS_COUNTER 0x00110000530#define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_HZ_CACHE_MISS_COUNTER 0x00120000531#define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000532#define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24533#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000534#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000535#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000536#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000537#define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000538#define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000539#define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000540#define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000541#define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000542#define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000543#define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000544 545#define VIVS_MC_PROFILE_CONFIG2 0x00000478546#define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff547#define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0548#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001549#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002550#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003551#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_COLORPIPE 0x00000004552#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_COLORPIPE 0x00000005553#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_DEPTHPIPE 0x00000007554#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_SENTOUT_FROM_DEPTHPIPE 0x00000008555#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_DEPTHPIPE 0x00000009556#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_DEPTHPIPE 0x0000000a557#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_DEPTHPIPE 0x0000000b558#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_OTHERS 0x0000000c559#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_OTHERS 0x0000000d560#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_FROM_OTHERS 0x0000000e561#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_OTHERS 0x0000000f562#define VIVS_MC_PROFILE_CONFIG2_MC_FE_READ_BANDWIDTH 0x00000015563#define VIVS_MC_PROFILE_CONFIG2_MC_MMU_READ_BANDWIDTH 0x00000016564#define VIVS_MC_PROFILE_CONFIG2_MC_BLT_READ_BANDWIDTH 0x00000017565#define VIVS_MC_PROFILE_CONFIG2_MC_SH0_READ_BANDWIDTH 0x00000018566#define VIVS_MC_PROFILE_CONFIG2_MC_SH1_READ_BANDWIDTH 0x00000019567#define VIVS_MC_PROFILE_CONFIG2_MC_PE_WRITE_BANDWIDTH 0x0000001a568#define VIVS_MC_PROFILE_CONFIG2_MC_BLT_WRITE_BANDWIDTH 0x0000001b569#define VIVS_MC_PROFILE_CONFIG2_MC_SH0_WRITE_BANDWIDTH 0x0000001c570#define VIVS_MC_PROFILE_CONFIG2_MC_SH1_WRITE_BANDWIDTH 0x0000001d571#define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00572#define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8573#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000574#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100575#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200576#define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00577#define VIVS_MC_PROFILE_CONFIG2_L2__MASK 0x00ff0000578#define VIVS_MC_PROFILE_CONFIG2_L2__SHIFT 16579#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_READ_REQUEST_COUNT 0x00000000580#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_WRITE_REQUEST_COUNT 0x00040000581#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI1_WRITE_REQUEST_COUNT 0x00050000582#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI0 0x00080000583#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI1 0x00090000584#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI0 0x000c0000585#define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI1 0x000d0000586#define VIVS_MC_PROFILE_CONFIG2_L2_RESET 0x000f0000587#define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_MINMAX_LATENCY 0x00100000588#define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_LATENCY 0x00110000589#define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_REQUEST_COUNT 0x00120000590#define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_MINMAX_LATENCY 0x00130000591#define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_LATENCY 0x00140000592#define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_REQUEST_COUNT 0x00150000593#define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000594#define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24595#define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000596 597#define VIVS_MC_PROFILE_CONFIG3 0x0000047c598 599#define VIVS_MC_BUS_CONFIG 0x00000480600#define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f601#define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0602#define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK)603#define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0604#define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4605#define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK)606 607#define VIVS_MC_START_COMPOSITION 0x00000554608 609#define VIVS_MC_FLAGS 0x00000558610#define VIVS_MC_FLAGS_128B_MERGE 0x00000001611#define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000612 613#define VIVS_MC_L2_CACHE_CONFIG 0x0000055c614 615#define VIVS_MC_PROFILE_L2_READ 0x00000564616 617#define VIVS_MC_MC_LATENCY_RESET 0x00000568618 619#define VIVS_MC_MC_AXI_MAX_MIN_LATENCY 0x0000056c620 621#define VIVS_MC_MC_AXI_TOTAL_LATENCY 0x00000570622 623#define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574624 625#define VIVS_DEC400EX 0x00000000626 627#define VIVS_DEC400EX_UNK00800 0x00000800628 629#define VIVS_DEC400EX_UNK00808 0x00000808630 631 632#endif /* STATE_HI_XML */633