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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 *4 * Cloned from drivers/media/video/s5p-tv/regs-mixer.h5 *6 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.7 * http://www.samsung.com/8 *9 * Mixer register header file for Samsung Mixer driver10*/11#ifndef SAMSUNG_REGS_MIXER_H12#define SAMSUNG_REGS_MIXER_H13 14/*15 * Register part16 */17#define MXR_STATUS 0x000018#define MXR_CFG 0x000419#define MXR_INT_EN 0x000820#define MXR_INT_STATUS 0x000C21#define MXR_LAYER_CFG 0x001022#define MXR_VIDEO_CFG 0x001423#define MXR_GRAPHIC0_CFG 0x002024#define MXR_GRAPHIC0_BASE 0x002425#define MXR_GRAPHIC0_SPAN 0x002826#define MXR_GRAPHIC0_SXY 0x002C27#define MXR_GRAPHIC0_WH 0x003028#define MXR_GRAPHIC0_DXY 0x003429#define MXR_GRAPHIC0_BLANK 0x003830#define MXR_GRAPHIC1_CFG 0x004031#define MXR_GRAPHIC1_BASE 0x004432#define MXR_GRAPHIC1_SPAN 0x004833#define MXR_GRAPHIC1_SXY 0x004C34#define MXR_GRAPHIC1_WH 0x005035#define MXR_GRAPHIC1_DXY 0x005436#define MXR_GRAPHIC1_BLANK 0x005837#define MXR_BG_CFG 0x006038#define MXR_BG_COLOR0 0x006439#define MXR_BG_COLOR1 0x006840#define MXR_BG_COLOR2 0x006C41#define MXR_CM_COEFF_Y 0x008042#define MXR_CM_COEFF_CB 0x008443#define MXR_CM_COEFF_CR 0x008844#define MXR_MO 0x030445#define MXR_RESOLUTION 0x031046 47#define MXR_CFG_S 0x200448#define MXR_GRAPHIC0_BASE_S 0x202449#define MXR_GRAPHIC1_BASE_S 0x204450 51/* for parametrized access to layer registers */52#define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20)53#define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20)54#define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20)55#define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20)56#define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20)57#define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20)58#define MXR_GRAPHIC_BLANK(i) (0x0038 + (i) * 0x20)59#define MXR_GRAPHIC_BASE_S(i) (0x2024 + (i) * 0x20)60 61/*62 * Bit definition part63 */64 65/* generates mask for range of bits */66#define MXR_MASK(high_bit, low_bit) \67 (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))68 69#define MXR_MASK_VAL(val, high_bit, low_bit) \70 (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))71 72/* bits for MXR_STATUS */73#define MXR_STATUS_SOFT_RESET (1 << 8)74#define MXR_STATUS_16_BURST (1 << 7)75#define MXR_STATUS_BURST_MASK (1 << 7)76#define MXR_STATUS_BIG_ENDIAN (1 << 3)77#define MXR_STATUS_ENDIAN_MASK (1 << 3)78#define MXR_STATUS_SYNC_ENABLE (1 << 2)79#define MXR_STATUS_REG_IDLE (1 << 1)80#define MXR_STATUS_REG_RUN (1 << 0)81 82/* bits for MXR_CFG */83#define MXR_CFG_LAYER_UPDATE (1 << 31)84#define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29)85#define MXR_CFG_QUANT_RANGE_FULL (0 << 9)86#define MXR_CFG_QUANT_RANGE_LIMITED (1 << 9)87#define MXR_CFG_RGB601 (0 << 10)88#define MXR_CFG_RGB709 (1 << 10)89 90#define MXR_CFG_RGB_FMT_MASK 0x60091#define MXR_CFG_OUT_YUV444 (0 << 8)92#define MXR_CFG_OUT_RGB888 (1 << 8)93#define MXR_CFG_OUT_MASK (1 << 8)94#define MXR_CFG_DST_SDO (0 << 7)95#define MXR_CFG_DST_HDMI (1 << 7)96#define MXR_CFG_DST_MASK (1 << 7)97#define MXR_CFG_SCAN_HD_720 (0 << 6)98#define MXR_CFG_SCAN_HD_1080 (1 << 6)99#define MXR_CFG_GRP1_ENABLE (1 << 5)100#define MXR_CFG_GRP0_ENABLE (1 << 4)101#define MXR_CFG_VP_ENABLE (1 << 3)102#define MXR_CFG_SCAN_INTERLACE (0 << 2)103#define MXR_CFG_SCAN_PROGRESSIVE (1 << 2)104#define MXR_CFG_SCAN_NTSC (0 << 1)105#define MXR_CFG_SCAN_PAL (1 << 1)106#define MXR_CFG_SCAN_SD (0 << 0)107#define MXR_CFG_SCAN_HD (1 << 0)108#define MXR_CFG_SCAN_MASK 0x47109 110/* bits for MXR_VIDEO_CFG */111#define MXR_VID_CFG_BLEND_EN (1 << 16)112 113/* bits for MXR_GRAPHICn_CFG */114#define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21)115#define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20)116#define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17)117#define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16)118#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20) | 0xff)119#define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8)120#define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0)121#define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)122 123/* bits for MXR_GRAPHICn_WH */124#define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28)125#define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12)126#define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16)127#define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)128 129/* bits for MXR_RESOLUTION */130#define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16)131#define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0)132 133/* bits for MXR_GRAPHICn_SXY */134#define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16)135#define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0)136 137/* bits for MXR_GRAPHICn_DXY */138#define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16)139#define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0)140 141/* bits for MXR_INT_EN */142#define MXR_INT_EN_VSYNC (1 << 11)143#define MXR_INT_EN_ALL (0x0f << 8)144 145/* bits for MXR_INT_STATUS */146#define MXR_INT_CLEAR_VSYNC (1 << 11)147#define MXR_INT_STATUS_VSYNC (1 << 0)148 149/* bits for MXR_LAYER_CFG */150#define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8)151#define MXR_LAYER_CFG_GRP1_MASK MXR_LAYER_CFG_GRP1_VAL(~0)152#define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4)153#define MXR_LAYER_CFG_GRP0_MASK MXR_LAYER_CFG_GRP0_VAL(~0)154#define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0)155#define MXR_LAYER_CFG_VP_MASK MXR_LAYER_CFG_VP_VAL(~0)156 157/* bits for MXR_CM_COEFF_Y */158#define MXR_CM_COEFF_RGB_FULL (1 << 30)159 160#endif /* SAMSUNG_REGS_MIXER_H */161 162