205 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* Hisilicon Hibmc SoC drm driver3 *4 * Based on the bochs drm driver.5 *6 * Copyright (c) 2016 Huawei Limited.7 *8 * Author:9 * Rongrong Zou <zourongrong@huawei.com>10 * Rongrong Zou <zourongrong@gmail.com>11 * Jianhua Li <lijianhua@huawei.com>12 */13 14#ifndef HIBMC_DRM_HW_H15#define HIBMC_DRM_HW_H16 17/* register definition */18#define HIBMC_MISC_CTRL 0x419 20#define HIBMC_MSCCTL_LOCALMEM_RESET(x) ((x) << 6)21#define HIBMC_MSCCTL_LOCALMEM_RESET_MASK 0x4022 23#define HIBMC_CURRENT_GATE 0x00004024#define HIBMC_CURR_GATE_DISPLAY(x) ((x) << 2)25#define HIBMC_CURR_GATE_DISPLAY_MASK 0x426 27#define HIBMC_CURR_GATE_LOCALMEM(x) ((x) << 1)28#define HIBMC_CURR_GATE_LOCALMEM_MASK 0x229 30#define HIBMC_MODE0_GATE 0x00004431#define HIBMC_MODE1_GATE 0x00004832#define HIBMC_POWER_MODE_CTRL 0x00004C33 34#define HIBMC_PW_MODE_CTL_OSC_INPUT(x) ((x) << 3)35#define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK 0x836 37#define HIBMC_PW_MODE_CTL_MODE(x) ((x) << 0)38#define HIBMC_PW_MODE_CTL_MODE_MASK 0x0339#define HIBMC_PW_MODE_CTL_MODE_SHIFT 040 41#define HIBMC_PW_MODE_CTL_MODE_MODE0 042#define HIBMC_PW_MODE_CTL_MODE_MODE1 143#define HIBMC_PW_MODE_CTL_MODE_SLEEP 244 45#define HIBMC_PANEL_PLL_CTRL 0x00005C46#define HIBMC_CRT_PLL_CTRL 0x00006047 48#define HIBMC_PLL_CTRL_BYPASS(x) ((x) << 18)49#define HIBMC_PLL_CTRL_BYPASS_MASK 0x4000050 51#define HIBMC_PLL_CTRL_POWER(x) ((x) << 17)52#define HIBMC_PLL_CTRL_POWER_MASK 0x2000053 54#define HIBMC_PLL_CTRL_INPUT(x) ((x) << 16)55#define HIBMC_PLL_CTRL_INPUT_MASK 0x1000056 57#define HIBMC_PLL_CTRL_POD(x) ((x) << 14)58#define HIBMC_PLL_CTRL_POD_MASK 0xC00059 60#define HIBMC_PLL_CTRL_OD(x) ((x) << 12)61#define HIBMC_PLL_CTRL_OD_MASK 0x300062 63#define HIBMC_PLL_CTRL_N(x) ((x) << 8)64#define HIBMC_PLL_CTRL_N_MASK 0xF0065 66#define HIBMC_PLL_CTRL_M(x) ((x) << 0)67#define HIBMC_PLL_CTRL_M_MASK 0xFF68 69#define HIBMC_CRT_DISP_CTL 0x8020070 71#define HIBMC_CRT_DISP_CTL_DPMS(x) ((x) << 30)72#define HIBMC_CRT_DISP_CTL_DPMS_MASK 0xc000000073 74#define HIBMC_CRT_DPMS_ON 075#define HIBMC_CRT_DPMS_OFF 376 77#define HIBMC_CRT_DISP_CTL_CRTSELECT(x) ((x) << 25)78#define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK 0x200000079 80#define HIBMC_CRTSELECT_CRT 181 82#define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x) ((x) << 14)83#define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK 0x400084 85#define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x) ((x) << 13)86#define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK 0x200087 88#define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x) ((x) << 12)89#define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK 0x100090 91#define HIBMC_CRT_DISP_CTL_TIMING(x) ((x) << 8)92#define HIBMC_CRT_DISP_CTL_TIMING_MASK 0x10093 94#define HIBMC_CTL_DISP_CTL_GAMMA(x) ((x) << 3)95#define HIBMC_CTL_DISP_CTL_GAMMA_MASK 0x0896 97#define HIBMC_CRT_DISP_CTL_PLANE(x) ((x) << 2)98#define HIBMC_CRT_DISP_CTL_PLANE_MASK 499 100#define HIBMC_CRT_DISP_CTL_FORMAT(x) ((x) << 0)101#define HIBMC_CRT_DISP_CTL_FORMAT_MASK 0x03102 103#define HIBMC_CRT_FB_ADDRESS 0x080204104 105#define HIBMC_CRT_FB_WIDTH 0x080208106#define HIBMC_CRT_FB_WIDTH_WIDTH(x) ((x) << 16)107#define HIBMC_CRT_FB_WIDTH_WIDTH_MASK 0x3FFF0000108#define HIBMC_CRT_FB_WIDTH_OFFS(x) ((x) << 0)109#define HIBMC_CRT_FB_WIDTH_OFFS_MASK 0x3FFF110 111#define HIBMC_CRT_HORZ_TOTAL 0x08020C112#define HIBMC_CRT_HORZ_TOTAL_TOTAL(x) ((x) << 16)113#define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK 0xFFF0000114 115#define HIBMC_CRT_HORZ_TOTAL_DISP_END(x) ((x) << 0)116#define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK 0xFFF117 118#define HIBMC_CRT_HORZ_SYNC 0x080210119#define HIBMC_CRT_HORZ_SYNC_WIDTH(x) ((x) << 16)120#define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK 0xFF0000121 122#define HIBMC_CRT_HORZ_SYNC_START(x) ((x) << 0)123#define HIBMC_CRT_HORZ_SYNC_START_MASK 0xFFF124 125#define HIBMC_CRT_VERT_TOTAL 0x080214126#define HIBMC_CRT_VERT_TOTAL_TOTAL(x) ((x) << 16)127#define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK 0x7FFF0000128 129#define HIBMC_CRT_VERT_TOTAL_DISP_END(x) ((x) << 0)130#define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK 0x7FF131 132#define HIBMC_CRT_VERT_SYNC 0x080218133#define HIBMC_CRT_VERT_SYNC_HEIGHT(x) ((x) << 16)134#define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK 0x3F0000135 136#define HIBMC_CRT_VERT_SYNC_START(x) ((x) << 0)137#define HIBMC_CRT_VERT_SYNC_START_MASK 0x7FF138 139/* Auto Centering */140#define HIBMC_CRT_AUTO_CENTERING_TL 0x080280141#define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x) ((x) << 16)142#define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK 0x7FF0000143 144#define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x) ((x) << 0)145#define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7FF146 147#define HIBMC_CRT_AUTO_CENTERING_BR 0x080284148#define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x) ((x) << 16)149#define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK 0x7FF0000150 151#define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x) ((x) << 0)152#define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7FF153 154/* register to control panel output */155#define HIBMC_DISPLAY_CONTROL_HISILE 0x80288156#define HIBMC_DISPLAY_CONTROL_FPVDDEN(x) ((x) << 0)157#define HIBMC_DISPLAY_CONTROL_PANELDATE(x) ((x) << 1)158#define HIBMC_DISPLAY_CONTROL_FPEN(x) ((x) << 2)159#define HIBMC_DISPLAY_CONTROL_VBIASEN(x) ((x) << 3)160 161#define HIBMC_RAW_INTERRUPT 0x80290162#define HIBMC_RAW_INTERRUPT_VBLANK(x) ((x) << 2)163#define HIBMC_RAW_INTERRUPT_VBLANK_MASK 0x4164 165#define HIBMC_RAW_INTERRUPT_EN 0x80298166#define HIBMC_RAW_INTERRUPT_EN_VBLANK(x) ((x) << 2)167#define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK 0x4168 169/* register and values for PLL control */170#define CRT_PLL1_HS 0x802a8171#define CRT_PLL1_HS_OUTER_BYPASS(x) ((x) << 30)172#define CRT_PLL1_HS_INTER_BYPASS(x) ((x) << 29)173#define CRT_PLL1_HS_POWERON(x) ((x) << 24)174 175#define CRT_PLL1_HS_25MHZ 0x23d40f02176#define CRT_PLL1_HS_40MHZ 0x23940801177#define CRT_PLL1_HS_65MHZ 0x23940d01178#define CRT_PLL1_HS_78MHZ 0x23540F82179#define CRT_PLL1_HS_74MHZ 0x23941dc2180#define CRT_PLL1_HS_80MHZ 0x23941001181#define CRT_PLL1_HS_80MHZ_1152 0x23540fc2182#define CRT_PLL1_HS_106MHZ 0x237C1641183#define CRT_PLL1_HS_108MHZ 0x23b41b01184#define CRT_PLL1_HS_162MHZ 0x23480681185#define CRT_PLL1_HS_148MHZ 0x23541dc2186#define CRT_PLL1_HS_193MHZ 0x234807c1187 188#define CRT_PLL2_HS 0x802ac189#define CRT_PLL2_HS_25MHZ 0x206B851E190#define CRT_PLL2_HS_40MHZ 0x30000000191#define CRT_PLL2_HS_65MHZ 0x40000000192#define CRT_PLL2_HS_78MHZ 0x50E147AE193#define CRT_PLL2_HS_74MHZ 0x602B6AE7194#define CRT_PLL2_HS_80MHZ 0x70000000195#define CRT_PLL2_HS_106MHZ 0x0075c28f196#define CRT_PLL2_HS_108MHZ 0x80000000197#define CRT_PLL2_HS_162MHZ 0xA0000000198#define CRT_PLL2_HS_148MHZ 0xB0CCCCCD199#define CRT_PLL2_HS_193MHZ 0xC0872B02200 201#define HIBMC_CRT_PALETTE 0x80C00202 203#define HIBMC_FIELD(field, value) (field(value) & field##_MASK)204#endif205