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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2016 Linaro Limited.4 * Copyright (c) 2014-2016 HiSilicon Limited.5 */6 7#ifndef __DW_DSI_REG_H__8#define __DW_DSI_REG_H__9 10#include <linux/io.h>11 12#define MASK(x) (BIT(x) - 1)13 14/*15 * regs16 */17#define PWR_UP 0x04 /* Core power-up */18#define RESET 019#define POWERUP BIT(0)20#define PHY_IF_CFG 0xA4 /* D-PHY interface configuration */21#define CLKMGR_CFG 0x08 /* the internal clock dividers */22#define PHY_RSTZ 0xA0 /* D-PHY reset control */23#define PHY_ENABLECLK BIT(2)24#define PHY_UNRSTZ BIT(1)25#define PHY_UNSHUTDOWNZ BIT(0)26#define PHY_TST_CTRL0 0xB4 /* D-PHY test interface control 0 */27#define PHY_TST_CTRL1 0xB8 /* D-PHY test interface control 1 */28#define CLK_TLPX 0x1029#define CLK_THS_PREPARE 0x1130#define CLK_THS_ZERO 0x1231#define CLK_THS_TRAIL 0x1332#define CLK_TWAKEUP 0x1433#define DATA_TLPX(x) (0x20 + ((x) << 4))34#define DATA_THS_PREPARE(x) (0x21 + ((x) << 4))35#define DATA_THS_ZERO(x) (0x22 + ((x) << 4))36#define DATA_THS_TRAIL(x) (0x23 + ((x) << 4))37#define DATA_TTA_GO(x) (0x24 + ((x) << 4))38#define DATA_TTA_GET(x) (0x25 + ((x) << 4))39#define DATA_TWAKEUP(x) (0x26 + ((x) << 4))40#define PHY_CFG_I 0x6041#define PHY_CFG_PLL_I 0x6342#define PHY_CFG_PLL_II 0x6443#define PHY_CFG_PLL_III 0x6544#define PHY_CFG_PLL_IV 0x6645#define PHY_CFG_PLL_V 0x6746#define DPI_COLOR_CODING 0x10 /* DPI color coding */47#define DPI_CFG_POL 0x14 /* DPI polarity configuration */48#define VID_HSA_TIME 0x48 /* Horizontal Sync Active time */49#define VID_HBP_TIME 0x4C /* Horizontal Back Porch time */50#define VID_HLINE_TIME 0x50 /* Line time */51#define VID_VSA_LINES 0x54 /* Vertical Sync Active period */52#define VID_VBP_LINES 0x58 /* Vertical Back Porch period */53#define VID_VFP_LINES 0x5C /* Vertical Front Porch period */54#define VID_VACTIVE_LINES 0x60 /* Vertical resolution */55#define VID_PKT_SIZE 0x3C /* Video packet size */56#define VID_MODE_CFG 0x38 /* Video mode configuration */57#define PHY_TMR_CFG 0x9C /* Data lanes timing configuration */58#define BTA_TO_CNT 0x8C /* Response timeout definition */59#define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */60#define CLK_DATA_TMR_CFG 0xCC61#define LPCLK_CTRL 0x94 /* Low-power in clock lane */62#define PHY_TXREQUESTCLKHS BIT(0)63#define MODE_CFG 0x34 /* Video or Command mode selection */64#define PHY_STATUS 0xB0 /* D-PHY PPI status interface */65 66#define PHY_STOP_WAIT_TIME 0x3067 68/*69 * regs relevant enum70 */71enum dpi_color_coding {72 DSI_24BITS_1 = 5,73};74 75enum dsi_video_mode_type {76 DSI_NON_BURST_SYNC_PULSES = 0,77 DSI_NON_BURST_SYNC_EVENTS,78 DSI_BURST_SYNC_PULSES_1,79 DSI_BURST_SYNC_PULSES_280};81 82enum dsi_work_mode {83 DSI_VIDEO_MODE = 0,84 DSI_COMMAND_MODE85};86 87/*88 * Register Write/Read Helper functions89 */90static inline void dw_update_bits(void __iomem *addr, u32 bit_start,91 u32 mask, u32 val)92{93 u32 tmp, orig;94 95 orig = readl(addr);96 tmp = orig & ~(mask << bit_start);97 tmp |= (val & mask) << bit_start;98 writel(tmp, addr);99}100 101#endif /* __DW_DRM_DSI_H__ */102