227 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2016 Linaro Limited.4 * Copyright (c) 2014-2016 HiSilicon Limited.5 */6 7#ifndef __KIRIN_ADE_REG_H__8#define __KIRIN_ADE_REG_H__9 10/*11 * ADE Registers12 */13#define MASK(x) (BIT_ULL(x) - 1)14 15#define ADE_CTRL 0x000416#define FRM_END_START_OFST 017#define FRM_END_START_MASK MASK(2)18#define AUTO_CLK_GATE_EN_OFST 019#define AUTO_CLK_GATE_EN BIT(0)20#define ADE_DISP_SRC_CFG 0x001821#define ADE_CTRL1 0x008C22#define ADE_EN 0x010023#define ADE_DISABLE 024#define ADE_ENABLE 125/* reset and reload regs */26#define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)27#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)28#define RDMA_OFST 029#define CLIP_OFST 1530#define SCL_OFST 2131#define CTRAN_OFST 2432#define OVLY_OFST 37 /* 32+5 */33/* channel regs */34#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80)35#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80)36#define RD_CH_SIZE(x) (0x100C + (x) * 0x80)37#define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80)38#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80)39#define RD_CH_EN(x) (0x1020 + (x) * 0x80)40/* overlay regs */41#define ADE_OVLY1_TRANS_CFG 0x002C42#define ADE_OVLY_CTL 0x009843#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4)44#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4)45#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4)46#define ADE_OVLY_OUTPUT_SIZE(x) (0x2070 + (x) * 8)47#define OUTPUT_XSIZE_OFST 1648#define ADE_OVLYX_CTL(x) (0x209C + (x) * 4)49#define CH_OVLY_SEL_OFST(x) ((x) * 4)50#define CH_OVLY_SEL_MASK MASK(2)51#define CH_OVLY_SEL_VAL(x) ((x) + 1)52#define CH_ALP_MODE_OFST 053#define CH_ALP_SEL_OFST 254#define CH_UNDER_ALP_SEL_OFST 455#define CH_EN_OFST 656#define CH_ALP_GBL_OFST 1557#define CH_SEL_OFST 2858/* ctran regs */59#define ADE_CTRAN_DIS(x) (0x5004 + (x) * 0x100)60#define CTRAN_BYPASS_ON 161#define CTRAN_BYPASS_OFF 062#define ADE_CTRAN_IMAGE_SIZE(x) (0x503C + (x) * 0x100)63/* clip regs */64#define ADE_CLIP_DISABLE(x) (0x6800 + (x) * 0x100)65#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100)66#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100)67 68/*69 * LDI Registers70 */71#define LDI_HRZ_CTRL0 0x740072#define HBP_OFST 2073#define LDI_HRZ_CTRL1 0x740474#define LDI_VRT_CTRL0 0x740875#define VBP_OFST 2076#define LDI_VRT_CTRL1 0x740C77#define LDI_PLR_CTRL 0x741078#define FLAG_NVSYNC BIT(0)79#define FLAG_NHSYNC BIT(1)80#define FLAG_NPIXCLK BIT(2)81#define FLAG_NDE BIT(3)82#define LDI_DSP_SIZE 0x741483#define VSIZE_OFST 2084#define LDI_INT_EN 0x741C85#define FRAME_END_INT_EN_OFST 186#define LDI_CTRL 0x742087#define BPP_OFST 388#define DATA_GATE_EN BIT(2)89#define LDI_EN BIT(0)90#define LDI_MSK_INT 0x742891#define LDI_INT_CLR 0x742C92#define LDI_WORK_MODE 0x743093#define LDI_HDMI_DSI_GT 0x743494 95/*96 * ADE media bus service regs97 */98#define ADE0_QOSGENERATOR_MODE 0x010C99#define QOSGENERATOR_MODE_MASK MASK(2)100#define ADE0_QOSGENERATOR_EXTCONTROL 0x0118101#define SOCKET_QOS_EN BIT(0)102#define ADE1_QOSGENERATOR_MODE 0x020C103#define ADE1_QOSGENERATOR_EXTCONTROL 0x0218104 105/*106 * ADE regs relevant enums107 */108enum frame_end_start {109 /* regs take effect in every vsync */110 REG_EFFECTIVE_IN_VSYNC = 0,111 /* regs take effect in fist ade en and every frame end */112 REG_EFFECTIVE_IN_ADEEN_FRMEND,113 /* regs take effect in ade en immediately */114 REG_EFFECTIVE_IN_ADEEN,115 /* regs take effect in first vsync and every frame end */116 REG_EFFECTIVE_IN_VSYNC_FRMEND117};118 119enum ade_fb_format {120 ADE_RGB_565 = 0,121 ADE_BGR_565,122 ADE_XRGB_8888,123 ADE_XBGR_8888,124 ADE_ARGB_8888,125 ADE_ABGR_8888,126 ADE_RGBA_8888,127 ADE_BGRA_8888,128 ADE_RGB_888,129 ADE_BGR_888 = 9,130 ADE_FORMAT_UNSUPPORT = 800131};132 133enum ade_channel {134 ADE_CH1 = 0, /* channel 1 for primary plane */135 ADE_CH_NUM136};137 138enum ade_scale {139 ADE_SCL1 = 0,140 ADE_SCL2,141 ADE_SCL3,142 ADE_SCL_NUM143};144 145enum ade_ctran {146 ADE_CTRAN1 = 0,147 ADE_CTRAN2,148 ADE_CTRAN3,149 ADE_CTRAN4,150 ADE_CTRAN5,151 ADE_CTRAN6,152 ADE_CTRAN_NUM153};154 155enum ade_overlay {156 ADE_OVLY1 = 0,157 ADE_OVLY2,158 ADE_OVLY3,159 ADE_OVLY_NUM160};161 162enum ade_alpha_mode {163 ADE_ALP_GLOBAL = 0,164 ADE_ALP_PIXEL,165 ADE_ALP_PIXEL_AND_GLB166};167 168enum ade_alpha_blending_mode {169 ADE_ALP_MUL_COEFF_0 = 0, /* alpha */170 ADE_ALP_MUL_COEFF_1, /* 1-alpha */171 ADE_ALP_MUL_COEFF_2, /* 0 */172 ADE_ALP_MUL_COEFF_3 /* 1 */173};174 175/*176 * LDI regs relevant enums177 */178enum dsi_pclk_en {179 DSI_PCLK_ON = 0,180 DSI_PCLK_OFF181};182 183enum ldi_output_format {184 LDI_OUT_RGB_565 = 0,185 LDI_OUT_RGB_666,186 LDI_OUT_RGB_888187};188 189enum ldi_work_mode {190 TEST_MODE = 0,191 NORMAL_MODE192};193 194enum ldi_input_source {195 DISP_SRC_NONE = 0,196 DISP_SRC_OVLY2,197 DISP_SRC_DISP,198 DISP_SRC_ROT,199 DISP_SRC_SCL2200};201 202/*203 * ADE media bus service relevant enums204 */205enum qos_generator_mode {206 FIXED_MODE = 0,207 LIMITER_MODE,208 BYPASS_MODE,209 REGULATOR_MODE210};211 212/*213 * Register Write/Read Helper functions214 */215static inline void ade_update_bits(void __iomem *addr, u32 bit_start,216 u32 mask, u32 val)217{218 u32 tmp, orig;219 220 orig = readl(addr);221 tmp = orig & ~(mask << bit_start);222 tmp |= (val & mask) << bit_start;223 writel(tmp, addr);224}225 226#endif227