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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2020 Intel Corporation4 *5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).6 */7 8#include <linux/string_helpers.h>9 10#include "g4x_dp.h"11#include "i915_reg.h"12#include "intel_audio.h"13#include "intel_backlight.h"14#include "intel_connector.h"15#include "intel_crtc.h"16#include "intel_de.h"17#include "intel_display_power.h"18#include "intel_display_types.h"19#include "intel_dp.h"20#include "intel_dp_aux.h"21#include "intel_dp_link_training.h"22#include "intel_dpio_phy.h"23#include "intel_encoder.h"24#include "intel_fifo_underrun.h"25#include "intel_hdmi.h"26#include "intel_hotplug.h"27#include "intel_pch_display.h"28#include "intel_pps.h"29#include "vlv_sideband.h"30 31static const struct dpll g4x_dpll[] = {32 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },33 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },34};35 36static const struct dpll pch_dpll[] = {37 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },38 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },39};40 41static const struct dpll vlv_dpll[] = {42 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },43 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },44};45 46static const struct dpll chv_dpll[] = {47 /* m2 is .22 binary fixed point */48 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },49 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },50};51 52const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)53{54 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];55}56 57void g4x_dp_set_clock(struct intel_encoder *encoder,58 struct intel_crtc_state *pipe_config)59{60 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);61 const struct dpll *divisor = NULL;62 int i, count = 0;63 64 if (IS_G4X(dev_priv)) {65 divisor = g4x_dpll;66 count = ARRAY_SIZE(g4x_dpll);67 } else if (HAS_PCH_SPLIT(dev_priv)) {68 divisor = pch_dpll;69 count = ARRAY_SIZE(pch_dpll);70 } else if (IS_CHERRYVIEW(dev_priv)) {71 divisor = chv_dpll;72 count = ARRAY_SIZE(chv_dpll);73 } else if (IS_VALLEYVIEW(dev_priv)) {74 divisor = vlv_dpll;75 count = ARRAY_SIZE(vlv_dpll);76 }77 78 if (divisor && count) {79 for (i = 0; i < count; i++) {80 if (pipe_config->port_clock == divisor[i].dot) {81 pipe_config->dpll = divisor[i];82 pipe_config->clock_set = true;83 break;84 }85 }86 }87}88 89static void intel_dp_prepare(struct intel_encoder *encoder,90 const struct intel_crtc_state *pipe_config)91{92 struct intel_display *display = to_intel_display(encoder);93 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);94 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);95 enum port port = encoder->port;96 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);97 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;98 99 intel_dp_set_link_params(intel_dp,100 pipe_config->port_clock,101 pipe_config->lane_count);102 103 /*104 * There are four kinds of DP registers:105 * IBX PCH106 * SNB CPU107 * IVB CPU108 * CPT PCH109 *110 * IBX PCH and CPU are the same for almost everything,111 * except that the CPU DP PLL is configured in this112 * register113 *114 * CPT PCH is quite different, having many bits moved115 * to the TRANS_DP_CTL register instead. That116 * configuration happens (oddly) in ilk_pch_enable117 */118 119 /* Preserve the BIOS-computed detected bit. This is120 * supposed to be read-only.121 */122 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;123 124 /* Handle DP bits in common between all three register formats */125 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;126 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);127 128 /* Split out the IBX/CPU vs CPT settings */129 130 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {131 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)132 intel_dp->DP |= DP_SYNC_HS_HIGH;133 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)134 intel_dp->DP |= DP_SYNC_VS_HIGH;135 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;136 137 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))138 intel_dp->DP |= DP_ENHANCED_FRAMING;139 140 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);141 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {142 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;143 144 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),145 TRANS_DP_ENH_FRAMING,146 pipe_config->enhanced_framing ?147 TRANS_DP_ENH_FRAMING : 0);148 } else {149 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)150 intel_dp->DP |= DP_COLOR_RANGE_16_235;151 152 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)153 intel_dp->DP |= DP_SYNC_HS_HIGH;154 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)155 intel_dp->DP |= DP_SYNC_VS_HIGH;156 intel_dp->DP |= DP_LINK_TRAIN_OFF;157 158 if (pipe_config->enhanced_framing)159 intel_dp->DP |= DP_ENHANCED_FRAMING;160 161 if (IS_CHERRYVIEW(dev_priv))162 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);163 else164 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);165 }166}167 168static void assert_dp_port(struct intel_dp *intel_dp, bool state)169{170 struct intel_display *display = to_intel_display(intel_dp);171 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);172 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);173 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;174 175 I915_STATE_WARN(dev_priv, cur_state != state,176 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",177 dig_port->base.base.base.id, dig_port->base.base.name,178 str_on_off(state), str_on_off(cur_state));179}180#define assert_dp_port_disabled(d) assert_dp_port((d), false)181 182static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)183{184 struct intel_display *display = &dev_priv->display;185 bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;186 187 I915_STATE_WARN(dev_priv, cur_state != state,188 "eDP PLL state assertion failure (expected %s, current %s)\n",189 str_on_off(state), str_on_off(cur_state));190}191#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)192#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)193 194static void ilk_edp_pll_on(struct intel_dp *intel_dp,195 const struct intel_crtc_state *pipe_config)196{197 struct intel_display *display = to_intel_display(intel_dp);198 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);200 201 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);202 assert_dp_port_disabled(intel_dp);203 assert_edp_pll_disabled(dev_priv);204 205 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",206 pipe_config->port_clock);207 208 intel_dp->DP &= ~DP_PLL_FREQ_MASK;209 210 if (pipe_config->port_clock == 162000)211 intel_dp->DP |= DP_PLL_FREQ_162MHZ;212 else213 intel_dp->DP |= DP_PLL_FREQ_270MHZ;214 215 intel_de_write(display, DP_A, intel_dp->DP);216 intel_de_posting_read(display, DP_A);217 udelay(500);218 219 /*220 * [DevILK] Work around required when enabling DP PLL221 * while a pipe is enabled going to FDI:222 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI223 * 2. Program DP PLL enable224 */225 if (IS_IRONLAKE(dev_priv))226 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);227 228 intel_dp->DP |= DP_PLL_ENABLE;229 230 intel_de_write(display, DP_A, intel_dp->DP);231 intel_de_posting_read(display, DP_A);232 udelay(200);233}234 235static void ilk_edp_pll_off(struct intel_dp *intel_dp,236 const struct intel_crtc_state *old_crtc_state)237{238 struct intel_display *display = to_intel_display(intel_dp);239 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);240 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);241 242 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);243 assert_dp_port_disabled(intel_dp);244 assert_edp_pll_enabled(dev_priv);245 246 drm_dbg_kms(display->drm, "disabling eDP PLL\n");247 248 intel_dp->DP &= ~DP_PLL_ENABLE;249 250 intel_de_write(display, DP_A, intel_dp->DP);251 intel_de_posting_read(display, DP_A);252 udelay(200);253}254 255static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,256 enum port port, enum pipe *pipe)257{258 struct intel_display *display = &dev_priv->display;259 enum pipe p;260 261 for_each_pipe(display, p) {262 u32 val = intel_de_read(display, TRANS_DP_CTL(p));263 264 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {265 *pipe = p;266 return true;267 }268 }269 270 drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",271 port_name(port));272 273 /* must initialize pipe to something for the asserts */274 *pipe = PIPE_A;275 276 return false;277}278 279bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,280 i915_reg_t dp_reg, enum port port,281 enum pipe *pipe)282{283 struct intel_display *display = &dev_priv->display;284 bool ret;285 u32 val;286 287 val = intel_de_read(display, dp_reg);288 289 ret = val & DP_PORT_EN;290 291 /* asserts want to know the pipe even if the port is disabled */292 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)293 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;294 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)295 ret &= cpt_dp_port_selected(dev_priv, port, pipe);296 else if (IS_CHERRYVIEW(dev_priv))297 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;298 else299 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;300 301 return ret;302}303 304static bool intel_dp_get_hw_state(struct intel_encoder *encoder,305 enum pipe *pipe)306{307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);308 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);309 intel_wakeref_t wakeref;310 bool ret;311 312 wakeref = intel_display_power_get_if_enabled(dev_priv,313 encoder->power_domain);314 if (!wakeref)315 return false;316 317 ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,318 encoder->port, pipe);319 320 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);321 322 return ret;323}324 325static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)326{327 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);328 329 if (crtc_state->has_pch_encoder) {330 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);331 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);332 } else {333 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,334 &crtc_state->dp_m_n);335 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,336 &crtc_state->dp_m2_n2);337 }338}339 340static void intel_dp_get_config(struct intel_encoder *encoder,341 struct intel_crtc_state *pipe_config)342{343 struct intel_display *display = to_intel_display(encoder);344 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);345 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);346 u32 tmp, flags = 0;347 enum port port = encoder->port;348 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);349 350 if (encoder->type == INTEL_OUTPUT_EDP)351 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);352 else353 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);354 355 tmp = intel_de_read(display, intel_dp->output_reg);356 357 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;358 359 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {360 u32 trans_dp = intel_de_read(display,361 TRANS_DP_CTL(crtc->pipe));362 363 if (trans_dp & TRANS_DP_ENH_FRAMING)364 pipe_config->enhanced_framing = true;365 366 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)367 flags |= DRM_MODE_FLAG_PHSYNC;368 else369 flags |= DRM_MODE_FLAG_NHSYNC;370 371 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)372 flags |= DRM_MODE_FLAG_PVSYNC;373 else374 flags |= DRM_MODE_FLAG_NVSYNC;375 } else {376 if (tmp & DP_ENHANCED_FRAMING)377 pipe_config->enhanced_framing = true;378 379 if (tmp & DP_SYNC_HS_HIGH)380 flags |= DRM_MODE_FLAG_PHSYNC;381 else382 flags |= DRM_MODE_FLAG_NHSYNC;383 384 if (tmp & DP_SYNC_VS_HIGH)385 flags |= DRM_MODE_FLAG_PVSYNC;386 else387 flags |= DRM_MODE_FLAG_NVSYNC;388 }389 390 pipe_config->hw.adjusted_mode.flags |= flags;391 392 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)393 pipe_config->limited_color_range = true;394 395 pipe_config->lane_count =396 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;397 398 g4x_dp_get_m_n(pipe_config);399 400 if (port == PORT_A) {401 if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)402 pipe_config->port_clock = 162000;403 else404 pipe_config->port_clock = 270000;405 }406 407 pipe_config->hw.adjusted_mode.crtc_clock =408 intel_dotclock_calculate(pipe_config->port_clock,409 &pipe_config->dp_m_n);410 411 if (intel_dp_is_edp(intel_dp))412 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);413 414 intel_audio_codec_get_config(encoder, pipe_config);415}416 417static void418intel_dp_link_down(struct intel_encoder *encoder,419 const struct intel_crtc_state *old_crtc_state)420{421 struct intel_display *display = to_intel_display(encoder);422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);423 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);424 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);425 enum port port = encoder->port;426 427 if (drm_WARN_ON(display->drm,428 (intel_de_read(display, intel_dp->output_reg) &429 DP_PORT_EN) == 0))430 return;431 432 drm_dbg_kms(display->drm, "\n");433 434 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||435 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {436 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;437 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;438 } else {439 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;440 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;441 }442 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);443 intel_de_posting_read(display, intel_dp->output_reg);444 445 intel_dp->DP &= ~DP_PORT_EN;446 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);447 intel_de_posting_read(display, intel_dp->output_reg);448 449 /*450 * HW workaround for IBX, we need to move the port451 * to transcoder A after disabling it to allow the452 * matching HDMI port to be enabled on transcoder A.453 */454 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {455 /*456 * We get CPU/PCH FIFO underruns on the other pipe when457 * doing the workaround. Sweep them under the rug.458 */459 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);460 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);461 462 /* always enable with pattern 1 (as per spec) */463 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);464 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |465 DP_LINK_TRAIN_PAT_1;466 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);467 intel_de_posting_read(display, intel_dp->output_reg);468 469 intel_dp->DP &= ~DP_PORT_EN;470 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);471 intel_de_posting_read(display, intel_dp->output_reg);472 473 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);474 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);475 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);476 }477 478 msleep(intel_dp->pps.panel_power_down_delay);479 480 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {481 intel_wakeref_t wakeref;482 483 with_intel_pps_lock(intel_dp, wakeref)484 intel_dp->pps.active_pipe = INVALID_PIPE;485 }486}487 488static void g4x_dp_audio_enable(struct intel_encoder *encoder,489 const struct intel_crtc_state *crtc_state,490 const struct drm_connector_state *conn_state)491{492 struct intel_display *display = to_intel_display(encoder);493 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);494 495 if (!crtc_state->has_audio)496 return;497 498 /* Enable audio presence detect */499 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;500 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);501 502 intel_audio_codec_enable(encoder, crtc_state, conn_state);503}504 505static void g4x_dp_audio_disable(struct intel_encoder *encoder,506 const struct intel_crtc_state *old_crtc_state,507 const struct drm_connector_state *old_conn_state)508{509 struct intel_display *display = to_intel_display(encoder);510 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);511 512 if (!old_crtc_state->has_audio)513 return;514 515 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);516 517 /* Disable audio presence detect */518 intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;519 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);520}521 522static void intel_disable_dp(struct intel_atomic_state *state,523 struct intel_encoder *encoder,524 const struct intel_crtc_state *old_crtc_state,525 const struct drm_connector_state *old_conn_state)526{527 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);528 529 intel_dp->link_trained = false;530 531 /*532 * Make sure the panel is off before trying to change the mode.533 * But also ensure that we have vdd while we switch off the panel.534 */535 intel_pps_vdd_on(intel_dp);536 intel_edp_backlight_off(old_conn_state);537 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);538 intel_pps_off(intel_dp);539}540 541static void g4x_disable_dp(struct intel_atomic_state *state,542 struct intel_encoder *encoder,543 const struct intel_crtc_state *old_crtc_state,544 const struct drm_connector_state *old_conn_state)545{546 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);547}548 549static void vlv_disable_dp(struct intel_atomic_state *state,550 struct intel_encoder *encoder,551 const struct intel_crtc_state *old_crtc_state,552 const struct drm_connector_state *old_conn_state)553{554 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);555}556 557static void g4x_post_disable_dp(struct intel_atomic_state *state,558 struct intel_encoder *encoder,559 const struct intel_crtc_state *old_crtc_state,560 const struct drm_connector_state *old_conn_state)561{562 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);563 enum port port = encoder->port;564 565 /*566 * Bspec does not list a specific disable sequence for g4x DP.567 * Follow the ilk+ sequence (disable pipe before the port) for568 * g4x DP as it does not suffer from underruns like the normal569 * g4x modeset sequence (disable pipe after the port).570 */571 intel_dp_link_down(encoder, old_crtc_state);572 573 /* Only ilk+ has port A */574 if (port == PORT_A)575 ilk_edp_pll_off(intel_dp, old_crtc_state);576}577 578static void vlv_post_disable_dp(struct intel_atomic_state *state,579 struct intel_encoder *encoder,580 const struct intel_crtc_state *old_crtc_state,581 const struct drm_connector_state *old_conn_state)582{583 intel_dp_link_down(encoder, old_crtc_state);584}585 586static void chv_post_disable_dp(struct intel_atomic_state *state,587 struct intel_encoder *encoder,588 const struct intel_crtc_state *old_crtc_state,589 const struct drm_connector_state *old_conn_state)590{591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);592 593 intel_dp_link_down(encoder, old_crtc_state);594 595 vlv_dpio_get(dev_priv);596 597 /* Assert data lane reset */598 chv_data_lane_soft_reset(encoder, old_crtc_state, true);599 600 vlv_dpio_put(dev_priv);601}602 603static void604cpt_set_link_train(struct intel_dp *intel_dp,605 const struct intel_crtc_state *crtc_state,606 u8 dp_train_pat)607{608 struct intel_display *display = to_intel_display(intel_dp);609 610 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;611 612 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {613 case DP_TRAINING_PATTERN_DISABLE:614 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;615 break;616 case DP_TRAINING_PATTERN_1:617 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;618 break;619 case DP_TRAINING_PATTERN_2:620 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;621 break;622 default:623 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));624 return;625 }626 627 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);628 intel_de_posting_read(display, intel_dp->output_reg);629}630 631static void632g4x_set_link_train(struct intel_dp *intel_dp,633 const struct intel_crtc_state *crtc_state,634 u8 dp_train_pat)635{636 struct intel_display *display = to_intel_display(intel_dp);637 638 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;639 640 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {641 case DP_TRAINING_PATTERN_DISABLE:642 intel_dp->DP |= DP_LINK_TRAIN_OFF;643 break;644 case DP_TRAINING_PATTERN_1:645 intel_dp->DP |= DP_LINK_TRAIN_PAT_1;646 break;647 case DP_TRAINING_PATTERN_2:648 intel_dp->DP |= DP_LINK_TRAIN_PAT_2;649 break;650 default:651 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));652 return;653 }654 655 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);656 intel_de_posting_read(display, intel_dp->output_reg);657}658 659static void intel_dp_enable_port(struct intel_dp *intel_dp,660 const struct intel_crtc_state *crtc_state)661{662 struct intel_display *display = to_intel_display(intel_dp);663 664 /* enable with pattern 1 (as per spec) */665 666 intel_dp_program_link_training_pattern(intel_dp, crtc_state,667 DP_PHY_DPRX, DP_TRAINING_PATTERN_1);668 669 /*670 * Magic for VLV/CHV. We _must_ first set up the register671 * without actually enabling the port, and then do another672 * write to enable the port. Otherwise link training will673 * fail when the power sequencer is freshly used for this port.674 */675 intel_dp->DP |= DP_PORT_EN;676 677 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);678 intel_de_posting_read(display, intel_dp->output_reg);679}680 681static void intel_enable_dp(struct intel_atomic_state *state,682 struct intel_encoder *encoder,683 const struct intel_crtc_state *pipe_config,684 const struct drm_connector_state *conn_state)685{686 struct intel_display *display = to_intel_display(state);687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);688 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);689 u32 dp_reg = intel_de_read(display, intel_dp->output_reg);690 intel_wakeref_t wakeref;691 692 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))693 return;694 695 with_intel_pps_lock(intel_dp, wakeref) {696 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))697 vlv_pps_init(encoder, pipe_config);698 699 intel_dp_enable_port(intel_dp, pipe_config);700 701 intel_pps_vdd_on_unlocked(intel_dp);702 intel_pps_on_unlocked(intel_dp);703 intel_pps_vdd_off_unlocked(intel_dp, true);704 }705 706 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {707 unsigned int lane_mask = 0x0;708 709 if (IS_CHERRYVIEW(dev_priv))710 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);711 712 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),713 lane_mask);714 }715 716 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);717 intel_dp_configure_protocol_converter(intel_dp, pipe_config);718 intel_dp_check_frl_training(intel_dp);719 intel_dp_pcon_dsc_configure(intel_dp, pipe_config);720 intel_dp_start_link_train(state, intel_dp, pipe_config);721 intel_dp_stop_link_train(intel_dp, pipe_config);722}723 724static void g4x_enable_dp(struct intel_atomic_state *state,725 struct intel_encoder *encoder,726 const struct intel_crtc_state *pipe_config,727 const struct drm_connector_state *conn_state)728{729 intel_enable_dp(state, encoder, pipe_config, conn_state);730 intel_edp_backlight_on(pipe_config, conn_state);731}732 733static void vlv_enable_dp(struct intel_atomic_state *state,734 struct intel_encoder *encoder,735 const struct intel_crtc_state *pipe_config,736 const struct drm_connector_state *conn_state)737{738 intel_edp_backlight_on(pipe_config, conn_state);739}740 741static void g4x_pre_enable_dp(struct intel_atomic_state *state,742 struct intel_encoder *encoder,743 const struct intel_crtc_state *pipe_config,744 const struct drm_connector_state *conn_state)745{746 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);747 enum port port = encoder->port;748 749 intel_dp_prepare(encoder, pipe_config);750 751 /* Only ilk+ has port A */752 if (port == PORT_A)753 ilk_edp_pll_on(intel_dp, pipe_config);754}755 756static void vlv_pre_enable_dp(struct intel_atomic_state *state,757 struct intel_encoder *encoder,758 const struct intel_crtc_state *pipe_config,759 const struct drm_connector_state *conn_state)760{761 vlv_phy_pre_encoder_enable(encoder, pipe_config);762 763 intel_enable_dp(state, encoder, pipe_config, conn_state);764}765 766static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,767 struct intel_encoder *encoder,768 const struct intel_crtc_state *pipe_config,769 const struct drm_connector_state *conn_state)770{771 intel_dp_prepare(encoder, pipe_config);772 773 vlv_phy_pre_pll_enable(encoder, pipe_config);774}775 776static void chv_pre_enable_dp(struct intel_atomic_state *state,777 struct intel_encoder *encoder,778 const struct intel_crtc_state *pipe_config,779 const struct drm_connector_state *conn_state)780{781 chv_phy_pre_encoder_enable(encoder, pipe_config);782 783 intel_enable_dp(state, encoder, pipe_config, conn_state);784 785 /* Second common lane will stay alive on its own now */786 chv_phy_release_cl2_override(encoder);787}788 789static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,790 struct intel_encoder *encoder,791 const struct intel_crtc_state *pipe_config,792 const struct drm_connector_state *conn_state)793{794 intel_dp_prepare(encoder, pipe_config);795 796 chv_phy_pre_pll_enable(encoder, pipe_config);797}798 799static void chv_dp_post_pll_disable(struct intel_atomic_state *state,800 struct intel_encoder *encoder,801 const struct intel_crtc_state *old_crtc_state,802 const struct drm_connector_state *old_conn_state)803{804 chv_phy_post_pll_disable(encoder, old_crtc_state);805}806 807static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,808 const struct intel_crtc_state *crtc_state)809{810 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;811}812 813static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,814 const struct intel_crtc_state *crtc_state)815{816 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;817}818 819static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)820{821 return DP_TRAIN_PRE_EMPH_LEVEL_2;822}823 824static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)825{826 return DP_TRAIN_PRE_EMPH_LEVEL_3;827}828 829static void vlv_set_signal_levels(struct intel_encoder *encoder,830 const struct intel_crtc_state *crtc_state)831{832 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);833 unsigned long demph_reg_value, preemph_reg_value,834 uniqtranscale_reg_value;835 u8 train_set = intel_dp->train_set[0];836 837 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {838 case DP_TRAIN_PRE_EMPH_LEVEL_0:839 preemph_reg_value = 0x0004000;840 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:842 demph_reg_value = 0x2B405555;843 uniqtranscale_reg_value = 0x552AB83A;844 break;845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:846 demph_reg_value = 0x2B404040;847 uniqtranscale_reg_value = 0x5548B83A;848 break;849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:850 demph_reg_value = 0x2B245555;851 uniqtranscale_reg_value = 0x5560B83A;852 break;853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:854 demph_reg_value = 0x2B405555;855 uniqtranscale_reg_value = 0x5598DA3A;856 break;857 default:858 return;859 }860 break;861 case DP_TRAIN_PRE_EMPH_LEVEL_1:862 preemph_reg_value = 0x0002000;863 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:865 demph_reg_value = 0x2B404040;866 uniqtranscale_reg_value = 0x5552B83A;867 break;868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:869 demph_reg_value = 0x2B404848;870 uniqtranscale_reg_value = 0x5580B83A;871 break;872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:873 demph_reg_value = 0x2B404040;874 uniqtranscale_reg_value = 0x55ADDA3A;875 break;876 default:877 return;878 }879 break;880 case DP_TRAIN_PRE_EMPH_LEVEL_2:881 preemph_reg_value = 0x0000000;882 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:884 demph_reg_value = 0x2B305555;885 uniqtranscale_reg_value = 0x5570B83A;886 break;887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:888 demph_reg_value = 0x2B2B4040;889 uniqtranscale_reg_value = 0x55ADDA3A;890 break;891 default:892 return;893 }894 break;895 case DP_TRAIN_PRE_EMPH_LEVEL_3:896 preemph_reg_value = 0x0006000;897 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {898 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:899 demph_reg_value = 0x1B405555;900 uniqtranscale_reg_value = 0x55ADDA3A;901 break;902 default:903 return;904 }905 break;906 default:907 return;908 }909 910 vlv_set_phy_signal_level(encoder, crtc_state,911 demph_reg_value, preemph_reg_value,912 uniqtranscale_reg_value, 0);913}914 915static void chv_set_signal_levels(struct intel_encoder *encoder,916 const struct intel_crtc_state *crtc_state)917{918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);919 u32 deemph_reg_value, margin_reg_value;920 bool uniq_trans_scale = false;921 u8 train_set = intel_dp->train_set[0];922 923 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {924 case DP_TRAIN_PRE_EMPH_LEVEL_0:925 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:927 deemph_reg_value = 128;928 margin_reg_value = 52;929 break;930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:931 deemph_reg_value = 128;932 margin_reg_value = 77;933 break;934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:935 deemph_reg_value = 128;936 margin_reg_value = 102;937 break;938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:939 deemph_reg_value = 128;940 margin_reg_value = 154;941 uniq_trans_scale = true;942 break;943 default:944 return;945 }946 break;947 case DP_TRAIN_PRE_EMPH_LEVEL_1:948 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:950 deemph_reg_value = 85;951 margin_reg_value = 78;952 break;953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:954 deemph_reg_value = 85;955 margin_reg_value = 116;956 break;957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:958 deemph_reg_value = 85;959 margin_reg_value = 154;960 break;961 default:962 return;963 }964 break;965 case DP_TRAIN_PRE_EMPH_LEVEL_2:966 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:968 deemph_reg_value = 64;969 margin_reg_value = 104;970 break;971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:972 deemph_reg_value = 64;973 margin_reg_value = 154;974 break;975 default:976 return;977 }978 break;979 case DP_TRAIN_PRE_EMPH_LEVEL_3:980 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {981 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:982 deemph_reg_value = 43;983 margin_reg_value = 154;984 break;985 default:986 return;987 }988 break;989 default:990 return;991 }992 993 chv_set_phy_signal_level(encoder, crtc_state,994 deemph_reg_value, margin_reg_value,995 uniq_trans_scale);996}997 998static u32 g4x_signal_levels(u8 train_set)999{1000 u32 signal_levels = 0;1001 1002 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {1003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:1004 default:1005 signal_levels |= DP_VOLTAGE_0_4;1006 break;1007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:1008 signal_levels |= DP_VOLTAGE_0_6;1009 break;1010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:1011 signal_levels |= DP_VOLTAGE_0_8;1012 break;1013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:1014 signal_levels |= DP_VOLTAGE_1_2;1015 break;1016 }1017 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {1018 case DP_TRAIN_PRE_EMPH_LEVEL_0:1019 default:1020 signal_levels |= DP_PRE_EMPHASIS_0;1021 break;1022 case DP_TRAIN_PRE_EMPH_LEVEL_1:1023 signal_levels |= DP_PRE_EMPHASIS_3_5;1024 break;1025 case DP_TRAIN_PRE_EMPH_LEVEL_2:1026 signal_levels |= DP_PRE_EMPHASIS_6;1027 break;1028 case DP_TRAIN_PRE_EMPH_LEVEL_3:1029 signal_levels |= DP_PRE_EMPHASIS_9_5;1030 break;1031 }1032 return signal_levels;1033}1034 1035static void1036g4x_set_signal_levels(struct intel_encoder *encoder,1037 const struct intel_crtc_state *crtc_state)1038{1039 struct intel_display *display = to_intel_display(encoder);1040 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);1041 u8 train_set = intel_dp->train_set[0];1042 u32 signal_levels;1043 1044 signal_levels = g4x_signal_levels(train_set);1045 1046 drm_dbg_kms(display->drm, "Using signal levels %08x\n",1047 signal_levels);1048 1049 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);1050 intel_dp->DP |= signal_levels;1051 1052 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);1053 intel_de_posting_read(display, intel_dp->output_reg);1054}1055 1056/* SNB CPU eDP voltage swing and pre-emphasis control */1057static u32 snb_cpu_edp_signal_levels(u8 train_set)1058{1059 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |1060 DP_TRAIN_PRE_EMPHASIS_MASK);1061 1062 switch (signal_levels) {1063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:1064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:1065 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;1066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:1067 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;1068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:1069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:1070 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;1071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:1072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:1073 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;1074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:1075 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:1076 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;1077 default:1078 MISSING_CASE(signal_levels);1079 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;1080 }1081}1082 1083static void1084snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,1085 const struct intel_crtc_state *crtc_state)1086{1087 struct intel_display *display = to_intel_display(encoder);1088 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);1089 u8 train_set = intel_dp->train_set[0];1090 u32 signal_levels;1091 1092 signal_levels = snb_cpu_edp_signal_levels(train_set);1093 1094 drm_dbg_kms(display->drm, "Using signal levels %08x\n",1095 signal_levels);1096 1097 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;1098 intel_dp->DP |= signal_levels;1099 1100 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);1101 intel_de_posting_read(display, intel_dp->output_reg);1102}1103 1104/* IVB CPU eDP voltage swing and pre-emphasis control */1105static u32 ivb_cpu_edp_signal_levels(u8 train_set)1106{1107 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |1108 DP_TRAIN_PRE_EMPHASIS_MASK);1109 1110 switch (signal_levels) {1111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:1112 return EDP_LINK_TRAIN_400MV_0DB_IVB;1113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:1114 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;1115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:1116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:1117 return EDP_LINK_TRAIN_400MV_6DB_IVB;1118 1119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:1120 return EDP_LINK_TRAIN_600MV_0DB_IVB;1121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:1122 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;1123 1124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:1125 return EDP_LINK_TRAIN_800MV_0DB_IVB;1126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:1127 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;1128 1129 default:1130 MISSING_CASE(signal_levels);1131 return EDP_LINK_TRAIN_500MV_0DB_IVB;1132 }1133}1134 1135static void1136ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,1137 const struct intel_crtc_state *crtc_state)1138{1139 struct intel_display *display = to_intel_display(encoder);1140 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);1141 u8 train_set = intel_dp->train_set[0];1142 u32 signal_levels;1143 1144 signal_levels = ivb_cpu_edp_signal_levels(train_set);1145 1146 drm_dbg_kms(display->drm, "Using signal levels %08x\n",1147 signal_levels);1148 1149 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;1150 intel_dp->DP |= signal_levels;1151 1152 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);1153 intel_de_posting_read(display, intel_dp->output_reg);1154}1155 1156/*1157 * If display is now connected check links status,1158 * there has been known issues of link loss triggering1159 * long pulse.1160 *1161 * Some sinks (eg. ASUS PB287Q) seem to perform some1162 * weird HPD ping pong during modesets. So we can apparently1163 * end up with HPD going low during a modeset, and then1164 * going back up soon after. And once that happens we must1165 * retrain the link to get a picture. That's in case no1166 * userspace component reacted to intermittent HPD dip.1167 */1168static enum intel_hotplug_state1169intel_dp_hotplug(struct intel_encoder *encoder,1170 struct intel_connector *connector)1171{1172 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);1173 enum intel_hotplug_state state;1174 1175 if (intel_dp->compliance.test_active &&1176 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {1177 intel_dp_phy_test(encoder);1178 /* just do the PHY test and nothing else */1179 return INTEL_HOTPLUG_UNCHANGED;1180 }1181 1182 state = intel_encoder_hotplug(encoder, connector);1183 1184 intel_dp_check_link_state(intel_dp);1185 1186 /*1187 * Keeping it consistent with intel_ddi_hotplug() and1188 * intel_hdmi_hotplug().1189 */1190 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)1191 state = INTEL_HOTPLUG_RETRY;1192 1193 return state;1194}1195 1196static bool ibx_digital_port_connected(struct intel_encoder *encoder)1197{1198 struct intel_display *display = to_intel_display(encoder);1199 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];1200 1201 return intel_de_read(display, SDEISR) & bit;1202}1203 1204static bool g4x_digital_port_connected(struct intel_encoder *encoder)1205{1206 struct intel_display *display = to_intel_display(encoder);1207 u32 bit;1208 1209 switch (encoder->hpd_pin) {1210 case HPD_PORT_B:1211 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;1212 break;1213 case HPD_PORT_C:1214 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;1215 break;1216 case HPD_PORT_D:1217 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;1218 break;1219 default:1220 MISSING_CASE(encoder->hpd_pin);1221 return false;1222 }1223 1224 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;1225}1226 1227static bool ilk_digital_port_connected(struct intel_encoder *encoder)1228{1229 struct intel_display *display = to_intel_display(encoder);1230 u32 bit = display->hotplug.hpd[encoder->hpd_pin];1231 1232 return intel_de_read(display, DEISR) & bit;1233}1234 1235static void g4x_dp_suspend_complete(struct intel_encoder *encoder)1236{1237 /*1238 * TODO: Move this to intel_dp_encoder_suspend(),1239 * once modeset locking around that is removed.1240 */1241 intel_encoder_link_check_flush_work(encoder);1242}1243 1244static void intel_dp_encoder_destroy(struct drm_encoder *encoder)1245{1246 intel_dp_encoder_flush_work(encoder);1247 1248 drm_encoder_cleanup(encoder);1249 kfree(enc_to_dig_port(to_intel_encoder(encoder)));1250}1251 1252enum pipe vlv_active_pipe(struct intel_dp *intel_dp)1253{1254 struct intel_display *display = to_intel_display(intel_dp);1255 struct drm_i915_private *dev_priv = to_i915(display->drm);1256 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;1257 enum pipe pipe;1258 1259 if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,1260 encoder->port, &pipe))1261 return pipe;1262 1263 return INVALID_PIPE;1264}1265 1266static void intel_dp_encoder_reset(struct drm_encoder *encoder)1267{1268 struct intel_display *display = to_intel_display(encoder->dev);1269 struct drm_i915_private *dev_priv = to_i915(encoder->dev);1270 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));1271 1272 intel_dp->DP = intel_de_read(display, intel_dp->output_reg);1273 1274 intel_dp->reset_link_params = true;1275 1276 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {1277 intel_wakeref_t wakeref;1278 1279 with_intel_pps_lock(intel_dp, wakeref)1280 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);1281 }1282 1283 intel_pps_encoder_reset(intel_dp);1284}1285 1286static const struct drm_encoder_funcs intel_dp_enc_funcs = {1287 .reset = intel_dp_encoder_reset,1288 .destroy = intel_dp_encoder_destroy,1289};1290 1291bool g4x_dp_init(struct drm_i915_private *dev_priv,1292 i915_reg_t output_reg, enum port port)1293{1294 struct intel_display *display = &dev_priv->display;1295 const struct intel_bios_encoder_data *devdata;1296 struct intel_digital_port *dig_port;1297 struct intel_encoder *intel_encoder;1298 struct drm_encoder *encoder;1299 struct intel_connector *intel_connector;1300 1301 if (!assert_port_valid(dev_priv, port))1302 return false;1303 1304 devdata = intel_bios_encoder_data_lookup(display, port);1305 1306 /* FIXME bail? */1307 if (!devdata)1308 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",1309 port_name(port));1310 1311 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);1312 if (!dig_port)1313 return false;1314 1315 dig_port->aux_ch = AUX_CH_NONE;1316 1317 intel_connector = intel_connector_alloc();1318 if (!intel_connector)1319 goto err_connector_alloc;1320 1321 intel_encoder = &dig_port->base;1322 encoder = &intel_encoder->base;1323 1324 intel_encoder->devdata = devdata;1325 1326 mutex_init(&dig_port->hdcp_mutex);1327 1328 if (drm_encoder_init(display->drm, &intel_encoder->base,1329 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,1330 "DP %c", port_name(port)))1331 goto err_encoder_init;1332 1333 intel_encoder_link_check_init(intel_encoder, intel_dp_link_check);1334 1335 intel_encoder->hotplug = intel_dp_hotplug;1336 intel_encoder->compute_config = intel_dp_compute_config;1337 intel_encoder->get_hw_state = intel_dp_get_hw_state;1338 intel_encoder->get_config = intel_dp_get_config;1339 intel_encoder->sync_state = intel_dp_sync_state;1340 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;1341 intel_encoder->update_pipe = intel_backlight_update;1342 intel_encoder->suspend = intel_dp_encoder_suspend;1343 intel_encoder->suspend_complete = g4x_dp_suspend_complete;1344 intel_encoder->shutdown = intel_dp_encoder_shutdown;1345 if (IS_CHERRYVIEW(dev_priv)) {1346 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;1347 intel_encoder->pre_enable = chv_pre_enable_dp;1348 intel_encoder->enable = vlv_enable_dp;1349 intel_encoder->disable = vlv_disable_dp;1350 intel_encoder->post_disable = chv_post_disable_dp;1351 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;1352 } else if (IS_VALLEYVIEW(dev_priv)) {1353 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;1354 intel_encoder->pre_enable = vlv_pre_enable_dp;1355 intel_encoder->enable = vlv_enable_dp;1356 intel_encoder->disable = vlv_disable_dp;1357 intel_encoder->post_disable = vlv_post_disable_dp;1358 } else {1359 intel_encoder->pre_enable = g4x_pre_enable_dp;1360 intel_encoder->enable = g4x_enable_dp;1361 intel_encoder->disable = g4x_disable_dp;1362 intel_encoder->post_disable = g4x_post_disable_dp;1363 }1364 intel_encoder->audio_enable = g4x_dp_audio_enable;1365 intel_encoder->audio_disable = g4x_dp_audio_disable;1366 1367 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||1368 (HAS_PCH_CPT(dev_priv) && port != PORT_A))1369 dig_port->dp.set_link_train = cpt_set_link_train;1370 else1371 dig_port->dp.set_link_train = g4x_set_link_train;1372 1373 if (IS_CHERRYVIEW(dev_priv))1374 intel_encoder->set_signal_levels = chv_set_signal_levels;1375 else if (IS_VALLEYVIEW(dev_priv))1376 intel_encoder->set_signal_levels = vlv_set_signal_levels;1377 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)1378 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;1379 else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)1380 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;1381 else1382 intel_encoder->set_signal_levels = g4x_set_signal_levels;1383 1384 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||1385 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {1386 dig_port->dp.preemph_max = intel_dp_preemph_max_3;1387 dig_port->dp.voltage_max = intel_dp_voltage_max_3;1388 } else {1389 dig_port->dp.preemph_max = intel_dp_preemph_max_2;1390 dig_port->dp.voltage_max = intel_dp_voltage_max_2;1391 }1392 1393 dig_port->dp.output_reg = output_reg;1394 dig_port->max_lanes = 4;1395 1396 intel_encoder->type = INTEL_OUTPUT_DP;1397 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);1398 if (IS_CHERRYVIEW(dev_priv)) {1399 if (port == PORT_D)1400 intel_encoder->pipe_mask = BIT(PIPE_C);1401 else1402 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);1403 } else {1404 intel_encoder->pipe_mask = ~0;1405 }1406 intel_encoder->cloneable = 0;1407 intel_encoder->port = port;1408 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);1409 1410 dig_port->hpd_pulse = intel_dp_hpd_pulse;1411 1412 if (HAS_GMCH(display)) {1413 dig_port->connected = g4x_digital_port_connected;1414 } else {1415 if (port == PORT_A)1416 dig_port->connected = ilk_digital_port_connected;1417 else1418 dig_port->connected = ibx_digital_port_connected;1419 }1420 1421 if (port != PORT_A)1422 intel_infoframe_init(dig_port);1423 1424 dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);1425 if (dig_port->aux_ch == AUX_CH_NONE)1426 goto err_init_connector;1427 1428 if (!intel_dp_init_connector(dig_port, intel_connector))1429 goto err_init_connector;1430 1431 return true;1432 1433err_init_connector:1434 drm_encoder_cleanup(encoder);1435err_encoder_init:1436 kfree(intel_connector);1437err_connector_alloc:1438 kfree(dig_port);1439 return false;1440}1441