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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2022 Intel Corporation4 */5 6#ifndef __ICL_DSI_REGS_H__7#define __ICL_DSI_REGS_H__8 9#include "intel_display_reg_defs.h"10 11/* Gen11 DSI */12#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \13 dsi0, dsi1)14#define _ICL_DSI_ESC_CLK_DIV0 0x6b09015#define _ICL_DSI_ESC_CLK_DIV1 0x6b89016#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \17 _ICL_DSI_ESC_CLK_DIV0, \18 _ICL_DSI_ESC_CLK_DIV1)19#define _ICL_DPHY_ESC_CLK_DIV0 0x16219020#define _ICL_DPHY_ESC_CLK_DIV1 0x6C19021#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \22 _ICL_DPHY_ESC_CLK_DIV0, \23 _ICL_DPHY_ESC_CLK_DIV1)24#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)25#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 1626#define ICL_ESC_CLK_DIV_MASK 0x1ff27#define ICL_ESC_CLK_DIV_SHIFT 028#define DSI_MAX_ESC_CLK 20000 /* in KHz */29 30#define _ADL_MIPIO_REG 0x18031#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))32#define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16)33#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)34#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)35 36#define _DSI_CMD_FRMCTL_0 0x6b03437#define _DSI_CMD_FRMCTL_1 0x6b83438#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \39 _DSI_CMD_FRMCTL_0,\40 _DSI_CMD_FRMCTL_1)41#define DSI_FRAME_UPDATE_REQUEST (1 << 31)42#define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29)43#define DSI_NULL_PACKET_ENABLE (1 << 28)44#define DSI_FRAME_IN_PROGRESS (1 << 0)45 46#define _DSI_INTR_MASK_REG_0 0x6b07047#define _DSI_INTR_MASK_REG_1 0x6b87048#define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \49 _DSI_INTR_MASK_REG_0,\50 _DSI_INTR_MASK_REG_1)51 52#define _DSI_INTR_IDENT_REG_0 0x6b07453#define _DSI_INTR_IDENT_REG_1 0x6b87454#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \55 _DSI_INTR_IDENT_REG_0,\56 _DSI_INTR_IDENT_REG_1)57#define DSI_TE_EVENT (1 << 31)58#define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30)59#define DSI_TX_DATA (1 << 29)60#define DSI_ULPS_ENTRY_DONE (1 << 28)61#define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27)62#define DSI_HOST_CHKSUM_ERROR (1 << 26)63#define DSI_HOST_MULTI_ECC_ERROR (1 << 25)64#define DSI_HOST_SINGL_ECC_ERROR (1 << 24)65#define DSI_HOST_CONTENTION_DETECTED (1 << 23)66#define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22)67#define DSI_HOST_TIMEOUT_ERROR (1 << 21)68#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20)69#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19)70#define DSI_FRAME_UPDATE_DONE (1 << 16)71#define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15)72#define DSI_INVALID_TX_LENGTH (1 << 13)73#define DSI_INVALID_VC (1 << 12)74#define DSI_INVALID_DATA_TYPE (1 << 11)75#define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10)76#define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9)77#define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8)78#define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7)79#define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6)80#define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5)81#define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4)82#define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3)83#define DSI_EOT_SYNC_ERROR (1 << 2)84#define DSI_SOT_SYNC_ERROR (1 << 1)85#define DSI_SOT_ERROR (1 << 0)86 87/* ICL DSI MODE control */88#define _ICL_DSI_IO_MODECTL_0 0x6B09489#define _ICL_DSI_IO_MODECTL_1 0x6B89490#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \91 _ICL_DSI_IO_MODECTL_0, \92 _ICL_DSI_IO_MODECTL_1)93#define COMBO_PHY_MODE_DSI (1 << 0)94 95/* TGL DSI Chicken register */96#define _TGL_DSI_CHKN_REG_0 0x6B0C097#define _TGL_DSI_CHKN_REG_1 0x6B8C098#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \99 _TGL_DSI_CHKN_REG_0, \100 _TGL_DSI_CHKN_REG_1)101#define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)102#define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \103 (byte_clocks))104#define _ICL_DSI_T_INIT_MASTER_0 0x6b088105#define _ICL_DSI_T_INIT_MASTER_1 0x6b888106#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \107 _ICL_DSI_T_INIT_MASTER_0,\108 _ICL_DSI_T_INIT_MASTER_1)109#define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0)110 111#define _DPHY_CLK_TIMING_PARAM_0 0x162180112#define _DPHY_CLK_TIMING_PARAM_1 0x6c180113#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \114 _DPHY_CLK_TIMING_PARAM_0,\115 _DPHY_CLK_TIMING_PARAM_1)116#define _DSI_CLK_TIMING_PARAM_0 0x6b080117#define _DSI_CLK_TIMING_PARAM_1 0x6b880118#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \119 _DSI_CLK_TIMING_PARAM_0,\120 _DSI_CLK_TIMING_PARAM_1)121#define CLK_PREPARE_OVERRIDE (1 << 31)122#define CLK_PREPARE(x) ((x) << 28)123#define CLK_PREPARE_MASK (0x7 << 28)124#define CLK_PREPARE_SHIFT 28125#define CLK_ZERO_OVERRIDE (1 << 27)126#define CLK_ZERO(x) ((x) << 20)127#define CLK_ZERO_MASK (0xf << 20)128#define CLK_ZERO_SHIFT 20129#define CLK_PRE_OVERRIDE (1 << 19)130#define CLK_PRE(x) ((x) << 16)131#define CLK_PRE_MASK (0x3 << 16)132#define CLK_PRE_SHIFT 16133#define CLK_POST_OVERRIDE (1 << 15)134#define CLK_POST(x) ((x) << 8)135#define CLK_POST_MASK (0x7 << 8)136#define CLK_POST_SHIFT 8137#define CLK_TRAIL_OVERRIDE (1 << 7)138#define CLK_TRAIL(x) ((x) << 0)139#define CLK_TRAIL_MASK (0xf << 0)140#define CLK_TRAIL_SHIFT 0141 142#define _DPHY_DATA_TIMING_PARAM_0 0x162184143#define _DPHY_DATA_TIMING_PARAM_1 0x6c184144#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \145 _DPHY_DATA_TIMING_PARAM_0,\146 _DPHY_DATA_TIMING_PARAM_1)147#define _DSI_DATA_TIMING_PARAM_0 0x6B084148#define _DSI_DATA_TIMING_PARAM_1 0x6B884149#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \150 _DSI_DATA_TIMING_PARAM_0,\151 _DSI_DATA_TIMING_PARAM_1)152#define HS_PREPARE_OVERRIDE (1 << 31)153#define HS_PREPARE(x) ((x) << 24)154#define HS_PREPARE_MASK (0x7 << 24)155#define HS_PREPARE_SHIFT 24156#define HS_ZERO_OVERRIDE (1 << 23)157#define HS_ZERO(x) ((x) << 16)158#define HS_ZERO_MASK (0xf << 16)159#define HS_ZERO_SHIFT 16160#define HS_TRAIL_OVERRIDE (1 << 15)161#define HS_TRAIL(x) ((x) << 8)162#define HS_TRAIL_MASK (0x7 << 8)163#define HS_TRAIL_SHIFT 8164#define HS_EXIT_OVERRIDE (1 << 7)165#define HS_EXIT(x) ((x) << 0)166#define HS_EXIT_MASK (0x7 << 0)167#define HS_EXIT_SHIFT 0168 169#define _DPHY_TA_TIMING_PARAM_0 0x162188170#define _DPHY_TA_TIMING_PARAM_1 0x6c188171#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \172 _DPHY_TA_TIMING_PARAM_0,\173 _DPHY_TA_TIMING_PARAM_1)174#define _DSI_TA_TIMING_PARAM_0 0x6b098175#define _DSI_TA_TIMING_PARAM_1 0x6b898176#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \177 _DSI_TA_TIMING_PARAM_0,\178 _DSI_TA_TIMING_PARAM_1)179#define TA_SURE_OVERRIDE (1 << 31)180#define TA_SURE(x) ((x) << 16)181#define TA_SURE_MASK (0x1f << 16)182#define TA_SURE_SHIFT 16183#define TA_GO_OVERRIDE (1 << 15)184#define TA_GO(x) ((x) << 8)185#define TA_GO_MASK (0xf << 8)186#define TA_GO_SHIFT 8187#define TA_GET_OVERRIDE (1 << 7)188#define TA_GET(x) ((x) << 0)189#define TA_GET_MASK (0xf << 0)190#define TA_GET_SHIFT 0191 192/* DSI transcoder configuration */193#define _DSI_TRANS_FUNC_CONF_0 0x6b030194#define _DSI_TRANS_FUNC_CONF_1 0x6b830195#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \196 _DSI_TRANS_FUNC_CONF_0,\197 _DSI_TRANS_FUNC_CONF_1)198#define OP_MODE_MASK (0x3 << 28)199#define OP_MODE_SHIFT 28200#define CMD_MODE_NO_GATE (0x0 << 28)201#define CMD_MODE_TE_GATE (0x1 << 28)202#define VIDEO_MODE_SYNC_EVENT (0x2 << 28)203#define VIDEO_MODE_SYNC_PULSE (0x3 << 28)204#define TE_SOURCE_GPIO (1 << 27)205#define LINK_READY (1 << 20)206#define PIX_FMT_MASK (0x3 << 16)207#define PIX_FMT_SHIFT 16208#define PIX_FMT_RGB565 (0x0 << 16)209#define PIX_FMT_RGB666_PACKED (0x1 << 16)210#define PIX_FMT_RGB666_LOOSE (0x2 << 16)211#define PIX_FMT_RGB888 (0x3 << 16)212#define PIX_FMT_RGB101010 (0x4 << 16)213#define PIX_FMT_RGB121212 (0x5 << 16)214#define PIX_FMT_COMPRESSED (0x6 << 16)215#define BGR_TRANSMISSION (1 << 15)216#define PIX_VIRT_CHAN(x) ((x) << 12)217#define PIX_VIRT_CHAN_MASK (0x3 << 12)218#define PIX_VIRT_CHAN_SHIFT 12219#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)220#define PIX_BUF_THRESHOLD_SHIFT 10221#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)222#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)223#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)224#define PIX_BUF_THRESHOLD_FULL (0x3 << 10)225#define CONTINUOUS_CLK_MASK (0x3 << 8)226#define CONTINUOUS_CLK_SHIFT 8227#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)228#define CLK_HS_OR_LP (0x2 << 8)229#define CLK_HS_CONTINUOUS (0x3 << 8)230#define LINK_CALIBRATION_MASK (0x3 << 4)231#define LINK_CALIBRATION_SHIFT 4232#define CALIBRATION_DISABLED (0x0 << 4)233#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)234#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)235#define BLANKING_PACKET_ENABLE (1 << 2)236#define S3D_ORIENTATION_LANDSCAPE (1 << 1)237#define EOTP_DISABLED (1 << 0)238 239#define _DSI_CMD_RXCTL_0 0x6b0d4240#define _DSI_CMD_RXCTL_1 0x6b8d4241#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \242 _DSI_CMD_RXCTL_0,\243 _DSI_CMD_RXCTL_1)244#define READ_UNLOADS_DW (1 << 16)245#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)246#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)247#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)248#define RECEIVED_RESET_TRIGGER (1 << 12)249#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)250#define RECEIVED_CRC_WAS_LOST (1 << 10)251#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)252#define NUMBER_RX_PLOAD_DW_SHIFT 0253 254#define _DSI_CMD_TXCTL_0 0x6b0d0255#define _DSI_CMD_TXCTL_1 0x6b8d0256#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \257 _DSI_CMD_TXCTL_0,\258 _DSI_CMD_TXCTL_1)259#define KEEP_LINK_IN_HS (1 << 24)260#define FREE_HEADER_CREDIT_MASK (0x1f << 8)261#define FREE_HEADER_CREDIT_SHIFT 0x8262#define FREE_PLOAD_CREDIT_MASK (0xff << 0)263#define FREE_PLOAD_CREDIT_SHIFT 0264#define MAX_HEADER_CREDIT 0x10265#define MAX_PLOAD_CREDIT 0x40266 267#define _DSI_CMD_TXHDR_0 0x6b100268#define _DSI_CMD_TXHDR_1 0x6b900269#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \270 _DSI_CMD_TXHDR_0,\271 _DSI_CMD_TXHDR_1)272#define PAYLOAD_PRESENT (1 << 31)273#define LP_DATA_TRANSFER (1 << 30)274#define VBLANK_FENCE (1 << 29)275#define PARAM_WC_MASK (0xffff << 8)276#define PARAM_WC_LOWER_SHIFT 8277#define PARAM_WC_UPPER_SHIFT 16278#define VC_MASK (0x3 << 6)279#define VC_SHIFT 6280#define DT_MASK (0x3f << 0)281#define DT_SHIFT 0282 283#define _DSI_CMD_TXPYLD_0 0x6b104284#define _DSI_CMD_TXPYLD_1 0x6b904285#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \286 _DSI_CMD_TXPYLD_0,\287 _DSI_CMD_TXPYLD_1)288 289#define _DSI_LP_MSG_0 0x6b0d8290#define _DSI_LP_MSG_1 0x6b8d8291#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \292 _DSI_LP_MSG_0,\293 _DSI_LP_MSG_1)294#define LPTX_IN_PROGRESS (1 << 17)295#define LINK_IN_ULPS (1 << 16)296#define LINK_ULPS_TYPE_LP11 (1 << 8)297#define LINK_ENTER_ULPS (1 << 0)298 299/* DSI timeout registers */300#define _DSI_HSTX_TO_0 0x6b044301#define _DSI_HSTX_TO_1 0x6b844302#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \303 _DSI_HSTX_TO_0,\304 _DSI_HSTX_TO_1)305#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)306#define HSTX_TIMEOUT_VALUE_SHIFT 16307#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)308#define HSTX_TIMED_OUT (1 << 0)309 310#define _DSI_LPRX_HOST_TO_0 0x6b048311#define _DSI_LPRX_HOST_TO_1 0x6b848312#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \313 _DSI_LPRX_HOST_TO_0,\314 _DSI_LPRX_HOST_TO_1)315#define LPRX_TIMED_OUT (1 << 16)316#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)317#define LPRX_TIMEOUT_VALUE_SHIFT 0318#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)319 320#define _DSI_PWAIT_TO_0 0x6b040321#define _DSI_PWAIT_TO_1 0x6b840322#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \323 _DSI_PWAIT_TO_0,\324 _DSI_PWAIT_TO_1)325#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)326#define PRESET_TIMEOUT_VALUE_SHIFT 16327#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)328#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)329#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0330#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)331 332#define _DSI_TA_TO_0 0x6b04c333#define _DSI_TA_TO_1 0x6b84c334#define DSI_TA_TO(tc) _MMIO_DSI(tc, \335 _DSI_TA_TO_0,\336 _DSI_TA_TO_1)337#define TA_TIMED_OUT (1 << 16)338#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)339#define TA_TIMEOUT_VALUE_SHIFT 0340#define TA_TIMEOUT_VALUE(x) ((x) << 0)341 342#endif /* __ICL_DSI_REGS_H__ */343