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1// SPDX-License-Identifier: MIT2/*3 * Copyright 2024, Intel Corporation.4 */5 6#include "intel_alpm.h"7#include "intel_crtc.h"8#include "intel_de.h"9#include "intel_display_types.h"10#include "intel_dp.h"11#include "intel_dp_aux.h"12#include "intel_psr_regs.h"13 14bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)15{16 return intel_dp->alpm_dpcd & DP_ALPM_CAP;17}18 19bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)20{21 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;22}23 24void intel_alpm_init_dpcd(struct intel_dp *intel_dp)25{26 u8 dpcd;27 28 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)29 return;30 31 intel_dp->alpm_dpcd = dpcd;32}33 34/*35 * See Bspec: 71632 for the table36 *37 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)38 *39 * Half cycle duration:40 *41 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns42 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )43 *44 * Link rates 5.4 - 8.145 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 1046 * LFPS Period chosen is the mid-point of the min:max values from the table47 * FLOOR( LFPS Period in Symbol clocks /48 * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) )49 */50static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate,51 int *silence_period,52 int *lfps_half_cycle)53{54 switch (link_rate) {55 case 162000:56 *silence_period = 20;57 *lfps_half_cycle = 5;58 break;59 case 216000:60 *silence_period = 27;61 *lfps_half_cycle = 7;62 break;63 case 243000:64 *silence_period = 31;65 *lfps_half_cycle = 8;66 break;67 case 270000:68 *silence_period = 34;69 *lfps_half_cycle = 9;70 break;71 case 324000:72 *silence_period = 41;73 *lfps_half_cycle = 11;74 break;75 case 432000:76 *silence_period = 56;77 *lfps_half_cycle = 15;78 break;79 case 540000:80 *silence_period = 69;81 *lfps_half_cycle = 12;82 break;83 case 648000:84 *silence_period = 84;85 *lfps_half_cycle = 15;86 break;87 case 675000:88 *silence_period = 87;89 *lfps_half_cycle = 15;90 break;91 case 810000:92 *silence_period = 104;93 *lfps_half_cycle = 19;94 break;95 default:96 *silence_period = *lfps_half_cycle = -1;97 return false;98 }99 return true;100}101 102/*103 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+104 * tSilence, Max+ tPHY Establishment + tCDS) / tline)105 * For the "PHY P2 to P0" latency see the PHY Power Control page106 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965107 * : 12 us108 * The tLFPS_Period, Max term is 800ns109 * The tSilence, Max term is 180ns110 * The tPHY Establishment (a.k.a. t1) term is 50us111 * The tCDS term is 1 or 2 times t2112 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK113 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)114 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and115 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start116 * within the CDS period complete within the CDS period regardless of117 * entry into the period118 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )119 * TPS4 Length = 252 Symbols120 */121static int _lnl_compute_aux_less_wake_time(int port_clock)122{123 int tphy2_p2_to_p0 = 12 * 1000;124 int tlfps_period_max = 800;125 int tsilence_max = 180;126 int t1 = 50 * 1000;127 int tps4 = 252;128 /* port_clock is link rate in 10kbit/s units */129 int tml_phy_lock = 1000 * 1000 * tps4 / port_clock;130 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;131 int t2 = num_ml_phy_lock * tml_phy_lock;132 int tcds = 1 * t2;133 134 return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max +135 t1 + tcds, 1000);136}137 138static int139_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,140 const struct intel_crtc_state *crtc_state)141{142 struct intel_display *display = to_intel_display(intel_dp);143 int aux_less_wake_time, aux_less_wake_lines, silence_period,144 lfps_half_cycle;145 146 aux_less_wake_time =147 _lnl_compute_aux_less_wake_time(crtc_state->port_clock);148 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,149 aux_less_wake_time);150 151 if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock,152 &silence_period,153 &lfps_half_cycle))154 return false;155 156 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||157 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||158 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)159 return false;160 161 if (display->params.psr_safest_params)162 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;163 164 intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;165 intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period;166 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;167 168 return true;169}170 171static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,172 const struct intel_crtc_state *crtc_state)173{174 struct intel_display *display = to_intel_display(intel_dp);175 int check_entry_lines;176 177 if (DISPLAY_VER(display) < 20)178 return true;179 180 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */181 check_entry_lines = 2 +182 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5);183 184 if (check_entry_lines > 15)185 return false;186 187 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))188 return false;189 190 if (display->params.psr_safest_params)191 check_entry_lines = 15;192 193 intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;194 195 return true;196}197 198/*199 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There200 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are201 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us.202 */203static int skl_io_buffer_wake_time(void)204{205 return 18;206}207 208static int tgl_io_buffer_wake_time(void)209{210 return 10;211}212 213static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)214{215 struct intel_display *display = to_intel_display(crtc_state);216 217 if (DISPLAY_VER(display) >= 12)218 return tgl_io_buffer_wake_time();219 else220 return skl_io_buffer_wake_time();221}222 223bool intel_alpm_compute_params(struct intel_dp *intel_dp,224 const struct intel_crtc_state *crtc_state)225{226 struct intel_display *display = to_intel_display(intel_dp);227 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;228 int tfw_exit_latency = 20; /* eDP spec */229 int phy_wake = 4; /* eDP spec */230 int preamble = 8; /* eDP spec */231 int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;232 u8 max_wake_lines;233 234 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +235 preamble + phy_wake + tfw_exit_latency;236 fast_wake_time = precharge + preamble + phy_wake +237 tfw_exit_latency;238 239 if (DISPLAY_VER(display) >= 20)240 max_wake_lines = 68;241 else if (DISPLAY_VER(display) >= 12)242 max_wake_lines = 12;243 else244 max_wake_lines = 8;245 246 io_wake_lines = intel_usecs_to_scanlines(247 &crtc_state->hw.adjusted_mode, io_wake_time);248 fast_wake_lines = intel_usecs_to_scanlines(249 &crtc_state->hw.adjusted_mode, fast_wake_time);250 251 if (io_wake_lines > max_wake_lines ||252 fast_wake_lines > max_wake_lines)253 return false;254 255 if (!_lnl_compute_alpm_params(intel_dp, crtc_state))256 return false;257 258 if (display->params.psr_safest_params)259 io_wake_lines = fast_wake_lines = max_wake_lines;260 261 /* According to Bspec lower limit should be set as 7 lines. */262 intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7);263 intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);264 265 return true;266}267 268void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,269 struct intel_crtc_state *crtc_state,270 struct drm_connector_state *conn_state)271{272 struct intel_display *display = to_intel_display(intel_dp);273 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;274 int waketime_in_lines, first_sdp_position;275 int context_latency, guardband;276 277 if (!intel_dp_is_edp(intel_dp))278 return;279 280 if (DISPLAY_VER(display) < 20)281 return;282 283 if (!intel_dp->as_sdp_supported)284 return;285 286 if (crtc_state->has_psr)287 return;288 289 if (!(intel_alpm_aux_wake_supported(intel_dp) ||290 intel_alpm_aux_less_wake_supported(intel_dp)))291 return;292 293 if (!intel_alpm_compute_params(intel_dp, crtc_state))294 return;295 296 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;297 guardband = adjusted_mode->crtc_vtotal -298 adjusted_mode->crtc_vdisplay - context_latency;299 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;300 if (intel_alpm_aux_less_wake_supported(intel_dp))301 waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;302 else303 waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines;304 305 crtc_state->has_lobf = (context_latency + guardband) >306 (first_sdp_position + waketime_in_lines);307}308 309static void lnl_alpm_configure(struct intel_dp *intel_dp,310 const struct intel_crtc_state *crtc_state)311{312 struct intel_display *display = to_intel_display(intel_dp);313 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;314 enum port port = dp_to_dig_port(intel_dp)->base.port;315 u32 alpm_ctl;316 317 if (DISPLAY_VER(display) < 20 ||318 (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp)))319 return;320 321 /*322 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to323 * check panel support at this point.324 */325 if ((intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) ||326 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) {327 alpm_ctl = ALPM_CTL_ALPM_ENABLE |328 ALPM_CTL_ALPM_AUX_LESS_ENABLE |329 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |330 ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);331 332 intel_de_write(display,333 PORT_ALPM_CTL(display, port),334 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |335 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |336 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |337 PORT_ALPM_CTL_SILENCE_PERIOD(338 intel_dp->alpm_parameters.silence_period_sym_clocks));339 340 intel_de_write(display,341 PORT_ALPM_LFPS_CTL(display, port),342 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |343 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(344 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |345 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(346 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |347 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(348 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));349 } else {350 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |351 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);352 }353 354 if (crtc_state->has_lobf)355 alpm_ctl |= ALPM_CTL_LOBF_ENABLE;356 357 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);358 359 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);360}361 362void intel_alpm_configure(struct intel_dp *intel_dp,363 const struct intel_crtc_state *crtc_state)364{365 lnl_alpm_configure(intel_dp, crtc_state);366}367 368static int i915_edp_lobf_info_show(struct seq_file *m, void *data)369{370 struct intel_connector *connector = m->private;371 struct intel_display *display = to_intel_display(connector);372 struct drm_crtc *crtc;373 struct intel_crtc_state *crtc_state;374 enum transcoder cpu_transcoder;375 u32 alpm_ctl;376 int ret;377 378 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);379 if (ret)380 return ret;381 382 crtc = connector->base.state->crtc;383 if (connector->base.status != connector_status_connected || !crtc) {384 ret = -ENODEV;385 goto out;386 }387 388 crtc_state = to_intel_crtc_state(crtc->state);389 cpu_transcoder = crtc_state->cpu_transcoder;390 alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));391 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE));392 seq_printf(m, "Aux-wake alpm status: %s\n",393 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));394 seq_printf(m, "Aux-less alpm status: %s\n",395 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));396out:397 drm_modeset_unlock(&display->drm->mode_config.connection_mutex);398 399 return ret;400}401 402DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);403 404void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)405{406 struct intel_display *display = to_intel_display(connector);407 struct dentry *root = connector->base.debugfs_entry;408 409 if (DISPLAY_VER(display) < 20 ||410 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)411 return;412 413 debugfs_create_file("i915_edp_lobf_info", 0444, root,414 connector, &i915_edp_lobf_info_fops);415}416