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1/*2 * Copyright © 2014 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER21 * DEALINGS IN THE SOFTWARE.22 */23 24/**25 * DOC: atomic plane helpers26 *27 * The functions here are used by the atomic plane helper functions to28 * implement legacy plane updates (i.e., drm_plane->update_plane() and29 * drm_plane->disable_plane()). This allows plane updates to use the30 * atomic state infrastructure and perform plane updates as separate31 * prepare/check/commit/cleanup steps.32 */33 34#include <linux/dma-fence-chain.h>35#include <linux/dma-resv.h>36 37#include <drm/drm_atomic_helper.h>38#include <drm/drm_gem_atomic_helper.h>39#include <drm/drm_blend.h>40#include <drm/drm_fourcc.h>41 42#include "i915_config.h"43#include "i9xx_plane_regs.h"44#include "intel_atomic_plane.h"45#include "intel_cdclk.h"46#include "intel_cursor.h"47#include "intel_display_rps.h"48#include "intel_display_trace.h"49#include "intel_display_types.h"50#include "intel_fb.h"51#include "intel_fb_pin.h"52#include "skl_scaler.h"53#include "skl_watermark.h"54 55static void intel_plane_state_reset(struct intel_plane_state *plane_state,56 struct intel_plane *plane)57{58 memset(plane_state, 0, sizeof(*plane_state));59 60 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);61 62 plane_state->scaler_id = -1;63}64 65struct intel_plane *intel_plane_alloc(void)66{67 struct intel_plane_state *plane_state;68 struct intel_plane *plane;69 70 plane = kzalloc(sizeof(*plane), GFP_KERNEL);71 if (!plane)72 return ERR_PTR(-ENOMEM);73 74 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);75 if (!plane_state) {76 kfree(plane);77 return ERR_PTR(-ENOMEM);78 }79 80 intel_plane_state_reset(plane_state, plane);81 82 plane->base.state = &plane_state->uapi;83 84 return plane;85}86 87void intel_plane_free(struct intel_plane *plane)88{89 intel_plane_destroy_state(&plane->base, plane->base.state);90 kfree(plane);91}92 93/**94 * intel_plane_duplicate_state - duplicate plane state95 * @plane: drm plane96 *97 * Allocates and returns a copy of the plane state (both common and98 * Intel-specific) for the specified plane.99 *100 * Returns: The newly allocated plane state, or NULL on failure.101 */102struct drm_plane_state *103intel_plane_duplicate_state(struct drm_plane *plane)104{105 struct intel_plane_state *intel_state;106 107 intel_state = to_intel_plane_state(plane->state);108 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);109 110 if (!intel_state)111 return NULL;112 113 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);114 115 intel_state->ggtt_vma = NULL;116 intel_state->dpt_vma = NULL;117 intel_state->flags = 0;118 119 /* add reference to fb */120 if (intel_state->hw.fb)121 drm_framebuffer_get(intel_state->hw.fb);122 123 return &intel_state->uapi;124}125 126/**127 * intel_plane_destroy_state - destroy plane state128 * @plane: drm plane129 * @state: state object to destroy130 *131 * Destroys the plane state (both common and Intel-specific) for the132 * specified plane.133 */134void135intel_plane_destroy_state(struct drm_plane *plane,136 struct drm_plane_state *state)137{138 struct intel_plane_state *plane_state = to_intel_plane_state(state);139 140 drm_WARN_ON(plane->dev, plane_state->ggtt_vma);141 drm_WARN_ON(plane->dev, plane_state->dpt_vma);142 143 __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);144 if (plane_state->hw.fb)145 drm_framebuffer_put(plane_state->hw.fb);146 kfree(plane_state);147}148 149bool intel_plane_needs_physical(struct intel_plane *plane)150{151 struct drm_i915_private *i915 = to_i915(plane->base.dev);152 153 return plane->id == PLANE_CURSOR &&154 DISPLAY_INFO(i915)->cursor_needs_physical;155}156 157unsigned int intel_adjusted_rate(const struct drm_rect *src,158 const struct drm_rect *dst,159 unsigned int rate)160{161 unsigned int src_w, src_h, dst_w, dst_h;162 163 src_w = drm_rect_width(src) >> 16;164 src_h = drm_rect_height(src) >> 16;165 dst_w = drm_rect_width(dst);166 dst_h = drm_rect_height(dst);167 168 /* Downscaling limits the maximum pixel rate */169 dst_w = min(src_w, dst_w);170 dst_h = min(src_h, dst_h);171 172 return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),173 dst_w * dst_h);174}175 176unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,177 const struct intel_plane_state *plane_state)178{179 /*180 * Note we don't check for plane visibility here as181 * we want to use this when calculating the cursor182 * watermarks even if the cursor is fully offscreen.183 * That depends on the src/dst rectangles being184 * correctly populated whenever the watermark code185 * considers the cursor to be visible, whether or not186 * it is actually visible.187 *188 * See: intel_wm_plane_visible() and intel_check_cursor()189 */190 191 return intel_adjusted_rate(&plane_state->uapi.src,192 &plane_state->uapi.dst,193 crtc_state->pixel_rate);194}195 196unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,197 const struct intel_plane_state *plane_state,198 int color_plane)199{200 const struct drm_framebuffer *fb = plane_state->hw.fb;201 202 if (!plane_state->uapi.visible)203 return 0;204 205 return intel_plane_pixel_rate(crtc_state, plane_state) *206 fb->format->cpp[color_plane];207}208 209static bool210use_min_ddb(const struct intel_crtc_state *crtc_state,211 struct intel_plane *plane)212{213 struct drm_i915_private *i915 = to_i915(plane->base.dev);214 215 return DISPLAY_VER(i915) >= 13 &&216 crtc_state->uapi.async_flip &&217 plane->async_flip;218}219 220static unsigned int221intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,222 const struct intel_plane_state *plane_state,223 int color_plane)224{225 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);226 const struct drm_framebuffer *fb = plane_state->hw.fb;227 int width, height;228 unsigned int rel_data_rate;229 230 if (plane->id == PLANE_CURSOR)231 return 0;232 233 if (!plane_state->uapi.visible)234 return 0;235 236 /*237 * We calculate extra ddb based on ratio plane rate/total data rate238 * in case, in some cases we should not allocate extra ddb for the plane,239 * so do not count its data rate, if this is the case.240 */241 if (use_min_ddb(crtc_state, plane))242 return 0;243 244 /*245 * Src coordinates are already rotated by 270 degrees for246 * the 90/270 degree plane rotation cases (to match the247 * GTT mapping), hence no need to account for rotation here.248 */249 width = drm_rect_width(&plane_state->uapi.src) >> 16;250 height = drm_rect_height(&plane_state->uapi.src) >> 16;251 252 /* UV plane does 1/2 pixel sub-sampling */253 if (color_plane == 1) {254 width /= 2;255 height /= 2;256 }257 258 rel_data_rate = width * height * fb->format->cpp[color_plane];259 260 return intel_adjusted_rate(&plane_state->uapi.src,261 &plane_state->uapi.dst,262 rel_data_rate);263}264 265int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,266 struct intel_plane *plane,267 bool *need_cdclk_calc)268{269 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);270 const struct intel_plane_state *plane_state =271 intel_atomic_get_new_plane_state(state, plane);272 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);273 const struct intel_cdclk_state *cdclk_state;274 const struct intel_crtc_state *old_crtc_state;275 struct intel_crtc_state *new_crtc_state;276 277 if (!plane_state->uapi.visible || !plane->min_cdclk)278 return 0;279 280 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);281 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);282 283 new_crtc_state->min_cdclk[plane->id] =284 plane->min_cdclk(new_crtc_state, plane_state);285 286 /*287 * No need to check against the cdclk state if288 * the min cdclk for the plane doesn't increase.289 *290 * Ie. we only ever increase the cdclk due to plane291 * requirements. This can reduce back and forth292 * display blinking due to constant cdclk changes.293 */294 if (new_crtc_state->min_cdclk[plane->id] <=295 old_crtc_state->min_cdclk[plane->id])296 return 0;297 298 cdclk_state = intel_atomic_get_cdclk_state(state);299 if (IS_ERR(cdclk_state))300 return PTR_ERR(cdclk_state);301 302 /*303 * No need to recalculate the cdclk state if304 * the min cdclk for the pipe doesn't increase.305 *306 * Ie. we only ever increase the cdclk due to plane307 * requirements. This can reduce back and forth308 * display blinking due to constant cdclk changes.309 */310 if (new_crtc_state->min_cdclk[plane->id] <=311 cdclk_state->min_cdclk[crtc->pipe])312 return 0;313 314 drm_dbg_kms(&dev_priv->drm,315 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",316 plane->base.base.id, plane->base.name,317 new_crtc_state->min_cdclk[plane->id],318 crtc->base.base.id, crtc->base.name,319 cdclk_state->min_cdclk[crtc->pipe]);320 *need_cdclk_calc = true;321 322 return 0;323}324 325static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)326{327 if (plane_state->hw.fb)328 drm_framebuffer_put(plane_state->hw.fb);329 330 memset(&plane_state->hw, 0, sizeof(plane_state->hw));331}332 333void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,334 const struct intel_plane_state *from_plane_state,335 struct intel_crtc *crtc)336{337 intel_plane_clear_hw_state(plane_state);338 339 /*340 * For the joiner secondary uapi.crtc will point at341 * the primary crtc. So we explicitly assign the right342 * secondary crtc to hw.crtc. uapi.crtc!=NULL simply343 * indicates the plane is logically enabled on the uapi level.344 */345 plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;346 347 plane_state->hw.fb = from_plane_state->uapi.fb;348 if (plane_state->hw.fb)349 drm_framebuffer_get(plane_state->hw.fb);350 351 plane_state->hw.alpha = from_plane_state->uapi.alpha;352 plane_state->hw.pixel_blend_mode =353 from_plane_state->uapi.pixel_blend_mode;354 plane_state->hw.rotation = from_plane_state->uapi.rotation;355 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;356 plane_state->hw.color_range = from_plane_state->uapi.color_range;357 plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;358 359 plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);360 plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);361}362 363void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,364 const struct intel_plane_state *from_plane_state)365{366 intel_plane_clear_hw_state(plane_state);367 368 memcpy(&plane_state->hw, &from_plane_state->hw,369 sizeof(plane_state->hw));370 371 if (plane_state->hw.fb)372 drm_framebuffer_get(plane_state->hw.fb);373}374 375void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,376 struct intel_plane_state *plane_state)377{378 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);379 380 crtc_state->active_planes &= ~BIT(plane->id);381 crtc_state->scaled_planes &= ~BIT(plane->id);382 crtc_state->nv12_planes &= ~BIT(plane->id);383 crtc_state->c8_planes &= ~BIT(plane->id);384 crtc_state->async_flip_planes &= ~BIT(plane->id);385 crtc_state->data_rate[plane->id] = 0;386 crtc_state->data_rate_y[plane->id] = 0;387 crtc_state->rel_data_rate[plane->id] = 0;388 crtc_state->rel_data_rate_y[plane->id] = 0;389 crtc_state->min_cdclk[plane->id] = 0;390 391 plane_state->uapi.visible = false;392}393 394/* FIXME nuke when all wm code is atomic */395static bool intel_wm_need_update(const struct intel_plane_state *cur,396 struct intel_plane_state *new)397{398 /* Update watermarks on tiling or size changes. */399 if (new->uapi.visible != cur->uapi.visible)400 return true;401 402 if (!cur->hw.fb || !new->hw.fb)403 return false;404 405 if (cur->hw.fb->modifier != new->hw.fb->modifier ||406 cur->hw.rotation != new->hw.rotation ||407 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||408 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||409 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||410 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))411 return true;412 413 return false;414}415 416static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)417{418 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;419 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;420 int dst_w = drm_rect_width(&plane_state->uapi.dst);421 int dst_h = drm_rect_height(&plane_state->uapi.dst);422 423 return src_w != dst_w || src_h != dst_h;424}425 426static bool intel_plane_do_async_flip(struct intel_plane *plane,427 const struct intel_crtc_state *old_crtc_state,428 const struct intel_crtc_state *new_crtc_state)429{430 struct drm_i915_private *i915 = to_i915(plane->base.dev);431 432 if (!plane->async_flip)433 return false;434 435 if (!new_crtc_state->uapi.async_flip)436 return false;437 438 /*439 * In platforms after DISPLAY13, we might need to override440 * first async flip in order to change watermark levels441 * as part of optimization.442 *443 * And let's do this for all skl+ so that we can eg. change the444 * modifier as well.445 *446 * TODO: For older platforms there is less reason to do this as447 * only X-tile is supported with async flips, though we could448 * extend this so other scanout parameters (stride/etc) could449 * be changed as well...450 */451 return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip;452}453 454static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,455 const struct intel_plane_state *old_plane_state,456 const struct intel_plane_state *new_plane_state)457{458 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);459 bool old_visible = old_plane_state->uapi.visible;460 bool new_visible = new_plane_state->uapi.visible;461 u32 old_ctl = old_plane_state->ctl;462 u32 new_ctl = new_plane_state->ctl;463 bool modeset, turn_on, turn_off;464 465 if (plane->id == PLANE_CURSOR)466 return false;467 468 modeset = intel_crtc_needs_modeset(new_crtc_state);469 turn_off = old_visible && (!new_visible || modeset);470 turn_on = new_visible && (!old_visible || modeset);471 472 /* Must disable CxSR around plane enable/disable */473 if (turn_on || turn_off)474 return true;475 476 if (!old_visible || !new_visible)477 return false;478 479 /*480 * Most plane control register updates are blocked while in CxSR.481 *482 * Tiling mode is one exception where the primary plane can483 * apparently handle it, whereas the sprites can not (the484 * sprite issue being only relevant on VLV/CHV where CxSR485 * is actually possible with a sprite enabled).486 */487 if (plane->id == PLANE_PRIMARY) {488 old_ctl &= ~DISP_TILED;489 new_ctl &= ~DISP_TILED;490 }491 492 return old_ctl != new_ctl;493}494 495static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,496 struct intel_crtc_state *new_crtc_state,497 const struct intel_plane_state *old_plane_state,498 struct intel_plane_state *new_plane_state)499{500 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);501 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);502 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);503 bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);504 bool was_crtc_enabled = old_crtc_state->hw.active;505 bool is_crtc_enabled = new_crtc_state->hw.active;506 bool turn_off, turn_on, visible, was_visible;507 int ret;508 509 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {510 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);511 if (ret)512 return ret;513 }514 515 was_visible = old_plane_state->uapi.visible;516 visible = new_plane_state->uapi.visible;517 518 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))519 was_visible = false;520 521 /*522 * Visibility is calculated as if the crtc was on, but523 * after scaler setup everything depends on it being off524 * when the crtc isn't active.525 *526 * FIXME this is wrong for watermarks. Watermarks should also527 * be computed as if the pipe would be active. Perhaps move528 * per-plane wm computation to the .check_plane() hook, and529 * only combine the results from all planes in the current place?530 */531 if (!is_crtc_enabled) {532 intel_plane_set_invisible(new_crtc_state, new_plane_state);533 visible = false;534 }535 536 if (!was_visible && !visible)537 return 0;538 539 turn_off = was_visible && (!visible || mode_changed);540 turn_on = visible && (!was_visible || mode_changed);541 542 drm_dbg_atomic(&dev_priv->drm,543 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",544 crtc->base.base.id, crtc->base.name,545 plane->base.base.id, plane->base.name,546 was_visible, visible,547 turn_off, turn_on, mode_changed);548 549 if (turn_on) {550 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))551 new_crtc_state->update_wm_pre = true;552 } else if (turn_off) {553 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))554 new_crtc_state->update_wm_post = true;555 } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {556 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {557 /* FIXME bollocks */558 new_crtc_state->update_wm_pre = true;559 new_crtc_state->update_wm_post = true;560 }561 }562 563 if (visible || was_visible)564 new_crtc_state->fb_bits |= plane->frontbuffer_bit;565 566 if (HAS_GMCH(dev_priv) &&567 i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))568 new_crtc_state->disable_cxsr = true;569 570 /*571 * ILK/SNB DVSACNTR/Sprite Enable572 * IVB SPR_CTL/Sprite Enable573 * "When in Self Refresh Big FIFO mode, a write to enable the574 * plane will be internally buffered and delayed while Big FIFO575 * mode is exiting."576 *577 * Which means that enabling the sprite can take an extra frame578 * when we start in big FIFO mode (LP1+). Thus we need to drop579 * down to LP0 and wait for vblank in order to make sure the580 * sprite gets enabled on the next vblank after the register write.581 * Doing otherwise would risk enabling the sprite one frame after582 * we've already signalled flip completion. We can resume LP1+583 * once the sprite has been enabled.584 *585 *586 * WaCxSRDisabledForSpriteScaling:ivb587 * IVB SPR_SCALE/Scaling Enable588 * "Low Power watermarks must be disabled for at least one589 * frame before enabling sprite scaling, and kept disabled590 * until sprite scaling is disabled."591 *592 * ILK/SNB DVSASCALE/Scaling Enable593 * "When in Self Refresh Big FIFO mode, scaling enable will be594 * masked off while Big FIFO mode is exiting."595 *596 * Despite the w/a only being listed for IVB we assume that597 * the ILK/SNB note has similar ramifications, hence we apply598 * the w/a on all three platforms.599 *600 * With experimental results seems this is needed also for primary601 * plane, not only sprite plane.602 */603 if (plane->id != PLANE_CURSOR &&604 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||605 IS_IVYBRIDGE(dev_priv)) &&606 (turn_on || (!intel_plane_is_scaled(old_plane_state) &&607 intel_plane_is_scaled(new_plane_state))))608 new_crtc_state->disable_lp_wm = true;609 610 if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {611 new_crtc_state->do_async_flip = true;612 new_crtc_state->async_flip_planes |= BIT(plane->id);613 } else if (plane->need_async_flip_toggle_wa &&614 new_crtc_state->uapi.async_flip) {615 /*616 * On platforms with double buffered async flip bit we617 * set the bit already one frame early during the sync618 * flip (see {i9xx,skl}_plane_update_arm()). The619 * hardware will therefore be ready to perform a real620 * async flip during the next commit, without having621 * to wait yet another frame for the bit to latch.622 */623 new_crtc_state->async_flip_planes |= BIT(plane->id);624 }625 626 return 0;627}628 629int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,630 struct intel_crtc_state *new_crtc_state,631 const struct intel_plane_state *old_plane_state,632 struct intel_plane_state *new_plane_state)633{634 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);635 const struct drm_framebuffer *fb = new_plane_state->hw.fb;636 int ret;637 638 intel_plane_set_invisible(new_crtc_state, new_plane_state);639 new_crtc_state->enabled_planes &= ~BIT(plane->id);640 641 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)642 return 0;643 644 ret = plane->check_plane(new_crtc_state, new_plane_state);645 if (ret)646 return ret;647 648 if (fb)649 new_crtc_state->enabled_planes |= BIT(plane->id);650 651 /* FIXME pre-g4x don't work like this */652 if (new_plane_state->uapi.visible)653 new_crtc_state->active_planes |= BIT(plane->id);654 655 if (new_plane_state->uapi.visible &&656 intel_plane_is_scaled(new_plane_state))657 new_crtc_state->scaled_planes |= BIT(plane->id);658 659 if (new_plane_state->uapi.visible &&660 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))661 new_crtc_state->nv12_planes |= BIT(plane->id);662 663 if (new_plane_state->uapi.visible &&664 fb->format->format == DRM_FORMAT_C8)665 new_crtc_state->c8_planes |= BIT(plane->id);666 667 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)668 new_crtc_state->update_planes |= BIT(plane->id);669 670 if (new_plane_state->uapi.visible &&671 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {672 new_crtc_state->data_rate_y[plane->id] =673 intel_plane_data_rate(new_crtc_state, new_plane_state, 0);674 new_crtc_state->data_rate[plane->id] =675 intel_plane_data_rate(new_crtc_state, new_plane_state, 1);676 677 new_crtc_state->rel_data_rate_y[plane->id] =678 intel_plane_relative_data_rate(new_crtc_state,679 new_plane_state, 0);680 new_crtc_state->rel_data_rate[plane->id] =681 intel_plane_relative_data_rate(new_crtc_state,682 new_plane_state, 1);683 } else if (new_plane_state->uapi.visible) {684 new_crtc_state->data_rate[plane->id] =685 intel_plane_data_rate(new_crtc_state, new_plane_state, 0);686 687 new_crtc_state->rel_data_rate[plane->id] =688 intel_plane_relative_data_rate(new_crtc_state,689 new_plane_state, 0);690 }691 692 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,693 old_plane_state, new_plane_state);694}695 696static struct intel_plane *697intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)698{699 struct drm_i915_private *i915 = to_i915(crtc->base.dev);700 struct intel_plane *plane;701 702 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {703 if (plane->id == plane_id)704 return plane;705 }706 707 return NULL;708}709 710int intel_plane_atomic_check(struct intel_atomic_state *state,711 struct intel_plane *plane)712{713 struct drm_i915_private *i915 = to_i915(state->base.dev);714 struct intel_plane_state *new_plane_state =715 intel_atomic_get_new_plane_state(state, plane);716 const struct intel_plane_state *old_plane_state =717 intel_atomic_get_old_plane_state(state, plane);718 const struct intel_plane_state *new_primary_crtc_plane_state;719 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);720 const struct intel_crtc_state *old_crtc_state =721 intel_atomic_get_old_crtc_state(state, crtc);722 struct intel_crtc_state *new_crtc_state =723 intel_atomic_get_new_crtc_state(state, crtc);724 725 if (new_crtc_state && intel_crtc_is_joiner_secondary(new_crtc_state)) {726 struct intel_crtc *primary_crtc =727 intel_primary_crtc(new_crtc_state);728 struct intel_plane *primary_crtc_plane =729 intel_crtc_get_plane(primary_crtc, plane->id);730 731 new_primary_crtc_plane_state =732 intel_atomic_get_new_plane_state(state, primary_crtc_plane);733 } else {734 new_primary_crtc_plane_state = new_plane_state;735 }736 737 intel_plane_copy_uapi_to_hw_state(new_plane_state,738 new_primary_crtc_plane_state,739 crtc);740 741 new_plane_state->uapi.visible = false;742 if (!new_crtc_state)743 return 0;744 745 return intel_plane_atomic_check_with_state(old_crtc_state,746 new_crtc_state,747 old_plane_state,748 new_plane_state);749}750 751static struct intel_plane *752skl_next_plane_to_commit(struct intel_atomic_state *state,753 struct intel_crtc *crtc,754 struct skl_ddb_entry ddb[I915_MAX_PLANES],755 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],756 unsigned int *update_mask)757{758 struct intel_crtc_state *crtc_state =759 intel_atomic_get_new_crtc_state(state, crtc);760 struct intel_plane_state __maybe_unused *plane_state;761 struct intel_plane *plane;762 int i;763 764 if (*update_mask == 0)765 return NULL;766 767 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {768 enum plane_id plane_id = plane->id;769 770 if (crtc->pipe != plane->pipe ||771 !(*update_mask & BIT(plane_id)))772 continue;773 774 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],775 ddb, I915_MAX_PLANES, plane_id) ||776 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],777 ddb_y, I915_MAX_PLANES, plane_id))778 continue;779 780 *update_mask &= ~BIT(plane_id);781 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];782 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];783 784 return plane;785 }786 787 /* should never happen */788 drm_WARN_ON(state->base.dev, 1);789 790 return NULL;791}792 793void intel_plane_update_noarm(struct intel_plane *plane,794 const struct intel_crtc_state *crtc_state,795 const struct intel_plane_state *plane_state)796{797 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);798 799 trace_intel_plane_update_noarm(plane, crtc);800 801 if (plane->update_noarm)802 plane->update_noarm(plane, crtc_state, plane_state);803}804 805void intel_plane_async_flip(struct intel_plane *plane,806 const struct intel_crtc_state *crtc_state,807 const struct intel_plane_state *plane_state,808 bool async_flip)809{810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);811 812 trace_intel_plane_async_flip(plane, crtc, async_flip);813 plane->async_flip(plane, crtc_state, plane_state, async_flip);814}815 816void intel_plane_update_arm(struct intel_plane *plane,817 const struct intel_crtc_state *crtc_state,818 const struct intel_plane_state *plane_state)819{820 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);821 822 if (crtc_state->do_async_flip && plane->async_flip) {823 intel_plane_async_flip(plane, crtc_state, plane_state, true);824 return;825 }826 827 trace_intel_plane_update_arm(plane, crtc);828 plane->update_arm(plane, crtc_state, plane_state);829}830 831void intel_plane_disable_arm(struct intel_plane *plane,832 const struct intel_crtc_state *crtc_state)833{834 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);835 836 trace_intel_plane_disable_arm(plane, crtc);837 plane->disable_arm(plane, crtc_state);838}839 840void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,841 struct intel_crtc *crtc)842{843 struct intel_crtc_state *new_crtc_state =844 intel_atomic_get_new_crtc_state(state, crtc);845 u32 update_mask = new_crtc_state->update_planes;846 struct intel_plane_state *new_plane_state;847 struct intel_plane *plane;848 int i;849 850 if (new_crtc_state->do_async_flip)851 return;852 853 /*854 * Since we only write non-arming registers here,855 * the order does not matter even for skl+.856 */857 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {858 if (crtc->pipe != plane->pipe ||859 !(update_mask & BIT(plane->id)))860 continue;861 862 /* TODO: for mailbox updates this should be skipped */863 if (new_plane_state->uapi.visible ||864 new_plane_state->planar_slave)865 intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);866 }867}868 869static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,870 struct intel_crtc *crtc)871{872 struct intel_crtc_state *old_crtc_state =873 intel_atomic_get_old_crtc_state(state, crtc);874 struct intel_crtc_state *new_crtc_state =875 intel_atomic_get_new_crtc_state(state, crtc);876 struct skl_ddb_entry ddb[I915_MAX_PLANES];877 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];878 u32 update_mask = new_crtc_state->update_planes;879 struct intel_plane *plane;880 881 memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,882 sizeof(old_crtc_state->wm.skl.plane_ddb));883 memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,884 sizeof(old_crtc_state->wm.skl.plane_ddb_y));885 886 while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {887 struct intel_plane_state *new_plane_state =888 intel_atomic_get_new_plane_state(state, plane);889 890 /*891 * TODO: for mailbox updates intel_plane_update_noarm()892 * would have to be called here as well.893 */894 if (new_plane_state->uapi.visible ||895 new_plane_state->planar_slave)896 intel_plane_update_arm(plane, new_crtc_state, new_plane_state);897 else898 intel_plane_disable_arm(plane, new_crtc_state);899 }900}901 902static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,903 struct intel_crtc *crtc)904{905 struct intel_crtc_state *new_crtc_state =906 intel_atomic_get_new_crtc_state(state, crtc);907 u32 update_mask = new_crtc_state->update_planes;908 struct intel_plane_state *new_plane_state;909 struct intel_plane *plane;910 int i;911 912 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {913 if (crtc->pipe != plane->pipe ||914 !(update_mask & BIT(plane->id)))915 continue;916 917 /*918 * TODO: for mailbox updates intel_plane_update_noarm()919 * would have to be called here as well.920 */921 if (new_plane_state->uapi.visible)922 intel_plane_update_arm(plane, new_crtc_state, new_plane_state);923 else924 intel_plane_disable_arm(plane, new_crtc_state);925 }926}927 928void intel_crtc_planes_update_arm(struct intel_atomic_state *state,929 struct intel_crtc *crtc)930{931 struct drm_i915_private *i915 = to_i915(state->base.dev);932 933 if (DISPLAY_VER(i915) >= 9)934 skl_crtc_planes_update_arm(state, crtc);935 else936 i9xx_crtc_planes_update_arm(state, crtc);937}938 939int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,940 struct intel_crtc_state *crtc_state,941 int min_scale, int max_scale,942 bool can_position)943{944 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);945 struct drm_framebuffer *fb = plane_state->hw.fb;946 struct drm_rect *src = &plane_state->uapi.src;947 struct drm_rect *dst = &plane_state->uapi.dst;948 const struct drm_rect *clip = &crtc_state->pipe_src;949 unsigned int rotation = plane_state->hw.rotation;950 int hscale, vscale;951 952 if (!fb) {953 plane_state->uapi.visible = false;954 return 0;955 }956 957 drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);958 959 /* Check scaling */960 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);961 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);962 if (hscale < 0 || vscale < 0) {963 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");964 drm_rect_debug_print("src: ", src, true);965 drm_rect_debug_print("dst: ", dst, false);966 return -ERANGE;967 }968 969 /*970 * FIXME: This might need further adjustment for seamless scaling971 * with phase information, for the 2p2 and 2p1 scenarios.972 */973 plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);974 975 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);976 977 if (!can_position && plane_state->uapi.visible &&978 !drm_rect_equals(dst, clip)) {979 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");980 drm_rect_debug_print("dst: ", dst, false);981 drm_rect_debug_print("clip: ", clip, false);982 return -EINVAL;983 }984 985 /* final plane coordinates will be relative to the plane's pipe */986 drm_rect_translate(dst, -clip->x1, -clip->y1);987 988 return 0;989}990 991int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)992{993 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);994 const struct drm_framebuffer *fb = plane_state->hw.fb;995 struct drm_rect *src = &plane_state->uapi.src;996 u32 src_x, src_y, src_w, src_h, hsub, vsub;997 bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);998 999 /*1000 * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS1001 * abuses hsub/vsub so we can't use them here. But as they1002 * are limited to 32bpp RGB formats we don't actually need1003 * to check anything.1004 */1005 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||1006 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)1007 return 0;1008 1009 /*1010 * Hardware doesn't handle subpixel coordinates.1011 * Adjust to (macro)pixel boundary, but be careful not to1012 * increase the source viewport size, because that could1013 * push the downscaling factor out of bounds.1014 */1015 src_x = src->x1 >> 16;1016 src_w = drm_rect_width(src) >> 16;1017 src_y = src->y1 >> 16;1018 src_h = drm_rect_height(src) >> 16;1019 1020 drm_rect_init(src, src_x << 16, src_y << 16,1021 src_w << 16, src_h << 16);1022 1023 if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {1024 hsub = 2;1025 vsub = 2;1026 } else if (DISPLAY_VER(i915) >= 20 &&1027 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {1028 /*1029 * This allows NV12 and P0xx formats to have odd size and/or odd1030 * source coordinates on DISPLAY_VER(i915) >= 201031 */1032 hsub = 1;1033 vsub = 1;1034 } else {1035 hsub = fb->format->hsub;1036 vsub = fb->format->vsub;1037 }1038 1039 if (rotated)1040 hsub = vsub = max(hsub, vsub);1041 1042 if (src_x % hsub || src_w % hsub) {1043 drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",1044 src_x, src_w, hsub, str_yes_no(rotated));1045 return -EINVAL;1046 }1047 1048 if (src_y % vsub || src_h % vsub) {1049 drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",1050 src_y, src_h, vsub, str_yes_no(rotated));1051 return -EINVAL;1052 }1053 1054 return 0;1055}1056 1057static int add_dma_resv_fences(struct dma_resv *resv,1058 struct drm_plane_state *new_plane_state)1059{1060 struct dma_fence *fence = dma_fence_get(new_plane_state->fence);1061 struct dma_fence *new;1062 int ret;1063 1064 ret = dma_resv_get_singleton(resv, dma_resv_usage_rw(false), &new);1065 if (ret)1066 goto error;1067 1068 if (new && fence) {1069 struct dma_fence_chain *chain = dma_fence_chain_alloc();1070 1071 if (!chain) {1072 ret = -ENOMEM;1073 goto error;1074 }1075 1076 dma_fence_chain_init(chain, fence, new, 1);1077 fence = &chain->base;1078 1079 } else if (new) {1080 fence = new;1081 }1082 1083 dma_fence_put(new_plane_state->fence);1084 new_plane_state->fence = fence;1085 return 0;1086 1087error:1088 dma_fence_put(fence);1089 return ret;1090}1091 1092/**1093 * intel_prepare_plane_fb - Prepare fb for usage on plane1094 * @_plane: drm plane to prepare for1095 * @_new_plane_state: the plane state being prepared1096 *1097 * Prepares a framebuffer for usage on a display plane. Generally this1098 * involves pinning the underlying object and updating the frontbuffer tracking1099 * bits. Some older platforms need special physical address handling for1100 * cursor planes.1101 *1102 * Returns 0 on success, negative error code on failure.1103 */1104static int1105intel_prepare_plane_fb(struct drm_plane *_plane,1106 struct drm_plane_state *_new_plane_state)1107{1108 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };1109 struct intel_plane *plane = to_intel_plane(_plane);1110 struct intel_plane_state *new_plane_state =1111 to_intel_plane_state(_new_plane_state);1112 struct intel_atomic_state *state =1113 to_intel_atomic_state(new_plane_state->uapi.state);1114 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);1115 struct intel_plane_state *old_plane_state =1116 intel_atomic_get_old_plane_state(state, plane);1117 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);1118 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);1119 int ret;1120 1121 if (old_obj) {1122 const struct intel_crtc_state *new_crtc_state =1123 intel_atomic_get_new_crtc_state(state,1124 to_intel_crtc(old_plane_state->hw.crtc));1125 1126 /* Big Hammer, we also need to ensure that any pending1127 * MI_WAIT_FOR_EVENT inside a user batch buffer on the1128 * current scanout is retired before unpinning the old1129 * framebuffer. Note that we rely on userspace rendering1130 * into the buffer attached to the pipe they are waiting1131 * on. If not, userspace generates a GPU hang with IPEHR1132 * point to the MI_WAIT_FOR_EVENT.1133 *1134 * This should only fail upon a hung GPU, in which case we1135 * can safely continue.1136 */1137 if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) {1138 ret = add_dma_resv_fences(intel_bo_to_drm_bo(old_obj)->resv,1139 &new_plane_state->uapi);1140 if (ret < 0)1141 return ret;1142 }1143 }1144 1145 if (!obj)1146 return 0;1147 1148 ret = intel_plane_pin_fb(new_plane_state);1149 if (ret)1150 return ret;1151 1152 ret = drm_gem_plane_helper_prepare_fb(&plane->base, &new_plane_state->uapi);1153 if (ret < 0)1154 goto unpin_fb;1155 1156 if (new_plane_state->uapi.fence) {1157 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,1158 &attr);1159 1160 intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,1161 new_plane_state->uapi.fence);1162 }1163 1164 /*1165 * We declare pageflips to be interactive and so merit a small bias1166 * towards upclocking to deliver the frame on time. By only changing1167 * the RPS thresholds to sample more regularly and aim for higher1168 * clocks we can hopefully deliver low power workloads (like kodi)1169 * that are not quite steady state without resorting to forcing1170 * maximum clocks following a vblank miss (see do_rps_boost()).1171 */1172 intel_display_rps_mark_interactive(dev_priv, state, true);1173 1174 return 0;1175 1176unpin_fb:1177 intel_plane_unpin_fb(new_plane_state);1178 1179 return ret;1180}1181 1182/**1183 * intel_cleanup_plane_fb - Cleans up an fb after plane use1184 * @plane: drm plane to clean up for1185 * @_old_plane_state: the state from the previous modeset1186 *1187 * Cleans up a framebuffer that has just been removed from a plane.1188 */1189static void1190intel_cleanup_plane_fb(struct drm_plane *plane,1191 struct drm_plane_state *_old_plane_state)1192{1193 struct intel_plane_state *old_plane_state =1194 to_intel_plane_state(_old_plane_state);1195 struct intel_atomic_state *state =1196 to_intel_atomic_state(old_plane_state->uapi.state);1197 struct drm_i915_private *dev_priv = to_i915(plane->dev);1198 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);1199 1200 if (!obj)1201 return;1202 1203 intel_display_rps_mark_interactive(dev_priv, state, false);1204 1205 intel_plane_unpin_fb(old_plane_state);1206}1207 1208static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {1209 .prepare_fb = intel_prepare_plane_fb,1210 .cleanup_fb = intel_cleanup_plane_fb,1211};1212 1213void intel_plane_helper_add(struct intel_plane *plane)1214{1215 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);1216}1217 1218void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,1219 struct intel_plane_state *new_plane_state)1220{1221 if (!old_plane_state->ggtt_vma ||1222 old_plane_state->ggtt_vma == new_plane_state->ggtt_vma)1223 return;1224 1225 drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc,1226 intel_cursor_unpin_work);1227}1228