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1/*2 * Copyright © 2006 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE21 * SOFTWARE.22 *23 * Authors:24 * Eric Anholt <eric@anholt.net>25 *26 */27 28#include <linux/firmware.h>29 30#include <drm/display/drm_dp_helper.h>31#include <drm/display/drm_dsc_helper.h>32#include <drm/drm_edid.h>33#include <drm/drm_fixed.h>34 35#include "i915_drv.h"36#include "i915_reg.h"37#include "intel_display.h"38#include "intel_display_types.h"39#include "intel_gmbus.h"40#include "intel_uncore.h"41 42#define _INTEL_BIOS_PRIVATE43#include "intel_vbt_defs.h"44 45/**46 * DOC: Video BIOS Table (VBT)47 *48 * The Video BIOS Table, or VBT, provides platform and board specific49 * configuration information to the driver that is not discoverable or available50 * through other means. The configuration is mostly related to display51 * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in52 * the PCI ROM.53 *54 * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB55 * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that56 * contain the actual configuration information. The VBT Header, and thus the57 * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the58 * BDB Header. The data blocks are concatenated after the BDB Header. The data59 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of60 * data. (Block 53, the MIPI Sequence Block is an exception.)61 *62 * The driver parses the VBT during load. The relevant information is stored in63 * driver private data for ease of use, and the actual VBT is not read after64 * that.65 */66 67/* Wrapper for VBT child device config */68struct intel_bios_encoder_data {69 struct intel_display *display;70 71 struct child_device_config child;72 struct dsc_compression_parameters_entry *dsc;73 struct list_head node;74};75 76#define TARGET_ADDR1 0x7077#define TARGET_ADDR2 0x7278 79/* Get BDB block size given a pointer to Block ID. */80static u32 _get_blocksize(const u8 *block_base)81{82 /* The MIPI Sequence Block v3+ has a separate size field. */83 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3)84 return *((const u32 *)(block_base + 4));85 else86 return *((const u16 *)(block_base + 1));87}88 89/* Get BDB block size give a pointer to data after Block ID and Block Size. */90static u32 get_blocksize(const void *block_data)91{92 return _get_blocksize(block_data - 3);93}94 95static const void *96find_raw_section(const void *_bdb, enum bdb_block_id section_id)97{98 const struct bdb_header *bdb = _bdb;99 const u8 *base = _bdb;100 int index = 0;101 u32 total, current_size;102 enum bdb_block_id current_id;103 104 /* skip to first section */105 index += bdb->header_size;106 total = bdb->bdb_size;107 108 /* walk the sections looking for section_id */109 while (index + 3 < total) {110 current_id = *(base + index);111 current_size = _get_blocksize(base + index);112 index += 3;113 114 if (index + current_size > total)115 return NULL;116 117 if (current_id == section_id)118 return base + index;119 120 index += current_size;121 }122 123 return NULL;124}125 126/*127 * Offset from the start of BDB to the start of the128 * block data (just past the block header).129 */130static u32 raw_block_offset(const void *bdb, enum bdb_block_id section_id)131{132 const void *block;133 134 block = find_raw_section(bdb, section_id);135 if (!block)136 return 0;137 138 return block - bdb;139}140 141struct bdb_block_entry {142 struct list_head node;143 enum bdb_block_id section_id;144 u8 data[];145};146 147static const void *148bdb_find_section(struct intel_display *display,149 enum bdb_block_id section_id)150{151 struct bdb_block_entry *entry;152 153 list_for_each_entry(entry, &display->vbt.bdb_blocks, node) {154 if (entry->section_id == section_id)155 return entry->data + 3;156 }157 158 return NULL;159}160 161static const struct {162 enum bdb_block_id section_id;163 size_t min_size;164} bdb_blocks[] = {165 { .section_id = BDB_GENERAL_FEATURES,166 .min_size = sizeof(struct bdb_general_features), },167 { .section_id = BDB_GENERAL_DEFINITIONS,168 .min_size = sizeof(struct bdb_general_definitions), },169 { .section_id = BDB_PSR,170 .min_size = sizeof(struct bdb_psr), },171 { .section_id = BDB_DRIVER_FEATURES,172 .min_size = sizeof(struct bdb_driver_features), },173 { .section_id = BDB_SDVO_LVDS_OPTIONS,174 .min_size = sizeof(struct bdb_sdvo_lvds_options), },175 { .section_id = BDB_SDVO_LVDS_DTD,176 .min_size = sizeof(struct bdb_sdvo_lvds_dtd), },177 { .section_id = BDB_EDP,178 .min_size = sizeof(struct bdb_edp), },179 { .section_id = BDB_LFP_OPTIONS,180 .min_size = sizeof(struct bdb_lfp_options), },181 /*182 * BDB_LFP_DATA depends on BDB_LFP_DATA_PTRS,183 * so keep the two ordered.184 */185 { .section_id = BDB_LFP_DATA_PTRS,186 .min_size = sizeof(struct bdb_lfp_data_ptrs), },187 { .section_id = BDB_LFP_DATA,188 .min_size = 0, /* special case */ },189 { .section_id = BDB_LFP_BACKLIGHT,190 .min_size = sizeof(struct bdb_lfp_backlight), },191 { .section_id = BDB_LFP_POWER,192 .min_size = sizeof(struct bdb_lfp_power), },193 { .section_id = BDB_MIPI_CONFIG,194 .min_size = sizeof(struct bdb_mipi_config), },195 { .section_id = BDB_MIPI_SEQUENCE,196 .min_size = sizeof(struct bdb_mipi_sequence) },197 { .section_id = BDB_COMPRESSION_PARAMETERS,198 .min_size = sizeof(struct bdb_compression_parameters), },199 { .section_id = BDB_GENERIC_DTD,200 .min_size = sizeof(struct bdb_generic_dtd), },201};202 203static size_t lfp_data_min_size(struct intel_display *display)204{205 const struct bdb_lfp_data_ptrs *ptrs;206 size_t size;207 208 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);209 if (!ptrs)210 return 0;211 212 size = sizeof(struct bdb_lfp_data);213 if (ptrs->panel_name.table_size)214 size = max(size, ptrs->panel_name.offset +215 sizeof(struct bdb_lfp_data_tail));216 217 return size;218}219 220static bool validate_lfp_data_ptrs(const void *bdb,221 const struct bdb_lfp_data_ptrs *ptrs)222{223 int fp_timing_size, dvo_timing_size, panel_pnp_id_size, panel_name_size;224 int data_block_size, lfp_data_size;225 const void *data_block;226 int i;227 228 data_block = find_raw_section(bdb, BDB_LFP_DATA);229 if (!data_block)230 return false;231 232 data_block_size = get_blocksize(data_block);233 if (data_block_size == 0)234 return false;235 236 /* always 3 indicating the presence of fp_timing+dvo_timing+panel_pnp_id */237 if (ptrs->num_entries != 3)238 return false;239 240 fp_timing_size = ptrs->ptr[0].fp_timing.table_size;241 dvo_timing_size = ptrs->ptr[0].dvo_timing.table_size;242 panel_pnp_id_size = ptrs->ptr[0].panel_pnp_id.table_size;243 panel_name_size = ptrs->panel_name.table_size;244 245 /* fp_timing has variable size */246 if (fp_timing_size < 32 ||247 dvo_timing_size != sizeof(struct bdb_edid_dtd) ||248 panel_pnp_id_size != sizeof(struct bdb_edid_pnp_id))249 return false;250 251 /* panel_name is not present in old VBTs */252 if (panel_name_size != 0 &&253 panel_name_size != sizeof(struct bdb_edid_product_name))254 return false;255 256 lfp_data_size = ptrs->ptr[1].fp_timing.offset - ptrs->ptr[0].fp_timing.offset;257 if (16 * lfp_data_size > data_block_size)258 return false;259 260 /* make sure the table entries have uniform size */261 for (i = 1; i < 16; i++) {262 if (ptrs->ptr[i].fp_timing.table_size != fp_timing_size ||263 ptrs->ptr[i].dvo_timing.table_size != dvo_timing_size ||264 ptrs->ptr[i].panel_pnp_id.table_size != panel_pnp_id_size)265 return false;266 267 if (ptrs->ptr[i].fp_timing.offset - ptrs->ptr[i-1].fp_timing.offset != lfp_data_size ||268 ptrs->ptr[i].dvo_timing.offset - ptrs->ptr[i-1].dvo_timing.offset != lfp_data_size ||269 ptrs->ptr[i].panel_pnp_id.offset - ptrs->ptr[i-1].panel_pnp_id.offset != lfp_data_size)270 return false;271 }272 273 /*274 * Except for vlv/chv machines all real VBTs seem to have 6275 * unaccounted bytes in the fp_timing table. And it doesn't276 * appear to be a really intentional hole as the fp_timing277 * 0xffff terminator is always within those 6 missing bytes.278 */279 if (fp_timing_size + 6 + dvo_timing_size + panel_pnp_id_size == lfp_data_size)280 fp_timing_size += 6;281 282 if (fp_timing_size + dvo_timing_size + panel_pnp_id_size != lfp_data_size)283 return false;284 285 if (ptrs->ptr[0].fp_timing.offset + fp_timing_size != ptrs->ptr[0].dvo_timing.offset ||286 ptrs->ptr[0].dvo_timing.offset + dvo_timing_size != ptrs->ptr[0].panel_pnp_id.offset ||287 ptrs->ptr[0].panel_pnp_id.offset + panel_pnp_id_size != lfp_data_size)288 return false;289 290 /* make sure the tables fit inside the data block */291 for (i = 0; i < 16; i++) {292 if (ptrs->ptr[i].fp_timing.offset + fp_timing_size > data_block_size ||293 ptrs->ptr[i].dvo_timing.offset + dvo_timing_size > data_block_size ||294 ptrs->ptr[i].panel_pnp_id.offset + panel_pnp_id_size > data_block_size)295 return false;296 }297 298 if (ptrs->panel_name.offset + 16 * panel_name_size > data_block_size)299 return false;300 301 /* make sure fp_timing terminators are present at expected locations */302 for (i = 0; i < 16; i++) {303 const u16 *t = data_block + ptrs->ptr[i].fp_timing.offset +304 fp_timing_size - 2;305 306 if (*t != 0xffff)307 return false;308 }309 310 return true;311}312 313/* make the data table offsets relative to the data block */314static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block)315{316 struct bdb_lfp_data_ptrs *ptrs = ptrs_block;317 u32 offset;318 int i;319 320 offset = raw_block_offset(bdb, BDB_LFP_DATA);321 322 for (i = 0; i < 16; i++) {323 if (ptrs->ptr[i].fp_timing.offset < offset ||324 ptrs->ptr[i].dvo_timing.offset < offset ||325 ptrs->ptr[i].panel_pnp_id.offset < offset)326 return false;327 328 ptrs->ptr[i].fp_timing.offset -= offset;329 ptrs->ptr[i].dvo_timing.offset -= offset;330 ptrs->ptr[i].panel_pnp_id.offset -= offset;331 }332 333 if (ptrs->panel_name.table_size) {334 if (ptrs->panel_name.offset < offset)335 return false;336 337 ptrs->panel_name.offset -= offset;338 }339 340 return validate_lfp_data_ptrs(bdb, ptrs);341}342 343static int make_lfp_data_ptr(struct lfp_data_ptr_table *table,344 int table_size, int total_size)345{346 if (total_size < table_size)347 return total_size;348 349 table->table_size = table_size;350 table->offset = total_size - table_size;351 352 return total_size - table_size;353}354 355static void next_lfp_data_ptr(struct lfp_data_ptr_table *next,356 const struct lfp_data_ptr_table *prev,357 int size)358{359 next->table_size = prev->table_size;360 next->offset = prev->offset + size;361}362 363static void *generate_lfp_data_ptrs(struct intel_display *display,364 const void *bdb)365{366 int i, size, table_size, block_size, offset, fp_timing_size;367 struct bdb_lfp_data_ptrs *ptrs;368 const void *block;369 void *ptrs_block;370 371 /*372 * The hardcoded fp_timing_size is only valid for373 * modernish VBTs. All older VBTs definitely should374 * include block 41 and thus we don't need to375 * generate one.376 */377 if (display->vbt.version < 155)378 return NULL;379 380 fp_timing_size = 38;381 382 block = find_raw_section(bdb, BDB_LFP_DATA);383 if (!block)384 return NULL;385 386 drm_dbg_kms(display->drm, "Generating LFP data table pointers\n");387 388 block_size = get_blocksize(block);389 390 size = fp_timing_size + sizeof(struct bdb_edid_dtd) +391 sizeof(struct bdb_edid_pnp_id);392 if (size * 16 > block_size)393 return NULL;394 395 ptrs_block = kzalloc(sizeof(*ptrs) + 3, GFP_KERNEL);396 if (!ptrs_block)397 return NULL;398 399 *(u8 *)(ptrs_block + 0) = BDB_LFP_DATA_PTRS;400 *(u16 *)(ptrs_block + 1) = sizeof(*ptrs);401 ptrs = ptrs_block + 3;402 403 table_size = sizeof(struct bdb_edid_pnp_id);404 size = make_lfp_data_ptr(&ptrs->ptr[0].panel_pnp_id, table_size, size);405 406 table_size = sizeof(struct bdb_edid_dtd);407 size = make_lfp_data_ptr(&ptrs->ptr[0].dvo_timing, table_size, size);408 409 table_size = fp_timing_size;410 size = make_lfp_data_ptr(&ptrs->ptr[0].fp_timing, table_size, size);411 412 if (ptrs->ptr[0].fp_timing.table_size)413 ptrs->num_entries++;414 if (ptrs->ptr[0].dvo_timing.table_size)415 ptrs->num_entries++;416 if (ptrs->ptr[0].panel_pnp_id.table_size)417 ptrs->num_entries++;418 419 if (size != 0 || ptrs->num_entries != 3) {420 kfree(ptrs_block);421 return NULL;422 }423 424 size = fp_timing_size + sizeof(struct bdb_edid_dtd) +425 sizeof(struct bdb_edid_pnp_id);426 for (i = 1; i < 16; i++) {427 next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, &ptrs->ptr[i-1].fp_timing, size);428 next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, &ptrs->ptr[i-1].dvo_timing, size);429 next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, &ptrs->ptr[i-1].panel_pnp_id, size);430 }431 432 table_size = sizeof(struct bdb_edid_product_name);433 434 if (16 * (size + table_size) <= block_size) {435 ptrs->panel_name.table_size = table_size;436 ptrs->panel_name.offset = size * 16;437 }438 439 offset = block - bdb;440 441 for (i = 0; i < 16; i++) {442 ptrs->ptr[i].fp_timing.offset += offset;443 ptrs->ptr[i].dvo_timing.offset += offset;444 ptrs->ptr[i].panel_pnp_id.offset += offset;445 }446 447 if (ptrs->panel_name.table_size)448 ptrs->panel_name.offset += offset;449 450 return ptrs_block;451}452 453static void454init_bdb_block(struct intel_display *display,455 const void *bdb, enum bdb_block_id section_id,456 size_t min_size)457{458 struct bdb_block_entry *entry;459 void *temp_block = NULL;460 const void *block;461 size_t block_size;462 463 block = find_raw_section(bdb, section_id);464 465 /* Modern VBTs lack the LFP data table pointers block, make one up */466 if (!block && section_id == BDB_LFP_DATA_PTRS) {467 temp_block = generate_lfp_data_ptrs(display, bdb);468 if (temp_block)469 block = temp_block + 3;470 }471 if (!block)472 return;473 474 drm_WARN(display->drm, min_size == 0,475 "Block %d min_size is zero\n", section_id);476 477 block_size = get_blocksize(block);478 479 /*480 * Version number and new block size are considered481 * part of the header for MIPI sequenece block v3+.482 */483 if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3)484 block_size += 5;485 486 entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3),487 GFP_KERNEL);488 if (!entry) {489 kfree(temp_block);490 return;491 }492 493 entry->section_id = section_id;494 memcpy(entry->data, block - 3, block_size + 3);495 496 kfree(temp_block);497 498 drm_dbg_kms(display->drm,499 "Found BDB block %d (size %zu, min size %zu)\n",500 section_id, block_size, min_size);501 502 if (section_id == BDB_LFP_DATA_PTRS &&503 !fixup_lfp_data_ptrs(bdb, entry->data + 3)) {504 drm_err(display->drm,505 "VBT has malformed LFP data table pointers\n");506 kfree(entry);507 return;508 }509 510 list_add_tail(&entry->node, &display->vbt.bdb_blocks);511}512 513static void init_bdb_blocks(struct intel_display *display,514 const void *bdb)515{516 int i;517 518 for (i = 0; i < ARRAY_SIZE(bdb_blocks); i++) {519 enum bdb_block_id section_id = bdb_blocks[i].section_id;520 size_t min_size = bdb_blocks[i].min_size;521 522 if (section_id == BDB_LFP_DATA)523 min_size = lfp_data_min_size(display);524 525 init_bdb_block(display, bdb, section_id, min_size);526 }527}528 529static void530fill_detail_timing_data(struct intel_display *display,531 struct drm_display_mode *panel_fixed_mode,532 const struct bdb_edid_dtd *dvo_timing)533{534 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |535 dvo_timing->hactive_lo;536 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +537 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);538 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +539 ((dvo_timing->hsync_pulse_width_hi << 8) |540 dvo_timing->hsync_pulse_width_lo);541 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +542 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);543 544 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |545 dvo_timing->vactive_lo;546 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +547 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);548 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +549 ((dvo_timing->vsync_pulse_width_hi << 4) |550 dvo_timing->vsync_pulse_width_lo);551 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +552 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);553 panel_fixed_mode->clock = dvo_timing->clock * 10;554 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;555 556 if (dvo_timing->hsync_positive)557 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;558 else559 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;560 561 if (dvo_timing->vsync_positive)562 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;563 else564 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;565 566 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |567 dvo_timing->himage_lo;568 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |569 dvo_timing->vimage_lo;570 571 /* Some VBTs have bogus h/vsync_end values */572 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) {573 drm_dbg_kms(display->drm, "reducing hsync_end %d->%d\n",574 panel_fixed_mode->hsync_end, panel_fixed_mode->htotal);575 panel_fixed_mode->hsync_end = panel_fixed_mode->htotal;576 }577 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) {578 drm_dbg_kms(display->drm, "reducing vsync_end %d->%d\n",579 panel_fixed_mode->vsync_end, panel_fixed_mode->vtotal);580 panel_fixed_mode->vsync_end = panel_fixed_mode->vtotal;581 }582 583 drm_mode_set_name(panel_fixed_mode);584}585 586static const struct bdb_edid_dtd *587get_lfp_dvo_timing(const struct bdb_lfp_data *data,588 const struct bdb_lfp_data_ptrs *ptrs,589 int index)590{591 return (const void *)data + ptrs->ptr[index].dvo_timing.offset;592}593 594static const struct fp_timing *595get_lfp_fp_timing(const struct bdb_lfp_data *data,596 const struct bdb_lfp_data_ptrs *ptrs,597 int index)598{599 return (const void *)data + ptrs->ptr[index].fp_timing.offset;600}601 602static const struct drm_edid_product_id *603get_lfp_pnp_id(const struct bdb_lfp_data *data,604 const struct bdb_lfp_data_ptrs *ptrs,605 int index)606{607 /* These two are supposed to have the same layout in memory. */608 BUILD_BUG_ON(sizeof(struct bdb_edid_pnp_id) != sizeof(struct drm_edid_product_id));609 610 return (const void *)data + ptrs->ptr[index].panel_pnp_id.offset;611}612 613static const struct bdb_lfp_data_tail *614get_lfp_data_tail(const struct bdb_lfp_data *data,615 const struct bdb_lfp_data_ptrs *ptrs)616{617 if (ptrs->panel_name.table_size)618 return (const void *)data + ptrs->panel_name.offset;619 else620 return NULL;621}622 623static int opregion_get_panel_type(struct intel_display *display,624 const struct intel_bios_encoder_data *devdata,625 const struct drm_edid *drm_edid, bool use_fallback)626{627 return intel_opregion_get_panel_type(display);628}629 630static int vbt_get_panel_type(struct intel_display *display,631 const struct intel_bios_encoder_data *devdata,632 const struct drm_edid *drm_edid, bool use_fallback)633{634 const struct bdb_lfp_options *lfp_options;635 636 lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);637 if (!lfp_options)638 return -1;639 640 if (lfp_options->panel_type > 0xf &&641 lfp_options->panel_type != 0xff) {642 drm_dbg_kms(display->drm, "Invalid VBT panel type 0x%x\n",643 lfp_options->panel_type);644 return -1;645 }646 647 if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2)648 return lfp_options->panel_type2;649 650 drm_WARN_ON(display->drm,651 devdata && devdata->child.handle != DEVICE_HANDLE_LFP1);652 653 return lfp_options->panel_type;654}655 656static int pnpid_get_panel_type(struct intel_display *display,657 const struct intel_bios_encoder_data *devdata,658 const struct drm_edid *drm_edid, bool use_fallback)659{660 const struct bdb_lfp_data *data;661 const struct bdb_lfp_data_ptrs *ptrs;662 struct drm_edid_product_id product_id, product_id_nodate;663 struct drm_printer p;664 int i, best = -1;665 666 if (!drm_edid)667 return -1;668 669 drm_edid_get_product_id(drm_edid, &product_id);670 671 product_id_nodate = product_id;672 product_id_nodate.week_of_manufacture = 0;673 product_id_nodate.year_of_manufacture = 0;674 675 p = drm_dbg_printer(display->drm, DRM_UT_KMS, "EDID");676 drm_edid_print_product_id(&p, &product_id, true);677 678 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);679 if (!ptrs)680 return -1;681 682 data = bdb_find_section(display, BDB_LFP_DATA);683 if (!data)684 return -1;685 686 for (i = 0; i < 16; i++) {687 const struct drm_edid_product_id *vbt_id =688 get_lfp_pnp_id(data, ptrs, i);689 690 /* full match? */691 if (!memcmp(vbt_id, &product_id, sizeof(*vbt_id)))692 return i;693 694 /*695 * Accept a match w/o date if no full match is found,696 * and the VBT entry does not specify a date.697 */698 if (best < 0 &&699 !memcmp(vbt_id, &product_id_nodate, sizeof(*vbt_id)))700 best = i;701 }702 703 return best;704}705 706static int fallback_get_panel_type(struct intel_display *display,707 const struct intel_bios_encoder_data *devdata,708 const struct drm_edid *drm_edid, bool use_fallback)709{710 return use_fallback ? 0 : -1;711}712 713enum panel_type {714 PANEL_TYPE_OPREGION,715 PANEL_TYPE_VBT,716 PANEL_TYPE_PNPID,717 PANEL_TYPE_FALLBACK,718};719 720static int get_panel_type(struct intel_display *display,721 const struct intel_bios_encoder_data *devdata,722 const struct drm_edid *drm_edid, bool use_fallback)723{724 struct {725 const char *name;726 int (*get_panel_type)(struct intel_display *display,727 const struct intel_bios_encoder_data *devdata,728 const struct drm_edid *drm_edid, bool use_fallback);729 int panel_type;730 } panel_types[] = {731 [PANEL_TYPE_OPREGION] = {732 .name = "OpRegion",733 .get_panel_type = opregion_get_panel_type,734 },735 [PANEL_TYPE_VBT] = {736 .name = "VBT",737 .get_panel_type = vbt_get_panel_type,738 },739 [PANEL_TYPE_PNPID] = {740 .name = "PNPID",741 .get_panel_type = pnpid_get_panel_type,742 },743 [PANEL_TYPE_FALLBACK] = {744 .name = "fallback",745 .get_panel_type = fallback_get_panel_type,746 },747 };748 int i;749 750 for (i = 0; i < ARRAY_SIZE(panel_types); i++) {751 panel_types[i].panel_type = panel_types[i].get_panel_type(display, devdata,752 drm_edid, use_fallback);753 754 drm_WARN_ON(display->drm, panel_types[i].panel_type > 0xf &&755 panel_types[i].panel_type != 0xff);756 757 if (panel_types[i].panel_type >= 0)758 drm_dbg_kms(display->drm, "Panel type (%s): %d\n",759 panel_types[i].name, panel_types[i].panel_type);760 }761 762 if (panel_types[PANEL_TYPE_OPREGION].panel_type >= 0)763 i = PANEL_TYPE_OPREGION;764 else if (panel_types[PANEL_TYPE_VBT].panel_type == 0xff &&765 panel_types[PANEL_TYPE_PNPID].panel_type >= 0)766 i = PANEL_TYPE_PNPID;767 else if (panel_types[PANEL_TYPE_VBT].panel_type != 0xff &&768 panel_types[PANEL_TYPE_VBT].panel_type >= 0)769 i = PANEL_TYPE_VBT;770 else771 i = PANEL_TYPE_FALLBACK;772 773 drm_dbg_kms(display->drm, "Selected panel type (%s): %d\n",774 panel_types[i].name, panel_types[i].panel_type);775 776 return panel_types[i].panel_type;777}778 779static unsigned int panel_bits(unsigned int value, int panel_type, int num_bits)780{781 return (value >> (panel_type * num_bits)) & (BIT(num_bits) - 1);782}783 784static bool panel_bool(unsigned int value, int panel_type)785{786 return panel_bits(value, panel_type, 1);787}788 789/* Parse general panel options */790static void791parse_panel_options(struct intel_display *display,792 struct intel_panel *panel)793{794 const struct bdb_lfp_options *lfp_options;795 int panel_type = panel->vbt.panel_type;796 int drrs_mode;797 798 lfp_options = bdb_find_section(display, BDB_LFP_OPTIONS);799 if (!lfp_options)800 return;801 802 panel->vbt.lvds_dither = lfp_options->pixel_dither;803 804 /*805 * Empirical evidence indicates the block size can be806 * either 4,14,16,24+ bytes. For older VBTs no clear807 * relationship between the block size vs. BDB version.808 */809 if (get_blocksize(lfp_options) < 16)810 return;811 812 drrs_mode = panel_bits(lfp_options->dps_panel_type_bits,813 panel_type, 2);814 /*815 * VBT has static DRRS = 0 and seamless DRRS = 2.816 * The below piece of code is required to adjust vbt.drrs_type817 * to match the enum drrs_support_type.818 */819 switch (drrs_mode) {820 case 0:821 panel->vbt.drrs_type = DRRS_TYPE_STATIC;822 drm_dbg_kms(display->drm, "DRRS supported mode is static\n");823 break;824 case 2:825 panel->vbt.drrs_type = DRRS_TYPE_SEAMLESS;826 drm_dbg_kms(display->drm,827 "DRRS supported mode is seamless\n");828 break;829 default:830 panel->vbt.drrs_type = DRRS_TYPE_NONE;831 drm_dbg_kms(display->drm,832 "DRRS not supported (VBT input)\n");833 break;834 }835}836 837static void838parse_lfp_panel_dtd(struct intel_display *display,839 struct intel_panel *panel,840 const struct bdb_lfp_data *lfp_data,841 const struct bdb_lfp_data_ptrs *lfp_data_ptrs)842{843 const struct bdb_edid_dtd *panel_dvo_timing;844 const struct fp_timing *fp_timing;845 struct drm_display_mode *panel_fixed_mode;846 int panel_type = panel->vbt.panel_type;847 848 panel_dvo_timing = get_lfp_dvo_timing(lfp_data,849 lfp_data_ptrs,850 panel_type);851 852 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);853 if (!panel_fixed_mode)854 return;855 856 fill_detail_timing_data(display, panel_fixed_mode, panel_dvo_timing);857 858 panel->vbt.lfp_vbt_mode = panel_fixed_mode;859 860 drm_dbg_kms(display->drm,861 "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n",862 DRM_MODE_ARG(panel_fixed_mode));863 864 fp_timing = get_lfp_fp_timing(lfp_data,865 lfp_data_ptrs,866 panel_type);867 868 /* check the resolution, just to be sure */869 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&870 fp_timing->y_res == panel_fixed_mode->vdisplay) {871 panel->vbt.bios_lvds_val = fp_timing->lvds_reg_val;872 drm_dbg_kms(display->drm,873 "VBT initial LVDS value %x\n",874 panel->vbt.bios_lvds_val);875 }876}877 878static void879parse_lfp_data(struct intel_display *display,880 struct intel_panel *panel)881{882 const struct bdb_lfp_data *data;883 const struct bdb_lfp_data_tail *tail;884 const struct bdb_lfp_data_ptrs *ptrs;885 const struct drm_edid_product_id *pnp_id;886 struct drm_printer p;887 int panel_type = panel->vbt.panel_type;888 889 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS);890 if (!ptrs)891 return;892 893 data = bdb_find_section(display, BDB_LFP_DATA);894 if (!data)895 return;896 897 if (!panel->vbt.lfp_vbt_mode)898 parse_lfp_panel_dtd(display, panel, data, ptrs);899 900 pnp_id = get_lfp_pnp_id(data, ptrs, panel_type);901 902 p = drm_dbg_printer(display->drm, DRM_UT_KMS, "Panel");903 drm_edid_print_product_id(&p, pnp_id, false);904 905 tail = get_lfp_data_tail(data, ptrs);906 if (!tail)907 return;908 909 drm_dbg_kms(display->drm, "Panel name: %.*s\n",910 (int)sizeof(tail->panel_name[0].name),911 tail->panel_name[panel_type].name);912 913 if (display->vbt.version >= 188) {914 panel->vbt.seamless_drrs_min_refresh_rate =915 tail->seamless_drrs_min_refresh_rate[panel_type];916 drm_dbg_kms(display->drm,917 "Seamless DRRS min refresh rate: %d Hz\n",918 panel->vbt.seamless_drrs_min_refresh_rate);919 }920}921 922static void923parse_generic_dtd(struct intel_display *display,924 struct intel_panel *panel)925{926 const struct bdb_generic_dtd *generic_dtd;927 const struct generic_dtd_entry *dtd;928 struct drm_display_mode *panel_fixed_mode;929 int num_dtd;930 931 /*932 * Older VBTs provided DTD information for internal displays through933 * the "LFP panel tables" block (42). As of VBT revision 229 the934 * DTD information should be provided via a newer "generic DTD"935 * block (58). Just to be safe, we'll try the new generic DTD block936 * first on VBT >= 229, but still fall back to trying the old LFP937 * block if that fails.938 */939 if (display->vbt.version < 229)940 return;941 942 generic_dtd = bdb_find_section(display, BDB_GENERIC_DTD);943 if (!generic_dtd)944 return;945 946 if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) {947 drm_err(display->drm, "GDTD size %u is too small.\n",948 generic_dtd->gdtd_size);949 return;950 } else if (generic_dtd->gdtd_size !=951 sizeof(struct generic_dtd_entry)) {952 drm_err(display->drm, "Unexpected GDTD size %u\n",953 generic_dtd->gdtd_size);954 /* DTD has unknown fields, but keep going */955 }956 957 num_dtd = (get_blocksize(generic_dtd) -958 sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;959 if (panel->vbt.panel_type >= num_dtd) {960 drm_err(display->drm,961 "Panel type %d not found in table of %d DTD's\n",962 panel->vbt.panel_type, num_dtd);963 return;964 }965 966 dtd = &generic_dtd->dtd[panel->vbt.panel_type];967 968 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);969 if (!panel_fixed_mode)970 return;971 972 panel_fixed_mode->hdisplay = dtd->hactive;973 panel_fixed_mode->hsync_start =974 panel_fixed_mode->hdisplay + dtd->hfront_porch;975 panel_fixed_mode->hsync_end =976 panel_fixed_mode->hsync_start + dtd->hsync;977 panel_fixed_mode->htotal =978 panel_fixed_mode->hdisplay + dtd->hblank;979 980 panel_fixed_mode->vdisplay = dtd->vactive;981 panel_fixed_mode->vsync_start =982 panel_fixed_mode->vdisplay + dtd->vfront_porch;983 panel_fixed_mode->vsync_end =984 panel_fixed_mode->vsync_start + dtd->vsync;985 panel_fixed_mode->vtotal =986 panel_fixed_mode->vdisplay + dtd->vblank;987 988 panel_fixed_mode->clock = dtd->pixel_clock;989 panel_fixed_mode->width_mm = dtd->width_mm;990 panel_fixed_mode->height_mm = dtd->height_mm;991 992 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;993 drm_mode_set_name(panel_fixed_mode);994 995 if (dtd->hsync_positive_polarity)996 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;997 else998 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;999 1000 if (dtd->vsync_positive_polarity)1001 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;1002 else1003 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;1004 1005 drm_dbg_kms(display->drm,1006 "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n",1007 DRM_MODE_ARG(panel_fixed_mode));1008 1009 panel->vbt.lfp_vbt_mode = panel_fixed_mode;1010}1011 1012static void1013parse_lfp_backlight(struct intel_display *display,1014 struct intel_panel *panel)1015{1016 const struct bdb_lfp_backlight *backlight_data;1017 const struct lfp_backlight_data_entry *entry;1018 int panel_type = panel->vbt.panel_type;1019 u16 level;1020 1021 backlight_data = bdb_find_section(display, BDB_LFP_BACKLIGHT);1022 if (!backlight_data)1023 return;1024 1025 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {1026 drm_dbg_kms(display->drm,1027 "Unsupported backlight data entry size %u\n",1028 backlight_data->entry_size);1029 return;1030 }1031 1032 entry = &backlight_data->data[panel_type];1033 1034 panel->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;1035 if (!panel->vbt.backlight.present) {1036 drm_dbg_kms(display->drm,1037 "PWM backlight not present in VBT (type %u)\n",1038 entry->type);1039 return;1040 }1041 1042 panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;1043 panel->vbt.backlight.controller = 0;1044 if (display->vbt.version >= 191) {1045 const struct lfp_backlight_control_method *method;1046 1047 method = &backlight_data->backlight_control[panel_type];1048 panel->vbt.backlight.type = method->type;1049 panel->vbt.backlight.controller = method->controller;1050 }1051 1052 panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;1053 panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;1054 1055 if (display->vbt.version >= 234) {1056 u16 min_level;1057 bool scale;1058 1059 level = backlight_data->brightness_level[panel_type].level;1060 min_level = backlight_data->brightness_min_level[panel_type].level;1061 1062 if (display->vbt.version >= 236)1063 scale = backlight_data->brightness_precision_bits[panel_type] == 16;1064 else1065 scale = level > 255;1066 1067 if (scale)1068 min_level = min_level / 255;1069 1070 if (min_level > 255) {1071 drm_warn(display->drm, "Brightness min level > 255\n");1072 level = 255;1073 }1074 panel->vbt.backlight.min_brightness = min_level;1075 1076 panel->vbt.backlight.brightness_precision_bits =1077 backlight_data->brightness_precision_bits[panel_type];1078 } else {1079 level = backlight_data->level[panel_type];1080 panel->vbt.backlight.min_brightness = entry->min_brightness;1081 }1082 1083 if (display->vbt.version >= 239)1084 panel->vbt.backlight.hdr_dpcd_refresh_timeout =1085 DIV_ROUND_UP(backlight_data->hdr_dpcd_refresh_timeout[panel_type], 100);1086 else1087 panel->vbt.backlight.hdr_dpcd_refresh_timeout = 30;1088 1089 drm_dbg_kms(display->drm,1090 "VBT backlight PWM modulation frequency %u Hz, "1091 "active %s, min brightness %u, level %u, controller %u\n",1092 panel->vbt.backlight.pwm_freq_hz,1093 panel->vbt.backlight.active_low_pwm ? "low" : "high",1094 panel->vbt.backlight.min_brightness,1095 level,1096 panel->vbt.backlight.controller);1097}1098 1099static void1100parse_sdvo_lvds_data(struct intel_display *display,1101 struct intel_panel *panel)1102{1103 const struct bdb_sdvo_lvds_dtd *dtd;1104 struct drm_display_mode *panel_fixed_mode;1105 int index;1106 1107 index = display->params.vbt_sdvo_panel_type;1108 if (index == -2) {1109 drm_dbg_kms(display->drm,1110 "Ignore SDVO LVDS mode from BIOS VBT tables.\n");1111 return;1112 }1113 1114 if (index == -1) {1115 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;1116 1117 sdvo_lvds_options = bdb_find_section(display, BDB_SDVO_LVDS_OPTIONS);1118 if (!sdvo_lvds_options)1119 return;1120 1121 index = sdvo_lvds_options->panel_type;1122 }1123 1124 dtd = bdb_find_section(display, BDB_SDVO_LVDS_DTD);1125 if (!dtd)1126 return;1127 1128 /*1129 * This should not happen, as long as the panel_type1130 * enumeration doesn't grow over 4 items. But if it does, it1131 * could lead to hard-to-detect bugs, so better double-check1132 * it here to be sure.1133 */1134 if (index >= ARRAY_SIZE(dtd->dtd)) {1135 drm_err(display->drm,1136 "index %d is larger than dtd->dtd[4] array\n",1137 index);1138 return;1139 }1140 1141 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);1142 if (!panel_fixed_mode)1143 return;1144 1145 fill_detail_timing_data(display, panel_fixed_mode, &dtd->dtd[index]);1146 1147 panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;1148 1149 drm_dbg_kms(display->drm,1150 "Found SDVO LVDS mode in BIOS VBT tables: " DRM_MODE_FMT "\n",1151 DRM_MODE_ARG(panel_fixed_mode));1152}1153 1154static int intel_bios_ssc_frequency(struct intel_display *display,1155 bool alternate)1156{1157 switch (DISPLAY_VER(display)) {1158 case 2:1159 return alternate ? 66667 : 48000;1160 case 3:1161 case 4:1162 return alternate ? 100000 : 96000;1163 default:1164 return alternate ? 100000 : 120000;1165 }1166}1167 1168static void1169parse_general_features(struct intel_display *display)1170{1171 struct drm_i915_private *i915 = to_i915(display->drm);1172 const struct bdb_general_features *general;1173 1174 general = bdb_find_section(display, BDB_GENERAL_FEATURES);1175 if (!general)1176 return;1177 1178 display->vbt.int_tv_support = general->int_tv_support;1179 /* int_crt_support can't be trusted on earlier platforms */1180 if (display->vbt.version >= 155 &&1181 (HAS_DDI(display) || IS_VALLEYVIEW(i915)))1182 display->vbt.int_crt_support = general->int_crt_support;1183 display->vbt.lvds_use_ssc = general->enable_ssc;1184 display->vbt.lvds_ssc_freq =1185 intel_bios_ssc_frequency(display, general->ssc_freq);1186 display->vbt.display_clock_mode = general->display_clock_mode;1187 display->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;1188 if (display->vbt.version >= 181) {1189 display->vbt.orientation = general->rotate_180 ?1190 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :1191 DRM_MODE_PANEL_ORIENTATION_NORMAL;1192 } else {1193 display->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;1194 }1195 1196 if (display->vbt.version >= 249 && general->afc_startup_config) {1197 display->vbt.override_afc_startup = true;1198 display->vbt.override_afc_startup_val = general->afc_startup_config == 1 ? 0 : 7;1199 }1200 1201 drm_dbg_kms(display->drm,1202 "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",1203 display->vbt.int_tv_support,1204 display->vbt.int_crt_support,1205 display->vbt.lvds_use_ssc,1206 display->vbt.lvds_ssc_freq,1207 display->vbt.display_clock_mode,1208 display->vbt.fdi_rx_polarity_inverted);1209}1210 1211static const struct child_device_config *1212child_device_ptr(const struct bdb_general_definitions *defs, int i)1213{1214 return (const void *) &defs->devices[i * defs->child_dev_size];1215}1216 1217static void1218parse_sdvo_device_mapping(struct intel_display *display)1219{1220 const struct intel_bios_encoder_data *devdata;1221 int count = 0;1222 1223 /*1224 * Only parse SDVO mappings on gens that could have SDVO. This isn't1225 * accurate and doesn't have to be, as long as it's not too strict.1226 */1227 if (!IS_DISPLAY_VER(display, 3, 7)) {1228 drm_dbg_kms(display->drm, "Skipping SDVO device mapping\n");1229 return;1230 }1231 1232 list_for_each_entry(devdata, &display->vbt.display_devices, node) {1233 const struct child_device_config *child = &devdata->child;1234 struct sdvo_device_mapping *mapping;1235 1236 if (child->target_addr != TARGET_ADDR1 &&1237 child->target_addr != TARGET_ADDR2) {1238 /*1239 * If the target address is neither 0x70 nor 0x72,1240 * it is not a SDVO device. Skip it.1241 */1242 continue;1243 }1244 if (child->dvo_port != DEVICE_PORT_DVOB &&1245 child->dvo_port != DEVICE_PORT_DVOC) {1246 /* skip the incorrect SDVO port */1247 drm_dbg_kms(display->drm,1248 "Incorrect SDVO port. Skip it\n");1249 continue;1250 }1251 drm_dbg_kms(display->drm,1252 "the SDVO device with target addr %2x is found on"1253 " %s port\n",1254 child->target_addr,1255 (child->dvo_port == DEVICE_PORT_DVOB) ?1256 "SDVOB" : "SDVOC");1257 mapping = &display->vbt.sdvo_mappings[child->dvo_port - 1];1258 if (!mapping->initialized) {1259 mapping->dvo_port = child->dvo_port;1260 mapping->target_addr = child->target_addr;1261 mapping->dvo_wiring = child->dvo_wiring;1262 mapping->ddc_pin = child->ddc_pin;1263 mapping->i2c_pin = child->i2c_pin;1264 mapping->initialized = 1;1265 drm_dbg_kms(display->drm,1266 "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",1267 mapping->dvo_port, mapping->target_addr,1268 mapping->dvo_wiring, mapping->ddc_pin,1269 mapping->i2c_pin);1270 } else {1271 drm_dbg_kms(display->drm,1272 "Maybe one SDVO port is shared by "1273 "two SDVO device.\n");1274 }1275 if (child->target2_addr) {1276 /* Maybe this is a SDVO device with multiple inputs */1277 /* And the mapping info is not added */1278 drm_dbg_kms(display->drm,1279 "there exists the target2_addr. Maybe this"1280 " is a SDVO device with multiple inputs.\n");1281 }1282 count++;1283 }1284 1285 if (!count) {1286 /* No SDVO device info is found */1287 drm_dbg_kms(display->drm,1288 "No SDVO device info is found in VBT\n");1289 }1290}1291 1292static void1293parse_driver_features(struct intel_display *display)1294{1295 const struct bdb_driver_features *driver;1296 1297 driver = bdb_find_section(display, BDB_DRIVER_FEATURES);1298 if (!driver)1299 return;1300 1301 if (DISPLAY_VER(display) >= 5) {1302 /*1303 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS1304 * to mean "eDP". The VBT spec doesn't agree with that1305 * interpretation, but real world VBTs seem to.1306 */1307 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)1308 display->vbt.int_lvds_support = 0;1309 } else {1310 /*1311 * FIXME it's not clear which BDB version has the LVDS config1312 * bits defined. Revision history in the VBT spec says:1313 * "0.92 | Add two definitions for VBT value of LVDS Active1314 * Config (00b and 11b values defined) | 06/13/2005"1315 * but does not the specify the BDB version.1316 *1317 * So far version 134 (on i945gm) is the oldest VBT observed1318 * in the wild with the bits correctly populated. Version1319 * 108 (on i85x) does not have the bits correctly populated.1320 */1321 if (display->vbt.version >= 134 &&1322 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&1323 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)1324 display->vbt.int_lvds_support = 0;1325 }1326}1327 1328static void1329parse_panel_driver_features(struct intel_display *display,1330 struct intel_panel *panel)1331{1332 const struct bdb_driver_features *driver;1333 1334 driver = bdb_find_section(display, BDB_DRIVER_FEATURES);1335 if (!driver)1336 return;1337 1338 if (display->vbt.version < 228) {1339 drm_dbg_kms(display->drm, "DRRS State Enabled:%d\n",1340 driver->drrs_enabled);1341 /*1342 * If DRRS is not supported, drrs_type has to be set to 0.1343 * This is because, VBT is configured in such a way that1344 * static DRRS is 0 and DRRS not supported is represented by1345 * driver->drrs_enabled=false1346 */1347 if (!driver->drrs_enabled && panel->vbt.drrs_type != DRRS_TYPE_NONE) {1348 /*1349 * FIXME Should DMRRS perhaps be treated as seamless1350 * but without the automatic downclocking?1351 */1352 if (driver->dmrrs_enabled)1353 panel->vbt.drrs_type = DRRS_TYPE_STATIC;1354 else1355 panel->vbt.drrs_type = DRRS_TYPE_NONE;1356 }1357 1358 panel->vbt.psr.enable = driver->psr_enabled;1359 }1360}1361 1362static void1363parse_power_conservation_features(struct intel_display *display,1364 struct intel_panel *panel)1365{1366 const struct bdb_lfp_power *power;1367 u8 panel_type = panel->vbt.panel_type;1368 1369 panel->vbt.vrr = true; /* matches Windows behaviour */1370 1371 if (display->vbt.version < 228)1372 return;1373 1374 power = bdb_find_section(display, BDB_LFP_POWER);1375 if (!power)1376 return;1377 1378 panel->vbt.psr.enable = panel_bool(power->psr, panel_type);1379 1380 /*1381 * If DRRS is not supported, drrs_type has to be set to 0.1382 * This is because, VBT is configured in such a way that1383 * static DRRS is 0 and DRRS not supported is represented by1384 * power->drrs & BIT(panel_type)=false1385 */1386 if (!panel_bool(power->drrs, panel_type) && panel->vbt.drrs_type != DRRS_TYPE_NONE) {1387 /*1388 * FIXME Should DMRRS perhaps be treated as seamless1389 * but without the automatic downclocking?1390 */1391 if (panel_bool(power->dmrrs, panel_type))1392 panel->vbt.drrs_type = DRRS_TYPE_STATIC;1393 else1394 panel->vbt.drrs_type = DRRS_TYPE_NONE;1395 }1396 1397 if (display->vbt.version >= 232)1398 panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type);1399 1400 if (display->vbt.version >= 233)1401 panel->vbt.vrr = panel_bool(power->vrr_feature_enabled,1402 panel_type);1403}1404 1405static void1406parse_edp(struct intel_display *display,1407 struct intel_panel *panel)1408{1409 const struct bdb_edp *edp;1410 const struct edp_power_seq *edp_pps;1411 const struct edp_fast_link_params *edp_link_params;1412 int panel_type = panel->vbt.panel_type;1413 1414 edp = bdb_find_section(display, BDB_EDP);1415 if (!edp)1416 return;1417 1418 switch (panel_bits(edp->color_depth, panel_type, 2)) {1419 case EDP_18BPP:1420 panel->vbt.edp.bpp = 18;1421 break;1422 case EDP_24BPP:1423 panel->vbt.edp.bpp = 24;1424 break;1425 case EDP_30BPP:1426 panel->vbt.edp.bpp = 30;1427 break;1428 }1429 1430 /* Get the eDP sequencing and link info */1431 edp_pps = &edp->power_seqs[panel_type];1432 edp_link_params = &edp->fast_link_params[panel_type];1433 1434 panel->vbt.edp.pps = *edp_pps;1435 1436 if (display->vbt.version >= 224) {1437 panel->vbt.edp.rate =1438 edp->edp_fast_link_training_rate[panel_type] * 20;1439 } else {1440 switch (edp_link_params->rate) {1441 case EDP_RATE_1_62:1442 panel->vbt.edp.rate = 162000;1443 break;1444 case EDP_RATE_2_7:1445 panel->vbt.edp.rate = 270000;1446 break;1447 case EDP_RATE_5_4:1448 panel->vbt.edp.rate = 540000;1449 break;1450 default:1451 drm_dbg_kms(display->drm,1452 "VBT has unknown eDP link rate value %u\n",1453 edp_link_params->rate);1454 break;1455 }1456 }1457 1458 switch (edp_link_params->lanes) {1459 case EDP_LANE_1:1460 panel->vbt.edp.lanes = 1;1461 break;1462 case EDP_LANE_2:1463 panel->vbt.edp.lanes = 2;1464 break;1465 case EDP_LANE_4:1466 panel->vbt.edp.lanes = 4;1467 break;1468 default:1469 drm_dbg_kms(display->drm,1470 "VBT has unknown eDP lane count value %u\n",1471 edp_link_params->lanes);1472 break;1473 }1474 1475 switch (edp_link_params->preemphasis) {1476 case EDP_PREEMPHASIS_NONE:1477 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;1478 break;1479 case EDP_PREEMPHASIS_3_5dB:1480 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;1481 break;1482 case EDP_PREEMPHASIS_6dB:1483 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;1484 break;1485 case EDP_PREEMPHASIS_9_5dB:1486 panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;1487 break;1488 default:1489 drm_dbg_kms(display->drm,1490 "VBT has unknown eDP pre-emphasis value %u\n",1491 edp_link_params->preemphasis);1492 break;1493 }1494 1495 switch (edp_link_params->vswing) {1496 case EDP_VSWING_0_4V:1497 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;1498 break;1499 case EDP_VSWING_0_6V:1500 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;1501 break;1502 case EDP_VSWING_0_8V:1503 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;1504 break;1505 case EDP_VSWING_1_2V:1506 panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;1507 break;1508 default:1509 drm_dbg_kms(display->drm,1510 "VBT has unknown eDP voltage swing value %u\n",1511 edp_link_params->vswing);1512 break;1513 }1514 1515 if (display->vbt.version >= 173) {1516 u8 vswing;1517 1518 /* Don't read from VBT if module parameter has valid value*/1519 if (display->params.edp_vswing) {1520 panel->vbt.edp.low_vswing =1521 display->params.edp_vswing == 1;1522 } else {1523 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;1524 panel->vbt.edp.low_vswing = vswing == 0;1525 }1526 }1527 1528 panel->vbt.edp.drrs_msa_timing_delay =1529 panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2);1530 1531 if (display->vbt.version >= 244)1532 panel->vbt.edp.max_link_rate =1533 edp->edp_max_port_link_rate[panel_type] * 20;1534 1535 if (display->vbt.version >= 251)1536 panel->vbt.edp.dsc_disable =1537 panel_bool(edp->edp_dsc_disable, panel_type);1538}1539 1540static void1541parse_psr(struct intel_display *display,1542 struct intel_panel *panel)1543{1544 struct drm_i915_private *i915 = to_i915(display->drm);1545 const struct bdb_psr *psr;1546 const struct psr_table *psr_table;1547 int panel_type = panel->vbt.panel_type;1548 1549 psr = bdb_find_section(display, BDB_PSR);1550 if (!psr) {1551 drm_dbg_kms(display->drm, "No PSR BDB found.\n");1552 return;1553 }1554 1555 psr_table = &psr->psr_table[panel_type];1556 1557 panel->vbt.psr.full_link = psr_table->full_link;1558 panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;1559 1560 /* Allowed VBT values goes from 0 to 15 */1561 panel->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :1562 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;1563 1564 /*1565 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us1566 * Old decimal value is wake up time in multiples of 100 us.1567 */1568 if (display->vbt.version >= 205 &&1569 (DISPLAY_VER(display) >= 9 && !IS_BROXTON(i915))) {1570 switch (psr_table->tp1_wakeup_time) {1571 case 0:1572 panel->vbt.psr.tp1_wakeup_time_us = 500;1573 break;1574 case 1:1575 panel->vbt.psr.tp1_wakeup_time_us = 100;1576 break;1577 case 3:1578 panel->vbt.psr.tp1_wakeup_time_us = 0;1579 break;1580 default:1581 drm_dbg_kms(display->drm,1582 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",1583 psr_table->tp1_wakeup_time);1584 fallthrough;1585 case 2:1586 panel->vbt.psr.tp1_wakeup_time_us = 2500;1587 break;1588 }1589 1590 switch (psr_table->tp2_tp3_wakeup_time) {1591 case 0:1592 panel->vbt.psr.tp2_tp3_wakeup_time_us = 500;1593 break;1594 case 1:1595 panel->vbt.psr.tp2_tp3_wakeup_time_us = 100;1596 break;1597 case 3:1598 panel->vbt.psr.tp2_tp3_wakeup_time_us = 0;1599 break;1600 default:1601 drm_dbg_kms(display->drm,1602 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",1603 psr_table->tp2_tp3_wakeup_time);1604 fallthrough;1605 case 2:1606 panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500;1607 break;1608 }1609 } else {1610 panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;1611 panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;1612 }1613 1614 if (display->vbt.version >= 226) {1615 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;1616 1617 wakeup_time = panel_bits(wakeup_time, panel_type, 2);1618 switch (wakeup_time) {1619 case 0:1620 wakeup_time = 500;1621 break;1622 case 1:1623 wakeup_time = 100;1624 break;1625 case 3:1626 wakeup_time = 50;1627 break;1628 default:1629 case 2:1630 wakeup_time = 2500;1631 break;1632 }1633 panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;1634 } else {1635 /* Reusing PSR1 wakeup time for PSR2 in older VBTs */1636 panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us;1637 }1638}1639 1640static void parse_dsi_backlight_ports(struct intel_display *display,1641 struct intel_panel *panel,1642 enum port port)1643{1644 enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C;1645 1646 if (!panel->vbt.dsi.config->dual_link || display->vbt.version < 197) {1647 panel->vbt.dsi.bl_ports = BIT(port);1648 if (panel->vbt.dsi.config->cabc_supported)1649 panel->vbt.dsi.cabc_ports = BIT(port);1650 1651 return;1652 }1653 1654 switch (panel->vbt.dsi.config->dl_dcs_backlight_ports) {1655 case DL_DCS_PORT_A:1656 panel->vbt.dsi.bl_ports = BIT(PORT_A);1657 break;1658 case DL_DCS_PORT_C:1659 panel->vbt.dsi.bl_ports = BIT(port_bc);1660 break;1661 default:1662 case DL_DCS_PORT_A_AND_C:1663 panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc);1664 break;1665 }1666 1667 if (!panel->vbt.dsi.config->cabc_supported)1668 return;1669 1670 switch (panel->vbt.dsi.config->dl_dcs_cabc_ports) {1671 case DL_DCS_PORT_A:1672 panel->vbt.dsi.cabc_ports = BIT(PORT_A);1673 break;1674 case DL_DCS_PORT_C:1675 panel->vbt.dsi.cabc_ports = BIT(port_bc);1676 break;1677 default:1678 case DL_DCS_PORT_A_AND_C:1679 panel->vbt.dsi.cabc_ports =1680 BIT(PORT_A) | BIT(port_bc);1681 break;1682 }1683}1684 1685static void1686parse_mipi_config(struct intel_display *display,1687 struct intel_panel *panel)1688{1689 const struct bdb_mipi_config *start;1690 const struct mipi_config *config;1691 const struct mipi_pps_data *pps;1692 int panel_type = panel->vbt.panel_type;1693 enum port port;1694 1695 /* parse MIPI blocks only if LFP type is MIPI */1696 if (!intel_bios_is_dsi_present(display, &port))1697 return;1698 1699 /* Initialize this to undefined indicating no generic MIPI support */1700 panel->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;1701 1702 start = bdb_find_section(display, BDB_MIPI_CONFIG);1703 if (!start) {1704 drm_dbg_kms(display->drm, "No MIPI config BDB found");1705 return;1706 }1707 1708 drm_dbg(display->drm, "Found MIPI Config block, panel index = %d\n",1709 panel_type);1710 1711 /*1712 * get hold of the correct configuration block and pps data as per1713 * the panel_type as index1714 */1715 config = &start->config[panel_type];1716 pps = &start->pps[panel_type];1717 1718 /* store as of now full data. Trim when we realise all is not needed */1719 panel->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);1720 if (!panel->vbt.dsi.config)1721 return;1722 1723 panel->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);1724 if (!panel->vbt.dsi.pps) {1725 kfree(panel->vbt.dsi.config);1726 return;1727 }1728 1729 parse_dsi_backlight_ports(display, panel, port);1730 1731 /* FIXME is the 90 vs. 270 correct? */1732 switch (config->rotation) {1733 case ENABLE_ROTATION_0:1734 /*1735 * Most (all?) VBTs claim 0 degrees despite having1736 * an upside down panel, thus we do not trust this.1737 */1738 panel->vbt.dsi.orientation =1739 DRM_MODE_PANEL_ORIENTATION_UNKNOWN;1740 break;1741 case ENABLE_ROTATION_90:1742 panel->vbt.dsi.orientation =1743 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;1744 break;1745 case ENABLE_ROTATION_180:1746 panel->vbt.dsi.orientation =1747 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;1748 break;1749 case ENABLE_ROTATION_270:1750 panel->vbt.dsi.orientation =1751 DRM_MODE_PANEL_ORIENTATION_LEFT_UP;1752 break;1753 }1754 1755 /* We have mandatory mipi config blocks. Initialize as generic panel */1756 panel->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;1757}1758 1759/* Find the sequence block and size for the given panel. */1760static const u8 *1761find_panel_sequence_block(struct intel_display *display,1762 const struct bdb_mipi_sequence *sequence,1763 u16 panel_id, u32 *seq_size)1764{1765 u32 total = get_blocksize(sequence);1766 const u8 *data = &sequence->data[0];1767 u8 current_id;1768 u32 current_size;1769 int header_size = sequence->version >= 3 ? 5 : 3;1770 int index = 0;1771 int i;1772 1773 /* skip new block size */1774 if (sequence->version >= 3)1775 data += 4;1776 1777 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {1778 if (index + header_size > total) {1779 drm_err(display->drm,1780 "Invalid sequence block (header)\n");1781 return NULL;1782 }1783 1784 current_id = *(data + index);1785 if (sequence->version >= 3)1786 current_size = *((const u32 *)(data + index + 1));1787 else1788 current_size = *((const u16 *)(data + index + 1));1789 1790 index += header_size;1791 1792 if (index + current_size > total) {1793 drm_err(display->drm, "Invalid sequence block\n");1794 return NULL;1795 }1796 1797 if (current_id == panel_id) {1798 *seq_size = current_size;1799 return data + index;1800 }1801 1802 index += current_size;1803 }1804 1805 drm_err(display->drm,1806 "Sequence block detected but no valid configuration\n");1807 1808 return NULL;1809}1810 1811static int goto_next_sequence(struct intel_display *display,1812 const u8 *data, int index, int total)1813{1814 u16 len;1815 1816 /* Skip Sequence Byte. */1817 for (index = index + 1; index < total; index += len) {1818 u8 operation_byte = *(data + index);1819 index++;1820 1821 switch (operation_byte) {1822 case MIPI_SEQ_ELEM_END:1823 return index;1824 case MIPI_SEQ_ELEM_SEND_PKT:1825 if (index + 4 > total)1826 return 0;1827 1828 len = *((const u16 *)(data + index + 2)) + 4;1829 break;1830 case MIPI_SEQ_ELEM_DELAY:1831 len = 4;1832 break;1833 case MIPI_SEQ_ELEM_GPIO:1834 len = 2;1835 break;1836 case MIPI_SEQ_ELEM_I2C:1837 if (index + 7 > total)1838 return 0;1839 len = *(data + index + 6) + 7;1840 break;1841 default:1842 drm_err(display->drm, "Unknown operation byte\n");1843 return 0;1844 }1845 }1846 1847 return 0;1848}1849 1850static int goto_next_sequence_v3(struct intel_display *display,1851 const u8 *data, int index, int total)1852{1853 int seq_end;1854 u16 len;1855 u32 size_of_sequence;1856 1857 /*1858 * Could skip sequence based on Size of Sequence alone, but also do some1859 * checking on the structure.1860 */1861 if (total < 5) {1862 drm_err(display->drm, "Too small sequence size\n");1863 return 0;1864 }1865 1866 /* Skip Sequence Byte. */1867 index++;1868 1869 /*1870 * Size of Sequence. Excludes the Sequence Byte and the size itself,1871 * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END1872 * byte.1873 */1874 size_of_sequence = *((const u32 *)(data + index));1875 index += 4;1876 1877 seq_end = index + size_of_sequence;1878 if (seq_end > total) {1879 drm_err(display->drm, "Invalid sequence size\n");1880 return 0;1881 }1882 1883 for (; index < total; index += len) {1884 u8 operation_byte = *(data + index);1885 index++;1886 1887 if (operation_byte == MIPI_SEQ_ELEM_END) {1888 if (index != seq_end) {1889 drm_err(display->drm,1890 "Invalid element structure\n");1891 return 0;1892 }1893 return index;1894 }1895 1896 len = *(data + index);1897 index++;1898 1899 /*1900 * FIXME: Would be nice to check elements like for v1/v2 in1901 * goto_next_sequence() above.1902 */1903 switch (operation_byte) {1904 case MIPI_SEQ_ELEM_SEND_PKT:1905 case MIPI_SEQ_ELEM_DELAY:1906 case MIPI_SEQ_ELEM_GPIO:1907 case MIPI_SEQ_ELEM_I2C:1908 case MIPI_SEQ_ELEM_SPI:1909 case MIPI_SEQ_ELEM_PMIC:1910 break;1911 default:1912 drm_err(display->drm, "Unknown operation byte %u\n",1913 operation_byte);1914 break;1915 }1916 }1917 1918 return 0;1919}1920 1921/*1922 * Get len of pre-fixed deassert fragment from a v1 init OTP sequence,1923 * skip all delay + gpio operands and stop at the first DSI packet op.1924 */1925static int get_init_otp_deassert_fragment_len(struct intel_display *display,1926 struct intel_panel *panel)1927{1928 const u8 *data = panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];1929 int index, len;1930 1931 if (drm_WARN_ON(display->drm,1932 !data || panel->vbt.dsi.seq_version != 1))1933 return 0;1934 1935 /* index = 1 to skip sequence byte */1936 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {1937 switch (data[index]) {1938 case MIPI_SEQ_ELEM_SEND_PKT:1939 return index == 1 ? 0 : index;1940 case MIPI_SEQ_ELEM_DELAY:1941 len = 5; /* 1 byte for operand + uint32 */1942 break;1943 case MIPI_SEQ_ELEM_GPIO:1944 len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */1945 break;1946 default:1947 return 0;1948 }1949 }1950 1951 return 0;1952}1953 1954/*1955 * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.1956 * The deassert must be done before calling intel_dsi_device_ready, so for1957 * these devices we split the init OTP sequence into a deassert sequence and1958 * the actual init OTP part.1959 */1960static void vlv_fixup_mipi_sequences(struct intel_display *display,1961 struct intel_panel *panel)1962{1963 u8 *init_otp;1964 int len;1965 1966 /* Limit this to v1 vid-mode sequences */1967 if (panel->vbt.dsi.config->is_cmd_mode ||1968 panel->vbt.dsi.seq_version != 1)1969 return;1970 1971 /* Only do this if there are otp and assert seqs and no deassert seq */1972 if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||1973 !panel->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||1974 panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])1975 return;1976 1977 /* The deassert-sequence ends at the first DSI packet */1978 len = get_init_otp_deassert_fragment_len(display, panel);1979 if (!len)1980 return;1981 1982 drm_dbg_kms(display->drm,1983 "Using init OTP fragment to deassert reset\n");1984 1985 /* Copy the fragment, update seq byte and terminate it */1986 init_otp = (u8 *)panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];1987 panel->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);1988 if (!panel->vbt.dsi.deassert_seq)1989 return;1990 panel->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;1991 panel->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;1992 /* Use the copy for deassert */1993 panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =1994 panel->vbt.dsi.deassert_seq;1995 /* Replace the last byte of the fragment with init OTP seq byte */1996 init_otp[len - 1] = MIPI_SEQ_INIT_OTP;1997 /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */1998 panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;1999}2000 2001/*2002 * Some machines (eg. Lenovo 82TQ) appear to have broken2003 * VBT sequences:2004 * - INIT_OTP is not present at all2005 * - what should be in INIT_OTP is in DISPLAY_ON2006 * - what should be in DISPLAY_ON is in BACKLIGHT_ON2007 * (along with the actual backlight stuff)2008 *2009 * To make those work we simply swap DISPLAY_ON and INIT_OTP.2010 *2011 * TODO: Do we need to limit this to specific machines,2012 * or examine the contents of the sequences to2013 * avoid false positives?2014 */2015static void icl_fixup_mipi_sequences(struct intel_display *display,2016 struct intel_panel *panel)2017{2018 if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] &&2019 panel->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]) {2020 drm_dbg_kms(display->drm,2021 "Broken VBT: Swapping INIT_OTP and DISPLAY_ON sequences\n");2022 2023 swap(panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP],2024 panel->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]);2025 }2026}2027 2028static void fixup_mipi_sequences(struct intel_display *display,2029 struct intel_panel *panel)2030{2031 struct drm_i915_private *i915 = to_i915(display->drm);2032 2033 if (DISPLAY_VER(display) >= 11)2034 icl_fixup_mipi_sequences(display, panel);2035 else if (IS_VALLEYVIEW(i915))2036 vlv_fixup_mipi_sequences(display, panel);2037}2038 2039static void2040parse_mipi_sequence(struct intel_display *display,2041 struct intel_panel *panel)2042{2043 int panel_type = panel->vbt.panel_type;2044 const struct bdb_mipi_sequence *sequence;2045 const u8 *seq_data;2046 u32 seq_size;2047 u8 *data;2048 int index = 0;2049 2050 /* Only our generic panel driver uses the sequence block. */2051 if (panel->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)2052 return;2053 2054 sequence = bdb_find_section(display, BDB_MIPI_SEQUENCE);2055 if (!sequence) {2056 drm_dbg_kms(display->drm,2057 "No MIPI Sequence found, parsing complete\n");2058 return;2059 }2060 2061 /* Fail gracefully for forward incompatible sequence block. */2062 if (sequence->version >= 4) {2063 drm_err(display->drm,2064 "Unable to parse MIPI Sequence Block v%u\n",2065 sequence->version);2066 return;2067 }2068 2069 drm_dbg(display->drm, "Found MIPI sequence block v%u\n",2070 sequence->version);2071 2072 seq_data = find_panel_sequence_block(display, sequence, panel_type, &seq_size);2073 if (!seq_data)2074 return;2075 2076 data = kmemdup(seq_data, seq_size, GFP_KERNEL);2077 if (!data)2078 return;2079 2080 /* Parse the sequences, store pointers to each sequence. */2081 for (;;) {2082 u8 seq_id = *(data + index);2083 if (seq_id == MIPI_SEQ_END)2084 break;2085 2086 if (seq_id >= MIPI_SEQ_MAX) {2087 drm_err(display->drm, "Unknown sequence %u\n",2088 seq_id);2089 goto err;2090 }2091 2092 /* Log about presence of sequences we won't run. */2093 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF)2094 drm_dbg_kms(display->drm,2095 "Unsupported sequence %u\n", seq_id);2096 2097 panel->vbt.dsi.sequence[seq_id] = data + index;2098 2099 if (sequence->version >= 3)2100 index = goto_next_sequence_v3(display, data, index, seq_size);2101 else2102 index = goto_next_sequence(display, data, index, seq_size);2103 if (!index) {2104 drm_err(display->drm, "Invalid sequence %u\n",2105 seq_id);2106 goto err;2107 }2108 }2109 2110 panel->vbt.dsi.data = data;2111 panel->vbt.dsi.size = seq_size;2112 panel->vbt.dsi.seq_version = sequence->version;2113 2114 fixup_mipi_sequences(display, panel);2115 2116 drm_dbg(display->drm, "MIPI related VBT parsing complete\n");2117 return;2118 2119err:2120 kfree(data);2121 memset(panel->vbt.dsi.sequence, 0, sizeof(panel->vbt.dsi.sequence));2122}2123 2124static void2125parse_compression_parameters(struct intel_display *display)2126{2127 const struct bdb_compression_parameters *params;2128 struct intel_bios_encoder_data *devdata;2129 u16 block_size;2130 int index;2131 2132 if (display->vbt.version < 198)2133 return;2134 2135 params = bdb_find_section(display, BDB_COMPRESSION_PARAMETERS);2136 if (params) {2137 /* Sanity checks */2138 if (params->entry_size != sizeof(params->data[0])) {2139 drm_dbg_kms(display->drm,2140 "VBT: unsupported compression param entry size\n");2141 return;2142 }2143 2144 block_size = get_blocksize(params);2145 if (block_size < sizeof(*params)) {2146 drm_dbg_kms(display->drm,2147 "VBT: expected 16 compression param entries\n");2148 return;2149 }2150 }2151 2152 list_for_each_entry(devdata, &display->vbt.display_devices, node) {2153 const struct child_device_config *child = &devdata->child;2154 2155 if (!child->compression_enable)2156 continue;2157 2158 if (!params) {2159 drm_dbg_kms(display->drm,2160 "VBT: compression params not available\n");2161 continue;2162 }2163 2164 if (child->compression_method_cps) {2165 drm_dbg_kms(display->drm,2166 "VBT: CPS compression not supported\n");2167 continue;2168 }2169 2170 index = child->compression_structure_index;2171 2172 devdata->dsc = kmemdup(¶ms->data[index],2173 sizeof(*devdata->dsc), GFP_KERNEL);2174 }2175}2176 2177static u8 translate_iboost(struct intel_display *display, u8 val)2178{2179 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */2180 2181 if (val >= ARRAY_SIZE(mapping)) {2182 drm_dbg_kms(display->drm,2183 "Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);2184 return 0;2185 }2186 return mapping[val];2187}2188 2189static const u8 cnp_ddc_pin_map[] = {2190 [0] = 0, /* N/A */2191 [GMBUS_PIN_1_BXT] = DDC_BUS_DDI_B,2192 [GMBUS_PIN_2_BXT] = DDC_BUS_DDI_C,2193 [GMBUS_PIN_4_CNP] = DDC_BUS_DDI_D, /* sic */2194 [GMBUS_PIN_3_BXT] = DDC_BUS_DDI_F, /* sic */2195};2196 2197static const u8 icp_ddc_pin_map[] = {2198 [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A,2199 [GMBUS_PIN_2_BXT] = ICL_DDC_BUS_DDI_B,2200 [GMBUS_PIN_3_BXT] = TGL_DDC_BUS_DDI_C,2201 [GMBUS_PIN_9_TC1_ICP] = ICL_DDC_BUS_PORT_1,2202 [GMBUS_PIN_10_TC2_ICP] = ICL_DDC_BUS_PORT_2,2203 [GMBUS_PIN_11_TC3_ICP] = ICL_DDC_BUS_PORT_3,2204 [GMBUS_PIN_12_TC4_ICP] = ICL_DDC_BUS_PORT_4,2205 [GMBUS_PIN_13_TC5_TGP] = TGL_DDC_BUS_PORT_5,2206 [GMBUS_PIN_14_TC6_TGP] = TGL_DDC_BUS_PORT_6,2207};2208 2209static const u8 rkl_pch_tgp_ddc_pin_map[] = {2210 [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A,2211 [GMBUS_PIN_2_BXT] = ICL_DDC_BUS_DDI_B,2212 [GMBUS_PIN_9_TC1_ICP] = RKL_DDC_BUS_DDI_D,2213 [GMBUS_PIN_10_TC2_ICP] = RKL_DDC_BUS_DDI_E,2214};2215 2216static const u8 adls_ddc_pin_map[] = {2217 [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A,2218 [GMBUS_PIN_9_TC1_ICP] = ADLS_DDC_BUS_PORT_TC1,2219 [GMBUS_PIN_10_TC2_ICP] = ADLS_DDC_BUS_PORT_TC2,2220 [GMBUS_PIN_11_TC3_ICP] = ADLS_DDC_BUS_PORT_TC3,2221 [GMBUS_PIN_12_TC4_ICP] = ADLS_DDC_BUS_PORT_TC4,2222};2223 2224static const u8 gen9bc_tgp_ddc_pin_map[] = {2225 [GMBUS_PIN_2_BXT] = DDC_BUS_DDI_B,2226 [GMBUS_PIN_9_TC1_ICP] = DDC_BUS_DDI_C,2227 [GMBUS_PIN_10_TC2_ICP] = DDC_BUS_DDI_D,2228};2229 2230static const u8 adlp_ddc_pin_map[] = {2231 [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A,2232 [GMBUS_PIN_2_BXT] = ICL_DDC_BUS_DDI_B,2233 [GMBUS_PIN_9_TC1_ICP] = ADLP_DDC_BUS_PORT_TC1,2234 [GMBUS_PIN_10_TC2_ICP] = ADLP_DDC_BUS_PORT_TC2,2235 [GMBUS_PIN_11_TC3_ICP] = ADLP_DDC_BUS_PORT_TC3,2236 [GMBUS_PIN_12_TC4_ICP] = ADLP_DDC_BUS_PORT_TC4,2237};2238 2239static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin)2240{2241 struct drm_i915_private *i915 = to_i915(display->drm);2242 const u8 *ddc_pin_map;2243 int i, n_entries;2244 2245 if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {2246 ddc_pin_map = adlp_ddc_pin_map;2247 n_entries = ARRAY_SIZE(adlp_ddc_pin_map);2248 } else if (IS_ALDERLAKE_S(i915)) {2249 ddc_pin_map = adls_ddc_pin_map;2250 n_entries = ARRAY_SIZE(adls_ddc_pin_map);2251 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {2252 return vbt_pin;2253 } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {2254 ddc_pin_map = rkl_pch_tgp_ddc_pin_map;2255 n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);2256 } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(display) == 9) {2257 ddc_pin_map = gen9bc_tgp_ddc_pin_map;2258 n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);2259 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {2260 ddc_pin_map = icp_ddc_pin_map;2261 n_entries = ARRAY_SIZE(icp_ddc_pin_map);2262 } else if (HAS_PCH_CNP(i915)) {2263 ddc_pin_map = cnp_ddc_pin_map;2264 n_entries = ARRAY_SIZE(cnp_ddc_pin_map);2265 } else {2266 /* Assuming direct map */2267 return vbt_pin;2268 }2269 2270 for (i = 0; i < n_entries; i++) {2271 if (ddc_pin_map[i] == vbt_pin)2272 return i;2273 }2274 2275 drm_dbg_kms(display->drm,2276 "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",2277 vbt_pin);2278 return 0;2279}2280 2281static u8 dvo_port_type(u8 dvo_port)2282{2283 switch (dvo_port) {2284 case DVO_PORT_HDMIA:2285 case DVO_PORT_HDMIB:2286 case DVO_PORT_HDMIC:2287 case DVO_PORT_HDMID:2288 case DVO_PORT_HDMIE:2289 case DVO_PORT_HDMIF:2290 case DVO_PORT_HDMIG:2291 case DVO_PORT_HDMIH:2292 case DVO_PORT_HDMII:2293 return DVO_PORT_HDMIA;2294 case DVO_PORT_DPA:2295 case DVO_PORT_DPB:2296 case DVO_PORT_DPC:2297 case DVO_PORT_DPD:2298 case DVO_PORT_DPE:2299 case DVO_PORT_DPF:2300 case DVO_PORT_DPG:2301 case DVO_PORT_DPH:2302 case DVO_PORT_DPI:2303 return DVO_PORT_DPA;2304 case DVO_PORT_MIPIA:2305 case DVO_PORT_MIPIB:2306 case DVO_PORT_MIPIC:2307 case DVO_PORT_MIPID:2308 return DVO_PORT_MIPIA;2309 default:2310 return dvo_port;2311 }2312}2313 2314static enum port __dvo_port_to_port(int n_ports, int n_dvo,2315 const int port_mapping[][3], u8 dvo_port)2316{2317 enum port port;2318 int i;2319 2320 for (port = PORT_A; port < n_ports; port++) {2321 for (i = 0; i < n_dvo; i++) {2322 if (port_mapping[port][i] == -1)2323 break;2324 2325 if (dvo_port == port_mapping[port][i])2326 return port;2327 }2328 }2329 2330 return PORT_NONE;2331}2332 2333static enum port dvo_port_to_port(struct intel_display *display,2334 u8 dvo_port)2335{2336 struct drm_i915_private *i915 = to_i915(display->drm);2337 /*2338 * Each DDI port can have more than one value on the "DVO Port" field,2339 * so look for all the possible values for each port.2340 */2341 static const int port_mapping[][3] = {2342 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },2343 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },2344 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },2345 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },2346 [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },2347 [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },2348 [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },2349 [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },2350 [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },2351 };2352 /*2353 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D2354 * map to DDI A,B,TC1,TC2 respectively.2355 */2356 static const int rkl_port_mapping[][3] = {2357 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },2358 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },2359 [PORT_C] = { -1 },2360 [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },2361 [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },2362 };2363 /*2364 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,2365 * PORT_F and PORT_G, we need to map that to correct VBT sections.2366 */2367 static const int adls_port_mapping[][3] = {2368 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },2369 [PORT_B] = { -1 },2370 [PORT_C] = { -1 },2371 [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },2372 [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },2373 [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },2374 [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },2375 };2376 static const int xelpd_port_mapping[][3] = {2377 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },2378 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },2379 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },2380 [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },2381 [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },2382 [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },2383 [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },2384 [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },2385 [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },2386 };2387 2388 if (DISPLAY_VER(display) >= 13)2389 return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),2390 ARRAY_SIZE(xelpd_port_mapping[0]),2391 xelpd_port_mapping,2392 dvo_port);2393 else if (IS_ALDERLAKE_S(i915))2394 return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),2395 ARRAY_SIZE(adls_port_mapping[0]),2396 adls_port_mapping,2397 dvo_port);2398 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))2399 return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),2400 ARRAY_SIZE(rkl_port_mapping[0]),2401 rkl_port_mapping,2402 dvo_port);2403 else2404 return __dvo_port_to_port(ARRAY_SIZE(port_mapping),2405 ARRAY_SIZE(port_mapping[0]),2406 port_mapping,2407 dvo_port);2408}2409 2410static enum port2411dsi_dvo_port_to_port(struct intel_display *display, u8 dvo_port)2412{2413 switch (dvo_port) {2414 case DVO_PORT_MIPIA:2415 return PORT_A;2416 case DVO_PORT_MIPIC:2417 if (DISPLAY_VER(display) >= 11)2418 return PORT_B;2419 else2420 return PORT_C;2421 default:2422 return PORT_NONE;2423 }2424}2425 2426enum port intel_bios_encoder_port(const struct intel_bios_encoder_data *devdata)2427{2428 struct intel_display *display = devdata->display;2429 const struct child_device_config *child = &devdata->child;2430 enum port port;2431 2432 port = dvo_port_to_port(display, child->dvo_port);2433 if (port == PORT_NONE && DISPLAY_VER(display) >= 11)2434 port = dsi_dvo_port_to_port(display, child->dvo_port);2435 2436 return port;2437}2438 2439static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate)2440{2441 switch (vbt_max_link_rate) {2442 default:2443 case BDB_230_VBT_DP_MAX_LINK_RATE_DEF:2444 return 0;2445 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20:2446 return 2000000;2447 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5:2448 return 1350000;2449 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10:2450 return 1000000;2451 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR3:2452 return 810000;2453 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR2:2454 return 540000;2455 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR:2456 return 270000;2457 case BDB_230_VBT_DP_MAX_LINK_RATE_LBR:2458 return 162000;2459 }2460}2461 2462static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate)2463{2464 switch (vbt_max_link_rate) {2465 default:2466 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR3:2467 return 810000;2468 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR2:2469 return 540000;2470 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR:2471 return 270000;2472 case BDB_216_VBT_DP_MAX_LINK_RATE_LBR:2473 return 162000;2474 }2475}2476 2477int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata)2478{2479 if (!devdata || devdata->display->vbt.version < 216)2480 return 0;2481 2482 if (devdata->display->vbt.version >= 230)2483 return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate);2484 else2485 return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);2486}2487 2488int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata)2489{2490 if (!devdata || devdata->display->vbt.version < 244)2491 return 0;2492 2493 return devdata->child.dp_max_lane_count + 1;2494}2495 2496static void sanitize_device_type(struct intel_bios_encoder_data *devdata,2497 enum port port)2498{2499 struct intel_display *display = devdata->display;2500 bool is_hdmi;2501 2502 if (port != PORT_A || DISPLAY_VER(display) >= 12)2503 return;2504 2505 if (!intel_bios_encoder_supports_dvi(devdata))2506 return;2507 2508 is_hdmi = intel_bios_encoder_supports_hdmi(devdata);2509 2510 drm_dbg_kms(display->drm, "VBT claims port A supports DVI%s, ignoring\n",2511 is_hdmi ? "/HDMI" : "");2512 2513 devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;2514 devdata->child.device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;2515}2516 2517static void sanitize_hdmi_level_shift(struct intel_bios_encoder_data *devdata,2518 enum port port)2519{2520 struct intel_display *display = devdata->display;2521 struct drm_i915_private *i915 = to_i915(display->drm);2522 2523 if (!intel_bios_encoder_supports_dvi(devdata))2524 return;2525 2526 /*2527 * Some BDW machines (eg. HP Pavilion 15-ab) shipped2528 * with a HSW VBT where the level shifter value goes2529 * up to 11, whereas the BDW max is 9.2530 */2531 if (IS_BROADWELL(i915) && devdata->child.hdmi_level_shifter_value > 9) {2532 drm_dbg_kms(display->drm,2533 "Bogus port %c VBT HDMI level shift %d, adjusting to %d\n",2534 port_name(port), devdata->child.hdmi_level_shifter_value, 9);2535 2536 devdata->child.hdmi_level_shifter_value = 9;2537 }2538}2539 2540static bool2541intel_bios_encoder_supports_crt(const struct intel_bios_encoder_data *devdata)2542{2543 return devdata->child.device_type & DEVICE_TYPE_ANALOG_OUTPUT;2544}2545 2546bool2547intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata)2548{2549 return devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;2550}2551 2552bool2553intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata)2554{2555 return intel_bios_encoder_supports_dvi(devdata) &&2556 (devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;2557}2558 2559bool2560intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata)2561{2562 return devdata->child.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;2563}2564 2565bool2566intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)2567{2568 return intel_bios_encoder_supports_dp(devdata) &&2569 devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;2570}2571 2572bool2573intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata)2574{2575 return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;2576}2577 2578bool2579intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata)2580{2581 return devdata && HAS_LSPCON(devdata->display) && devdata->child.lspcon;2582}2583 2584/* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */2585int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata)2586{2587 if (!devdata || devdata->display->vbt.version < 158 ||2588 DISPLAY_VER(devdata->display) >= 14)2589 return -1;2590 2591 return devdata->child.hdmi_level_shifter_value;2592}2593 2594int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata)2595{2596 if (!devdata || devdata->display->vbt.version < 204)2597 return 0;2598 2599 switch (devdata->child.hdmi_max_data_rate) {2600 default:2601 MISSING_CASE(devdata->child.hdmi_max_data_rate);2602 fallthrough;2603 case HDMI_MAX_DATA_RATE_PLATFORM:2604 return 0;2605 case HDMI_MAX_DATA_RATE_594:2606 return 594000;2607 case HDMI_MAX_DATA_RATE_340:2608 return 340000;2609 case HDMI_MAX_DATA_RATE_300:2610 return 300000;2611 case HDMI_MAX_DATA_RATE_297:2612 return 297000;2613 case HDMI_MAX_DATA_RATE_165:2614 return 165000;2615 }2616}2617 2618static bool is_port_valid(struct intel_display *display, enum port port)2619{2620 struct drm_i915_private *i915 = to_i915(display->drm);2621 /*2622 * On some ICL SKUs port F is not present, but broken VBTs mark2623 * the port as present. Only try to initialize port F for the2624 * SKUs that may actually have it.2625 */2626 if (port == PORT_F && IS_ICELAKE(i915))2627 return IS_ICL_WITH_PORT_F(i915);2628 2629 return true;2630}2631 2632static void print_ddi_port(const struct intel_bios_encoder_data *devdata)2633{2634 struct intel_display *display = devdata->display;2635 const struct child_device_config *child = &devdata->child;2636 bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt;2637 int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;2638 enum port port;2639 2640 port = intel_bios_encoder_port(devdata);2641 if (port == PORT_NONE)2642 return;2643 2644 is_dvi = intel_bios_encoder_supports_dvi(devdata);2645 is_dp = intel_bios_encoder_supports_dp(devdata);2646 is_crt = intel_bios_encoder_supports_crt(devdata);2647 is_hdmi = intel_bios_encoder_supports_hdmi(devdata);2648 is_edp = intel_bios_encoder_supports_edp(devdata);2649 is_dsi = intel_bios_encoder_supports_dsi(devdata);2650 2651 supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata);2652 supports_tbt = intel_bios_encoder_supports_tbt(devdata);2653 2654 drm_dbg_kms(display->drm,2655 "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d DSI:%d DP++:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",2656 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, is_dsi,2657 intel_bios_encoder_supports_dp_dual_mode(devdata),2658 intel_bios_encoder_is_lspcon(devdata),2659 supports_typec_usb, supports_tbt,2660 devdata->dsc != NULL);2661 2662 hdmi_level_shift = intel_bios_hdmi_level_shift(devdata);2663 if (hdmi_level_shift >= 0) {2664 drm_dbg_kms(display->drm,2665 "Port %c VBT HDMI level shift: %d\n",2666 port_name(port), hdmi_level_shift);2667 }2668 2669 max_tmds_clock = intel_bios_hdmi_max_tmds_clock(devdata);2670 if (max_tmds_clock)2671 drm_dbg_kms(display->drm,2672 "Port %c VBT HDMI max TMDS clock: %d kHz\n",2673 port_name(port), max_tmds_clock);2674 2675 /* I_boost config for SKL and above */2676 dp_boost_level = intel_bios_dp_boost_level(devdata);2677 if (dp_boost_level)2678 drm_dbg_kms(display->drm,2679 "Port %c VBT (e)DP boost level: %d\n",2680 port_name(port), dp_boost_level);2681 2682 hdmi_boost_level = intel_bios_hdmi_boost_level(devdata);2683 if (hdmi_boost_level)2684 drm_dbg_kms(display->drm,2685 "Port %c VBT HDMI boost level: %d\n",2686 port_name(port), hdmi_boost_level);2687 2688 dp_max_link_rate = intel_bios_dp_max_link_rate(devdata);2689 if (dp_max_link_rate)2690 drm_dbg_kms(display->drm,2691 "Port %c VBT DP max link rate: %d\n",2692 port_name(port), dp_max_link_rate);2693 2694 /*2695 * FIXME need to implement support for VBT2696 * vswing/preemph tables should this ever trigger.2697 */2698 drm_WARN(display->drm, child->use_vbt_vswing,2699 "Port %c asks to use VBT vswing/preemph tables\n",2700 port_name(port));2701}2702 2703static void parse_ddi_port(struct intel_bios_encoder_data *devdata)2704{2705 struct intel_display *display = devdata->display;2706 enum port port;2707 2708 port = intel_bios_encoder_port(devdata);2709 if (port == PORT_NONE)2710 return;2711 2712 if (!is_port_valid(display, port)) {2713 drm_dbg_kms(display->drm,2714 "VBT reports port %c as supported, but that can't be true: skipping\n",2715 port_name(port));2716 return;2717 }2718 2719 sanitize_device_type(devdata, port);2720 sanitize_hdmi_level_shift(devdata, port);2721}2722 2723static bool has_ddi_port_info(struct intel_display *display)2724{2725 struct drm_i915_private *i915 = to_i915(display->drm);2726 2727 return DISPLAY_VER(display) >= 5 || IS_G4X(i915);2728}2729 2730static void parse_ddi_ports(struct intel_display *display)2731{2732 struct intel_bios_encoder_data *devdata;2733 2734 if (!has_ddi_port_info(display))2735 return;2736 2737 list_for_each_entry(devdata, &display->vbt.display_devices, node)2738 parse_ddi_port(devdata);2739 2740 list_for_each_entry(devdata, &display->vbt.display_devices, node)2741 print_ddi_port(devdata);2742}2743 2744static int child_device_expected_size(u16 version)2745{2746 BUILD_BUG_ON(sizeof(struct child_device_config) < 40);2747 2748 if (version > 256)2749 return -ENOENT;2750 else if (version >= 256)2751 return 40;2752 else if (version >= 216)2753 return 39;2754 else if (version >= 196)2755 return 38;2756 else if (version >= 195)2757 return 37;2758 else if (version >= 111)2759 return LEGACY_CHILD_DEVICE_CONFIG_SIZE;2760 else if (version >= 106)2761 return 27;2762 else2763 return 22;2764}2765 2766static bool child_device_size_valid(struct intel_display *display, int size)2767{2768 int expected_size;2769 2770 expected_size = child_device_expected_size(display->vbt.version);2771 if (expected_size < 0) {2772 expected_size = sizeof(struct child_device_config);2773 drm_dbg(display->drm,2774 "Expected child device config size for VBT version %u not known; assuming %d\n",2775 display->vbt.version, expected_size);2776 }2777 2778 /* Flag an error for unexpected size, but continue anyway. */2779 if (size != expected_size)2780 drm_err(display->drm,2781 "Unexpected child device config size %d (expected %d for VBT version %u)\n",2782 size, expected_size, display->vbt.version);2783 2784 /* The legacy sized child device config is the minimum we need. */2785 if (size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {2786 drm_dbg_kms(display->drm,2787 "Child device config size %d is too small.\n",2788 size);2789 return false;2790 }2791 2792 return true;2793}2794 2795static void2796parse_general_definitions(struct intel_display *display)2797{2798 struct drm_i915_private *i915 = to_i915(display->drm);2799 const struct bdb_general_definitions *defs;2800 struct intel_bios_encoder_data *devdata;2801 const struct child_device_config *child;2802 int i, child_device_num;2803 u16 block_size;2804 int bus_pin;2805 2806 defs = bdb_find_section(display, BDB_GENERAL_DEFINITIONS);2807 if (!defs) {2808 drm_dbg_kms(display->drm,2809 "No general definition block is found, no devices defined.\n");2810 return;2811 }2812 2813 block_size = get_blocksize(defs);2814 if (block_size < sizeof(*defs)) {2815 drm_dbg_kms(display->drm,2816 "General definitions block too small (%u)\n",2817 block_size);2818 return;2819 }2820 2821 bus_pin = defs->crt_ddc_gmbus_pin;2822 drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);2823 if (intel_gmbus_is_valid_pin(i915, bus_pin))2824 display->vbt.crt_ddc_pin = bus_pin;2825 2826 if (!child_device_size_valid(display, defs->child_dev_size))2827 return;2828 2829 /* get the number of child device */2830 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;2831 2832 for (i = 0; i < child_device_num; i++) {2833 child = child_device_ptr(defs, i);2834 if (!child->device_type)2835 continue;2836 2837 drm_dbg_kms(display->drm,2838 "Found VBT child device with type 0x%x\n",2839 child->device_type);2840 2841 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL);2842 if (!devdata)2843 break;2844 2845 devdata->display = display;2846 2847 /*2848 * Copy as much as we know (sizeof) and is available2849 * (child_dev_size) of the child device config. Accessing the2850 * data must depend on VBT version.2851 */2852 memcpy(&devdata->child, child,2853 min_t(size_t, defs->child_dev_size, sizeof(*child)));2854 2855 list_add_tail(&devdata->node, &display->vbt.display_devices);2856 }2857 2858 if (list_empty(&display->vbt.display_devices))2859 drm_dbg_kms(display->drm,2860 "no child dev is parsed from VBT\n");2861}2862 2863/* Common defaults which may be overridden by VBT. */2864static void2865init_vbt_defaults(struct intel_display *display)2866{2867 struct drm_i915_private *i915 = to_i915(display->drm);2868 2869 display->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;2870 2871 /* general features */2872 display->vbt.int_tv_support = 1;2873 display->vbt.int_crt_support = 1;2874 2875 /* driver features */2876 display->vbt.int_lvds_support = 1;2877 2878 /* Default to using SSC */2879 display->vbt.lvds_use_ssc = 1;2880 /*2881 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference2882 * clock for LVDS.2883 */2884 display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display,2885 !HAS_PCH_SPLIT(i915));2886 drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n",2887 display->vbt.lvds_ssc_freq);2888}2889 2890/* Common defaults which may be overridden by VBT. */2891static void2892init_vbt_panel_defaults(struct intel_panel *panel)2893{2894 /* Default to having backlight */2895 panel->vbt.backlight.present = true;2896 2897 /* LFP panel data */2898 panel->vbt.lvds_dither = true;2899}2900 2901/* Defaults to initialize only if there is no VBT. */2902static void2903init_vbt_missing_defaults(struct intel_display *display)2904{2905 struct drm_i915_private *i915 = to_i915(display->drm);2906 unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask;2907 enum port port;2908 2909 if (!HAS_DDI(display) && !IS_CHERRYVIEW(i915))2910 return;2911 2912 for_each_port_masked(port, ports) {2913 struct intel_bios_encoder_data *devdata;2914 struct child_device_config *child;2915 enum phy phy = intel_port_to_phy(i915, port);2916 2917 /*2918 * VBT has the TypeC mode (native,TBT/USB) and we don't want2919 * to detect it.2920 */2921 if (intel_phy_is_tc(i915, phy))2922 continue;2923 2924 /* Create fake child device config */2925 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL);2926 if (!devdata)2927 break;2928 2929 devdata->display = display;2930 child = &devdata->child;2931 2932 if (port == PORT_F)2933 child->dvo_port = DVO_PORT_HDMIF;2934 else if (port == PORT_E)2935 child->dvo_port = DVO_PORT_HDMIE;2936 else2937 child->dvo_port = DVO_PORT_HDMIA + port;2938 2939 if (port != PORT_A && port != PORT_E)2940 child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING;2941 2942 if (port != PORT_E)2943 child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT;2944 2945 if (port == PORT_A)2946 child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR;2947 2948 list_add_tail(&devdata->node, &display->vbt.display_devices);2949 2950 drm_dbg_kms(display->drm,2951 "Generating default VBT child device with type 0x%04x on port %c\n",2952 child->device_type, port_name(port));2953 }2954 2955 /* Bypass some minimum baseline VBT version checks */2956 display->vbt.version = 155;2957}2958 2959static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)2960{2961 const void *_vbt = vbt;2962 2963 return _vbt + vbt->bdb_offset;2964}2965 2966/**2967 * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT2968 * @display: display device2969 * @buf: pointer to a buffer to validate2970 * @size: size of the buffer2971 *2972 * Returns true on valid VBT.2973 */2974bool intel_bios_is_valid_vbt(struct intel_display *display,2975 const void *buf, size_t size)2976{2977 const struct vbt_header *vbt = buf;2978 const struct bdb_header *bdb;2979 2980 if (!vbt)2981 return false;2982 2983 if (sizeof(struct vbt_header) > size) {2984 drm_dbg_kms(display->drm, "VBT header incomplete\n");2985 return false;2986 }2987 2988 if (memcmp(vbt->signature, "$VBT", 4)) {2989 drm_dbg_kms(display->drm, "VBT invalid signature\n");2990 return false;2991 }2992 2993 if (vbt->vbt_size > size) {2994 drm_dbg_kms(display->drm,2995 "VBT incomplete (vbt_size overflows)\n");2996 return false;2997 }2998 2999 size = vbt->vbt_size;3000 3001 if (range_overflows_t(size_t,3002 vbt->bdb_offset,3003 sizeof(struct bdb_header),3004 size)) {3005 drm_dbg_kms(display->drm, "BDB header incomplete\n");3006 return false;3007 }3008 3009 bdb = get_bdb_header(vbt);3010 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {3011 drm_dbg_kms(display->drm, "BDB incomplete\n");3012 return false;3013 }3014 3015 return vbt;3016}3017 3018static struct vbt_header *firmware_get_vbt(struct intel_display *display,3019 size_t *size)3020{3021 struct vbt_header *vbt = NULL;3022 const struct firmware *fw = NULL;3023 const char *name = display->params.vbt_firmware;3024 int ret;3025 3026 if (!name || !*name)3027 return NULL;3028 3029 ret = request_firmware(&fw, name, display->drm->dev);3030 if (ret) {3031 drm_err(display->drm,3032 "Requesting VBT firmware \"%s\" failed (%d)\n",3033 name, ret);3034 return NULL;3035 }3036 3037 if (intel_bios_is_valid_vbt(display, fw->data, fw->size)) {3038 vbt = kmemdup(fw->data, fw->size, GFP_KERNEL);3039 if (vbt) {3040 drm_dbg_kms(display->drm,3041 "Found valid VBT firmware \"%s\"\n", name);3042 if (size)3043 *size = fw->size;3044 }3045 } else {3046 drm_dbg_kms(display->drm, "Invalid VBT firmware \"%s\"\n",3047 name);3048 }3049 3050 release_firmware(fw);3051 3052 return vbt;3053}3054 3055static u32 intel_spi_read(struct intel_uncore *uncore, u32 offset)3056{3057 intel_uncore_write(uncore, PRIMARY_SPI_ADDRESS, offset);3058 3059 return intel_uncore_read(uncore, PRIMARY_SPI_TRIGGER);3060}3061 3062static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display,3063 size_t *size)3064{3065 struct drm_i915_private *i915 = to_i915(display->drm);3066 u32 count, data, found, store = 0;3067 u32 static_region, oprom_offset;3068 u32 oprom_size = 0x200000;3069 u16 vbt_size;3070 u32 *vbt;3071 3072 static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);3073 static_region &= OPTIONROM_SPI_REGIONID_MASK;3074 intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);3075 3076 oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);3077 oprom_offset &= OROM_OFFSET_MASK;3078 3079 for (count = 0; count < oprom_size; count += 4) {3080 data = intel_spi_read(&i915->uncore, oprom_offset + count);3081 if (data == *((const u32 *)"$VBT")) {3082 found = oprom_offset + count;3083 break;3084 }3085 }3086 3087 if (count >= oprom_size)3088 goto err_not_found;3089 3090 /* Get VBT size and allocate space for the VBT */3091 vbt_size = intel_spi_read(&i915->uncore,3092 found + offsetof(struct vbt_header, vbt_size));3093 vbt_size &= 0xffff;3094 3095 vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL);3096 if (!vbt)3097 goto err_not_found;3098 3099 for (count = 0; count < vbt_size; count += 4)3100 *(vbt + store++) = intel_spi_read(&i915->uncore, found + count);3101 3102 if (!intel_bios_is_valid_vbt(display, vbt, vbt_size))3103 goto err_free_vbt;3104 3105 drm_dbg_kms(display->drm, "Found valid VBT in SPI flash\n");3106 3107 if (size)3108 *size = vbt_size;3109 3110 return (struct vbt_header *)vbt;3111 3112err_free_vbt:3113 kfree(vbt);3114err_not_found:3115 return NULL;3116}3117 3118static struct vbt_header *oprom_get_vbt(struct intel_display *display,3119 size_t *sizep)3120{3121 struct pci_dev *pdev = to_pci_dev(display->drm->dev);3122 void __iomem *p = NULL, *oprom;3123 struct vbt_header *vbt;3124 u16 vbt_size;3125 size_t i, size;3126 3127 oprom = pci_map_rom(pdev, &size);3128 if (!oprom)3129 return NULL;3130 3131 /* Scour memory looking for the VBT signature. */3132 for (i = 0; i + 4 < size; i += 4) {3133 if (ioread32(oprom + i) != *((const u32 *)"$VBT"))3134 continue;3135 3136 p = oprom + i;3137 size -= i;3138 break;3139 }3140 3141 if (!p)3142 goto err_unmap_oprom;3143 3144 if (sizeof(struct vbt_header) > size) {3145 drm_dbg(display->drm, "VBT header incomplete\n");3146 goto err_unmap_oprom;3147 }3148 3149 vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size));3150 if (vbt_size > size) {3151 drm_dbg(display->drm,3152 "VBT incomplete (vbt_size overflows)\n");3153 goto err_unmap_oprom;3154 }3155 3156 /* The rest will be validated by intel_bios_is_valid_vbt() */3157 vbt = kmalloc(vbt_size, GFP_KERNEL);3158 if (!vbt)3159 goto err_unmap_oprom;3160 3161 memcpy_fromio(vbt, p, vbt_size);3162 3163 if (!intel_bios_is_valid_vbt(display, vbt, vbt_size))3164 goto err_free_vbt;3165 3166 pci_unmap_rom(pdev, oprom);3167 3168 if (sizep)3169 *sizep = vbt_size;3170 3171 drm_dbg_kms(display->drm, "Found valid VBT in PCI ROM\n");3172 3173 return vbt;3174 3175err_free_vbt:3176 kfree(vbt);3177err_unmap_oprom:3178 pci_unmap_rom(pdev, oprom);3179 3180 return NULL;3181}3182 3183static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display,3184 size_t *sizep)3185{3186 struct drm_i915_private *i915 = to_i915(display->drm);3187 const struct vbt_header *vbt = NULL;3188 intel_wakeref_t wakeref;3189 3190 vbt = firmware_get_vbt(display, sizep);3191 3192 if (!vbt)3193 vbt = intel_opregion_get_vbt(display, sizep);3194 3195 /*3196 * If the OpRegion does not have VBT, look in SPI flash3197 * through MMIO or PCI mapping3198 */3199 if (!vbt && IS_DGFX(i915))3200 with_intel_runtime_pm(&i915->runtime_pm, wakeref)3201 vbt = spi_oprom_get_vbt(display, sizep);3202 3203 if (!vbt)3204 with_intel_runtime_pm(&i915->runtime_pm, wakeref)3205 vbt = oprom_get_vbt(display, sizep);3206 3207 return vbt;3208}3209 3210/**3211 * intel_bios_init - find VBT and initialize settings from the BIOS3212 * @display: display device instance3213 *3214 * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT3215 * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also3216 * initialize some defaults if the VBT is not present at all.3217 */3218void intel_bios_init(struct intel_display *display)3219{3220 const struct vbt_header *vbt;3221 const struct bdb_header *bdb;3222 3223 INIT_LIST_HEAD(&display->vbt.display_devices);3224 INIT_LIST_HEAD(&display->vbt.bdb_blocks);3225 3226 if (!HAS_DISPLAY(display)) {3227 drm_dbg_kms(display->drm,3228 "Skipping VBT init due to disabled display.\n");3229 return;3230 }3231 3232 init_vbt_defaults(display);3233 3234 vbt = intel_bios_get_vbt(display, NULL);3235 3236 if (!vbt)3237 goto out;3238 3239 bdb = get_bdb_header(vbt);3240 display->vbt.version = bdb->version;3241 3242 drm_dbg_kms(display->drm,3243 "VBT signature \"%.*s\", BDB version %d\n",3244 (int)sizeof(vbt->signature), vbt->signature,3245 display->vbt.version);3246 3247 init_bdb_blocks(display, bdb);3248 3249 /* Grab useful general definitions */3250 parse_general_features(display);3251 parse_general_definitions(display);3252 parse_driver_features(display);3253 3254 /* Depends on child device list */3255 parse_compression_parameters(display);3256 3257out:3258 if (!vbt) {3259 drm_info(display->drm,3260 "Failed to find VBIOS tables (VBT)\n");3261 init_vbt_missing_defaults(display);3262 }3263 3264 /* Further processing on pre-parsed or generated child device data */3265 parse_sdvo_device_mapping(display);3266 parse_ddi_ports(display);3267 3268 kfree(vbt);3269}3270 3271static void intel_bios_init_panel(struct intel_display *display,3272 struct intel_panel *panel,3273 const struct intel_bios_encoder_data *devdata,3274 const struct drm_edid *drm_edid,3275 bool use_fallback)3276{3277 /* already have it? */3278 if (panel->vbt.panel_type >= 0) {3279 drm_WARN_ON(display->drm, !use_fallback);3280 return;3281 }3282 3283 panel->vbt.panel_type = get_panel_type(display, devdata,3284 drm_edid, use_fallback);3285 if (panel->vbt.panel_type < 0) {3286 drm_WARN_ON(display->drm, use_fallback);3287 return;3288 }3289 3290 init_vbt_panel_defaults(panel);3291 3292 parse_panel_options(display, panel);3293 parse_generic_dtd(display, panel);3294 parse_lfp_data(display, panel);3295 parse_lfp_backlight(display, panel);3296 parse_sdvo_lvds_data(display, panel);3297 parse_panel_driver_features(display, panel);3298 parse_power_conservation_features(display, panel);3299 parse_edp(display, panel);3300 parse_psr(display, panel);3301 parse_mipi_config(display, panel);3302 parse_mipi_sequence(display, panel);3303}3304 3305void intel_bios_init_panel_early(struct intel_display *display,3306 struct intel_panel *panel,3307 const struct intel_bios_encoder_data *devdata)3308{3309 intel_bios_init_panel(display, panel, devdata, NULL, false);3310}3311 3312void intel_bios_init_panel_late(struct intel_display *display,3313 struct intel_panel *panel,3314 const struct intel_bios_encoder_data *devdata,3315 const struct drm_edid *drm_edid)3316{3317 intel_bios_init_panel(display, panel, devdata, drm_edid, true);3318}3319 3320/**3321 * intel_bios_driver_remove - Free any resources allocated by intel_bios_init()3322 * @display: display device instance3323 */3324void intel_bios_driver_remove(struct intel_display *display)3325{3326 struct intel_bios_encoder_data *devdata, *nd;3327 struct bdb_block_entry *entry, *ne;3328 3329 list_for_each_entry_safe(devdata, nd, &display->vbt.display_devices,3330 node) {3331 list_del(&devdata->node);3332 kfree(devdata->dsc);3333 kfree(devdata);3334 }3335 3336 list_for_each_entry_safe(entry, ne, &display->vbt.bdb_blocks, node) {3337 list_del(&entry->node);3338 kfree(entry);3339 }3340}3341 3342void intel_bios_fini_panel(struct intel_panel *panel)3343{3344 kfree(panel->vbt.sdvo_lvds_vbt_mode);3345 panel->vbt.sdvo_lvds_vbt_mode = NULL;3346 kfree(panel->vbt.lfp_vbt_mode);3347 panel->vbt.lfp_vbt_mode = NULL;3348 kfree(panel->vbt.dsi.data);3349 panel->vbt.dsi.data = NULL;3350 kfree(panel->vbt.dsi.pps);3351 panel->vbt.dsi.pps = NULL;3352 kfree(panel->vbt.dsi.config);3353 panel->vbt.dsi.config = NULL;3354 kfree(panel->vbt.dsi.deassert_seq);3355 panel->vbt.dsi.deassert_seq = NULL;3356}3357 3358/**3359 * intel_bios_is_tv_present - is integrated TV present in VBT3360 * @display: display device instance3361 *3362 * Return true if TV is present. If no child devices were parsed from VBT,3363 * assume TV is present.3364 */3365bool intel_bios_is_tv_present(struct intel_display *display)3366{3367 const struct intel_bios_encoder_data *devdata;3368 3369 if (!display->vbt.int_tv_support)3370 return false;3371 3372 if (list_empty(&display->vbt.display_devices))3373 return true;3374 3375 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3376 const struct child_device_config *child = &devdata->child;3377 3378 /*3379 * If the device type is not TV, continue.3380 */3381 switch (child->device_type) {3382 case DEVICE_TYPE_INT_TV:3383 case DEVICE_TYPE_TV:3384 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:3385 break;3386 default:3387 continue;3388 }3389 /* Only when the addin_offset is non-zero, it is regarded3390 * as present.3391 */3392 if (child->addin_offset)3393 return true;3394 }3395 3396 return false;3397}3398 3399/**3400 * intel_bios_is_lvds_present - is LVDS present in VBT3401 * @display: display device instance3402 * @i2c_pin: i2c pin for LVDS if present3403 *3404 * Return true if LVDS is present. If no child devices were parsed from VBT,3405 * assume LVDS is present.3406 */3407bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)3408{3409 struct drm_i915_private *i915 = to_i915(display->drm);3410 const struct intel_bios_encoder_data *devdata;3411 3412 if (list_empty(&display->vbt.display_devices))3413 return true;3414 3415 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3416 const struct child_device_config *child = &devdata->child;3417 3418 /* If the device type is not LFP, continue.3419 * We have to check both the new identifiers as well as the3420 * old for compatibility with some BIOSes.3421 */3422 if (child->device_type != DEVICE_TYPE_INT_LFP &&3423 child->device_type != DEVICE_TYPE_LFP)3424 continue;3425 3426 if (intel_gmbus_is_valid_pin(i915, child->i2c_pin))3427 *i2c_pin = child->i2c_pin;3428 3429 /* However, we cannot trust the BIOS writers to populate3430 * the VBT correctly. Since LVDS requires additional3431 * information from AIM blocks, a non-zero addin offset is3432 * a good indicator that the LVDS is actually present.3433 */3434 if (child->addin_offset)3435 return true;3436 3437 /* But even then some BIOS writers perform some black magic3438 * and instantiate the device without reference to any3439 * additional data. Trust that if the VBT was written into3440 * the OpRegion then they have validated the LVDS's existence.3441 */3442 return intel_opregion_vbt_present(display);3443 }3444 3445 return false;3446}3447 3448/**3449 * intel_bios_is_port_present - is the specified digital port present3450 * @display: display device instance3451 * @port: port to check3452 *3453 * Return true if the device in %port is present.3454 */3455bool intel_bios_is_port_present(struct intel_display *display, enum port port)3456{3457 const struct intel_bios_encoder_data *devdata;3458 3459 if (WARN_ON(!has_ddi_port_info(display)))3460 return true;3461 3462 if (!is_port_valid(display, port))3463 return false;3464 3465 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3466 const struct child_device_config *child = &devdata->child;3467 3468 if (dvo_port_to_port(display, child->dvo_port) == port)3469 return true;3470 }3471 3472 return false;3473}3474 3475bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata)3476{3477 const struct child_device_config *child = &devdata->child;3478 3479 if (!devdata)3480 return false;3481 3482 if (!intel_bios_encoder_supports_dp(devdata) ||3483 !intel_bios_encoder_supports_hdmi(devdata))3484 return false;3485 3486 if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA)3487 return true;3488 3489 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */3490 if (dvo_port_type(child->dvo_port) == DVO_PORT_HDMIA &&3491 child->aux_channel != 0)3492 return true;3493 3494 return false;3495}3496 3497/**3498 * intel_bios_is_dsi_present - is DSI present in VBT3499 * @display: display device instance3500 * @port: port for DSI if present3501 *3502 * Return true if DSI is present, and return the port in %port.3503 */3504bool intel_bios_is_dsi_present(struct intel_display *display,3505 enum port *port)3506{3507 const struct intel_bios_encoder_data *devdata;3508 3509 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3510 const struct child_device_config *child = &devdata->child;3511 u8 dvo_port = child->dvo_port;3512 3513 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))3514 continue;3515 3516 if (dsi_dvo_port_to_port(display, dvo_port) == PORT_NONE) {3517 drm_dbg_kms(display->drm,3518 "VBT has unsupported DSI port %c\n",3519 port_name(dvo_port - DVO_PORT_MIPIA));3520 continue;3521 }3522 3523 if (port)3524 *port = dsi_dvo_port_to_port(display, dvo_port);3525 return true;3526 }3527 3528 return false;3529}3530 3531static void fill_dsc(struct intel_crtc_state *crtc_state,3532 struct dsc_compression_parameters_entry *dsc,3533 int dsc_max_bpc)3534{3535 struct intel_display *display = to_intel_display(crtc_state);3536 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;3537 int bpc = 8;3538 3539 vdsc_cfg->dsc_version_major = dsc->version_major;3540 vdsc_cfg->dsc_version_minor = dsc->version_minor;3541 3542 if (dsc->support_12bpc && dsc_max_bpc >= 12)3543 bpc = 12;3544 else if (dsc->support_10bpc && dsc_max_bpc >= 10)3545 bpc = 10;3546 else if (dsc->support_8bpc && dsc_max_bpc >= 8)3547 bpc = 8;3548 else3549 drm_dbg_kms(display->drm, "VBT: Unsupported BPC %d for DCS\n",3550 dsc_max_bpc);3551 3552 crtc_state->pipe_bpp = bpc * 3;3553 3554 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,3555 VBT_DSC_MAX_BPP(dsc->max_bpp)));3556 3557 /*3558 * FIXME: This is ugly, and slice count should take DSC engine3559 * throughput etc. into account.3560 *3561 * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.3562 */3563 if (dsc->slices_per_line & BIT(2)) {3564 crtc_state->dsc.slice_count = 4;3565 } else if (dsc->slices_per_line & BIT(1)) {3566 crtc_state->dsc.slice_count = 2;3567 } else {3568 /* FIXME */3569 if (!(dsc->slices_per_line & BIT(0)))3570 drm_dbg_kms(display->drm,3571 "VBT: Unsupported DSC slice count for DSI\n");3572 3573 crtc_state->dsc.slice_count = 1;3574 }3575 3576 if (crtc_state->hw.adjusted_mode.crtc_hdisplay %3577 crtc_state->dsc.slice_count != 0)3578 drm_dbg_kms(display->drm,3579 "VBT: DSC hdisplay %d not divisible by slice count %d\n",3580 crtc_state->hw.adjusted_mode.crtc_hdisplay,3581 crtc_state->dsc.slice_count);3582 3583 /*3584 * The VBT rc_buffer_block_size and rc_buffer_size definitions3585 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.3586 */3587 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,3588 dsc->rc_buffer_size);3589 3590 /* FIXME: DSI spec says bpc + 1 for this one */3591 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);3592 3593 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;3594 3595 vdsc_cfg->slice_height = dsc->slice_height;3596}3597 3598/* FIXME: initially DSI specific */3599bool intel_bios_get_dsc_params(struct intel_encoder *encoder,3600 struct intel_crtc_state *crtc_state,3601 int dsc_max_bpc)3602{3603 struct intel_display *display = to_intel_display(encoder);3604 const struct intel_bios_encoder_data *devdata;3605 3606 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3607 const struct child_device_config *child = &devdata->child;3608 3609 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))3610 continue;3611 3612 if (dsi_dvo_port_to_port(display, child->dvo_port) == encoder->port) {3613 if (!devdata->dsc)3614 return false;3615 3616 fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);3617 3618 return true;3619 }3620 }3621 3622 return false;3623}3624 3625static const u8 adlp_aux_ch_map[] = {3626 [AUX_CH_A] = DP_AUX_A,3627 [AUX_CH_B] = DP_AUX_B,3628 [AUX_CH_C] = DP_AUX_C,3629 [AUX_CH_D_XELPD] = DP_AUX_D,3630 [AUX_CH_E_XELPD] = DP_AUX_E,3631 [AUX_CH_USBC1] = DP_AUX_F,3632 [AUX_CH_USBC2] = DP_AUX_G,3633 [AUX_CH_USBC3] = DP_AUX_H,3634 [AUX_CH_USBC4] = DP_AUX_I,3635};3636 3637/*3638 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E3639 * map to DDI A,TC1,TC2,TC3,TC4 respectively.3640 */3641static const u8 adls_aux_ch_map[] = {3642 [AUX_CH_A] = DP_AUX_A,3643 [AUX_CH_USBC1] = DP_AUX_B,3644 [AUX_CH_USBC2] = DP_AUX_C,3645 [AUX_CH_USBC3] = DP_AUX_D,3646 [AUX_CH_USBC4] = DP_AUX_E,3647};3648 3649/*3650 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D3651 * map to DDI A,B,TC1,TC2 respectively.3652 */3653static const u8 rkl_aux_ch_map[] = {3654 [AUX_CH_A] = DP_AUX_A,3655 [AUX_CH_B] = DP_AUX_B,3656 [AUX_CH_USBC1] = DP_AUX_C,3657 [AUX_CH_USBC2] = DP_AUX_D,3658};3659 3660static const u8 direct_aux_ch_map[] = {3661 [AUX_CH_A] = DP_AUX_A,3662 [AUX_CH_B] = DP_AUX_B,3663 [AUX_CH_C] = DP_AUX_C,3664 [AUX_CH_D] = DP_AUX_D, /* aka AUX_CH_USBC1 */3665 [AUX_CH_E] = DP_AUX_E, /* aka AUX_CH_USBC2 */3666 [AUX_CH_F] = DP_AUX_F, /* aka AUX_CH_USBC3 */3667 [AUX_CH_G] = DP_AUX_G, /* aka AUX_CH_USBC4 */3668 [AUX_CH_H] = DP_AUX_H, /* aka AUX_CH_USBC5 */3669 [AUX_CH_I] = DP_AUX_I, /* aka AUX_CH_USBC6 */3670};3671 3672static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel)3673{3674 struct drm_i915_private *i915 = to_i915(display->drm);3675 const u8 *aux_ch_map;3676 int i, n_entries;3677 3678 if (DISPLAY_VER(display) >= 13) {3679 aux_ch_map = adlp_aux_ch_map;3680 n_entries = ARRAY_SIZE(adlp_aux_ch_map);3681 } else if (IS_ALDERLAKE_S(i915)) {3682 aux_ch_map = adls_aux_ch_map;3683 n_entries = ARRAY_SIZE(adls_aux_ch_map);3684 } else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) {3685 aux_ch_map = rkl_aux_ch_map;3686 n_entries = ARRAY_SIZE(rkl_aux_ch_map);3687 } else {3688 aux_ch_map = direct_aux_ch_map;3689 n_entries = ARRAY_SIZE(direct_aux_ch_map);3690 }3691 3692 for (i = 0; i < n_entries; i++) {3693 if (aux_ch_map[i] == aux_channel)3694 return i;3695 }3696 3697 drm_dbg_kms(display->drm,3698 "Ignoring alternate AUX CH: VBT claims AUX 0x%x, which is not valid for this platform\n",3699 aux_channel);3700 3701 return AUX_CH_NONE;3702}3703 3704enum aux_ch intel_bios_dp_aux_ch(const struct intel_bios_encoder_data *devdata)3705{3706 if (!devdata || !devdata->child.aux_channel)3707 return AUX_CH_NONE;3708 3709 return map_aux_ch(devdata->display, devdata->child.aux_channel);3710}3711 3712bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata)3713{3714 struct intel_display *display;3715 u8 aux_channel;3716 int count = 0;3717 3718 if (!devdata || !devdata->child.aux_channel)3719 return false;3720 3721 display = devdata->display;3722 aux_channel = devdata->child.aux_channel;3723 3724 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3725 if (intel_bios_encoder_supports_dp(devdata) &&3726 aux_channel == devdata->child.aux_channel)3727 count++;3728 }3729 3730 return count > 1;3731}3732 3733int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata)3734{3735 if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)3736 return 0;3737 3738 return translate_iboost(devdata->display, devdata->child.dp_iboost_level);3739}3740 3741int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata)3742{3743 if (!devdata || devdata->display->vbt.version < 196 || !devdata->child.iboost)3744 return 0;3745 3746 return translate_iboost(devdata->display, devdata->child.hdmi_iboost_level);3747}3748 3749int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)3750{3751 if (!devdata || !devdata->child.ddc_pin)3752 return 0;3753 3754 return map_ddc_pin(devdata->display, devdata->child.ddc_pin);3755}3756 3757bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)3758{3759 return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;3760}3761 3762bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)3763{3764 return devdata->display->vbt.version >= 209 && devdata->child.tbt;3765}3766 3767bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)3768{3769 return devdata && devdata->child.lane_reversal;3770}3771 3772bool intel_bios_encoder_hpd_invert(const struct intel_bios_encoder_data *devdata)3773{3774 return devdata && devdata->child.hpd_invert;3775}3776 3777const struct intel_bios_encoder_data *3778intel_bios_encoder_data_lookup(struct intel_display *display, enum port port)3779{3780 struct intel_bios_encoder_data *devdata;3781 3782 list_for_each_entry(devdata, &display->vbt.display_devices, node) {3783 if (intel_bios_encoder_port(devdata) == port)3784 return devdata;3785 }3786 3787 return NULL;3788}3789 3790void intel_bios_for_each_encoder(struct intel_display *display,3791 void (*func)(struct intel_display *display,3792 const struct intel_bios_encoder_data *devdata))3793{3794 struct intel_bios_encoder_data *devdata;3795 3796 list_for_each_entry(devdata, &display->vbt.display_devices, node)3797 func(display, devdata);3798}3799 3800static int intel_bios_vbt_show(struct seq_file *m, void *unused)3801{3802 struct intel_display *display = m->private;3803 const void *vbt;3804 size_t vbt_size;3805 3806 vbt = intel_bios_get_vbt(display, &vbt_size);3807 3808 if (vbt) {3809 seq_write(m, vbt, vbt_size);3810 kfree(vbt);3811 }3812 3813 return 0;3814}3815 3816DEFINE_SHOW_ATTRIBUTE(intel_bios_vbt);3817 3818void intel_bios_debugfs_register(struct intel_display *display)3819{3820 struct drm_minor *minor = display->drm->primary;3821 3822 debugfs_create_file("i915_vbt", 0444, minor->debugfs_root,3823 display, &intel_bios_vbt_fops);3824}3825