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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2018 Intel Corporation4 */5 6#include "i915_reg.h"7#include "intel_combo_phy.h"8#include "intel_combo_phy_regs.h"9#include "intel_de.h"10#include "intel_display_types.h"11 12#define for_each_combo_phy(__dev_priv, __phy) \13 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \14 for_each_if(intel_phy_is_combo(__dev_priv, __phy))15 16#define for_each_combo_phy_reverse(__dev_priv, __phy) \17 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \18 for_each_if(intel_phy_is_combo(__dev_priv, __phy))19 20enum {21 PROCMON_0_85V_DOT_0,22 PROCMON_0_95V_DOT_0,23 PROCMON_0_95V_DOT_1,24 PROCMON_1_05V_DOT_0,25 PROCMON_1_05V_DOT_1,26};27 28static const struct icl_procmon {29 const char *name;30 u32 dw1, dw9, dw10;31} icl_procmon_values[] = {32 [PROCMON_0_85V_DOT_0] = {33 .name = "0.85V dot0 (low-voltage)",34 .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96,35 },36 [PROCMON_0_95V_DOT_0] = {37 .name = "0.95V dot0",38 .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB,39 },40 [PROCMON_0_95V_DOT_1] = {41 .name = "0.95V dot1",42 .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5,43 },44 [PROCMON_1_05V_DOT_0] = {45 .name = "1.05V dot0",46 .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1,47 },48 [PROCMON_1_05V_DOT_1] = {49 .name = "1.05V dot1",50 .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1,51 },52};53 54static const struct icl_procmon *55icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)56{57 u32 val;58 59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));60 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {61 default:62 MISSING_CASE(val);63 fallthrough;64 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:65 return &icl_procmon_values[PROCMON_0_85V_DOT_0];66 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:67 return &icl_procmon_values[PROCMON_0_95V_DOT_0];68 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:69 return &icl_procmon_values[PROCMON_0_95V_DOT_1];70 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:71 return &icl_procmon_values[PROCMON_1_05V_DOT_0];72 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:73 return &icl_procmon_values[PROCMON_1_05V_DOT_1];74 }75}76 77static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,78 enum phy phy)79{80 const struct icl_procmon *procmon;81 82 procmon = icl_get_procmon_ref_values(dev_priv, phy);83 84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy),85 (0xff << 16) | 0xff, procmon->dw1);86 87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);89}90 91static bool check_phy_reg(struct drm_i915_private *dev_priv,92 enum phy phy, i915_reg_t reg, u32 mask,93 u32 expected_val)94{95 u32 val = intel_de_read(dev_priv, reg);96 97 if ((val & mask) != expected_val) {98 drm_dbg(&dev_priv->drm,99 "Combo PHY %c reg %08x state mismatch: "100 "current %08x mask %08x expected %08x\n",101 phy_name(phy),102 reg.reg, val, mask, expected_val);103 return false;104 }105 106 return true;107}108 109static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,110 enum phy phy)111{112 const struct icl_procmon *procmon;113 bool ret;114 115 procmon = icl_get_procmon_ref_values(dev_priv, phy);116 117 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),118 (0xff << 16) | 0xff, procmon->dw1);119 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),120 -1U, procmon->dw9);121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),122 -1U, procmon->dw10);123 124 return ret;125}126 127static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)128{129 /*130 * Some platforms only expect PHY_MISC to be programmed for PHY-A and131 * PHY-B and may not even have instances of the register for the132 * other combo PHY's.133 *134 * ADL-S technically has three instances of PHY_MISC, but only requires135 * that we program it for PHY A.136 */137 138 if (IS_ALDERLAKE_S(i915))139 return phy == PHY_A;140 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||141 IS_ROCKETLAKE(i915) ||142 IS_DG1(i915))143 return phy < PHY_C;144 145 return true;146}147 148static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,149 enum phy phy)150{151 /* The PHY C added by EHL has no PHY_MISC register */152 if (!has_phy_misc(dev_priv, phy))153 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;154 else155 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &156 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&157 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);158}159 160static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)161{162 struct intel_display *display = &i915->display;163 164 bool ddi_a_present = intel_bios_is_port_present(display, PORT_A);165 bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);166 bool dsi_present = intel_bios_is_dsi_present(display, NULL);167 168 /*169 * VBT's 'dvo port' field for child devices references the DDI, not170 * the PHY. So if combo PHY A is wired up to drive an external171 * display, we should see a child device present on PORT_D and172 * nothing on PORT_A and no DSI.173 */174 if (ddi_d_present && !ddi_a_present && !dsi_present)175 return true;176 177 /*178 * If we encounter a VBT that claims to have an external display on179 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message180 * in the log and let the internal display win.181 */182 if (ddi_d_present)183 drm_err(&i915->drm,184 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n");185 186 return false;187}188 189static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)190{191 /*192 * Certain PHYs are connected to compensation resistors and act193 * as masters to other PHYs.194 *195 * ICL,TGL:196 * A(master) -> B(slave), C(slave)197 * RKL,DG1:198 * A(master) -> B(slave)199 * C(master) -> D(slave)200 * ADL-S:201 * A(master) -> B(slave), C(slave)202 * D(master) -> E(slave)203 *204 * We must set the IREFGEN bit for any PHY acting as a master205 * to another PHY.206 */207 if (phy == PHY_A)208 return true;209 else if (IS_ALDERLAKE_S(dev_priv))210 return phy == PHY_D;211 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))212 return phy == PHY_C;213 214 return false;215}216 217static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,218 enum phy phy)219{220 bool ret = true;221 u32 expected_val = 0;222 223 if (!icl_combo_phy_enabled(dev_priv, phy))224 return false;225 226 if (DISPLAY_VER(dev_priv) >= 12) {227 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),228 ICL_PORT_TX_DW8_ODCC_CLK_SEL |229 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,230 ICL_PORT_TX_DW8_ODCC_CLK_SEL |231 ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);232 233 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),234 DCC_MODE_SELECT_MASK, RUN_DCC_ONCE);235 }236 237 ret &= icl_verify_procmon_ref_values(dev_priv, phy);238 239 if (phy_is_master(dev_priv, phy)) {240 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),241 IREFGEN, IREFGEN);242 243 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {244 if (ehl_vbt_ddi_d_present(dev_priv))245 expected_val = ICL_PHY_MISC_MUX_DDID;246 247 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),248 ICL_PHY_MISC_MUX_DDID,249 expected_val);250 }251 }252 253 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),254 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);255 256 return ret;257}258 259void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,260 enum phy phy, bool is_dsi,261 int lane_count, bool lane_reversal)262{263 u8 lane_mask;264 265 if (is_dsi) {266 drm_WARN_ON(&dev_priv->drm, lane_reversal);267 268 switch (lane_count) {269 case 1:270 lane_mask = PWR_DOWN_LN_3_1_0;271 break;272 case 2:273 lane_mask = PWR_DOWN_LN_3_1;274 break;275 case 3:276 lane_mask = PWR_DOWN_LN_3;277 break;278 default:279 MISSING_CASE(lane_count);280 fallthrough;281 case 4:282 lane_mask = PWR_UP_ALL_LANES;283 break;284 }285 } else {286 switch (lane_count) {287 case 1:288 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :289 PWR_DOWN_LN_3_2_1;290 break;291 case 2:292 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :293 PWR_DOWN_LN_3_2;294 break;295 default:296 MISSING_CASE(lane_count);297 fallthrough;298 case 4:299 lane_mask = PWR_UP_ALL_LANES;300 break;301 }302 }303 304 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy),305 PWR_DOWN_LN_MASK, lane_mask);306}307 308static void icl_combo_phys_init(struct drm_i915_private *dev_priv)309{310 enum phy phy;311 312 for_each_combo_phy(dev_priv, phy) {313 const struct icl_procmon *procmon;314 u32 val;315 316 if (icl_combo_phy_verify_state(dev_priv, phy))317 continue;318 319 procmon = icl_get_procmon_ref_values(dev_priv, phy);320 321 drm_dbg(&dev_priv->drm,322 "Initializing combo PHY %c (Voltage/Process Info : %s)\n",323 phy_name(phy), procmon->name);324 325 if (!has_phy_misc(dev_priv, phy))326 goto skip_phy_misc;327 328 /*329 * EHL's combo PHY A can be hooked up to either an external330 * display (via DDI-D) or an internal display (via DDI-A or331 * the DSI DPHY). This is a motherboard design decision that332 * can't be changed on the fly, so initialize the PHY's mux333 * based on whether our VBT indicates the presence of any334 * "internal" child devices.335 */336 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));337 if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&338 phy == PHY_A) {339 val &= ~ICL_PHY_MISC_MUX_DDID;340 341 if (ehl_vbt_ddi_d_present(dev_priv))342 val |= ICL_PHY_MISC_MUX_DDID;343 }344 345 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;346 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);347 348skip_phy_misc:349 if (DISPLAY_VER(dev_priv) >= 12) {350 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));351 val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;352 val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;353 val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;354 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);355 356 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));357 val &= ~DCC_MODE_SELECT_MASK;358 val |= RUN_DCC_ONCE;359 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);360 }361 362 icl_set_procmon_ref_values(dev_priv, phy);363 364 if (phy_is_master(dev_priv, phy))365 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy),366 0, IREFGEN);367 368 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);369 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),370 0, CL_POWER_DOWN_ENABLE);371 }372}373 374static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)375{376 enum phy phy;377 378 for_each_combo_phy_reverse(dev_priv, phy) {379 if (phy == PHY_A &&380 !icl_combo_phy_verify_state(dev_priv, phy)) {381 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {382 /*383 * A known problem with old ifwi:384 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411385 * Suppress the warning for CI. Remove ASAP!386 */387 drm_dbg_kms(&dev_priv->drm,388 "Combo PHY %c HW state changed unexpectedly\n",389 phy_name(phy));390 } else {391 drm_warn(&dev_priv->drm,392 "Combo PHY %c HW state changed unexpectedly\n",393 phy_name(phy));394 }395 }396 397 if (!has_phy_misc(dev_priv, phy))398 goto skip_phy_misc;399 400 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0,401 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN);402 403skip_phy_misc:404 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);405 }406}407 408void intel_combo_phy_init(struct drm_i915_private *i915)409{410 icl_combo_phys_init(i915);411}412 413void intel_combo_phy_uninit(struct drm_i915_private *i915)414{415 icl_combo_phys_uninit(i915);416}417