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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2022 Intel Corporation4 */5 6#include <drm/drm_edid.h>7#include <drm/drm_eld.h>8 9#include "i915_drv.h"10#include "intel_crtc_state_dump.h"11#include "intel_display_types.h"12#include "intel_hdmi.h"13#include "intel_vdsc.h"14#include "intel_vrr.h"15 16static void intel_dump_crtc_timings(struct drm_printer *p,17 const struct drm_display_mode *mode)18{19 drm_printf(p, "crtc timings: clock=%d, "20 "hd=%d hb=%d-%d hs=%d-%d ht=%d, "21 "vd=%d vb=%d-%d vs=%d-%d vt=%d, "22 "flags=0x%x\n",23 mode->crtc_clock,24 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end,25 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal,26 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end,27 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal,28 mode->flags);29}30 31static void32intel_dump_m_n_config(struct drm_printer *p,33 const struct intel_crtc_state *pipe_config,34 const char *id, unsigned int lane_count,35 const struct intel_link_m_n *m_n)36{37 drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",38 id, lane_count,39 m_n->data_m, m_n->data_n,40 m_n->link_m, m_n->link_n, m_n->tu);41}42 43static void44intel_dump_infoframe(struct drm_i915_private *i915,45 const union hdmi_infoframe *frame)46{47 if (!drm_debug_enabled(DRM_UT_KMS))48 return;49 50 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);51}52 53static void54intel_dump_buffer(const char *prefix, const u8 *buf, size_t len)55{56 if (!drm_debug_enabled(DRM_UT_KMS))57 return;58 59 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE,60 16, 0, buf, len, false);61}62 63#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x64 65static const char * const output_type_str[] = {66 OUTPUT_TYPE(UNUSED),67 OUTPUT_TYPE(ANALOG),68 OUTPUT_TYPE(DVO),69 OUTPUT_TYPE(SDVO),70 OUTPUT_TYPE(LVDS),71 OUTPUT_TYPE(TVOUT),72 OUTPUT_TYPE(HDMI),73 OUTPUT_TYPE(DP),74 OUTPUT_TYPE(EDP),75 OUTPUT_TYPE(DSI),76 OUTPUT_TYPE(DDI),77 OUTPUT_TYPE(DP_MST),78};79 80#undef OUTPUT_TYPE81 82static void snprintf_output_types(char *buf, size_t len,83 unsigned int output_types)84{85 char *str = buf;86 int i;87 88 str[0] = '\0';89 90 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {91 int r;92 93 if ((output_types & BIT(i)) == 0)94 continue;95 96 r = snprintf(str, len, "%s%s",97 str != buf ? "," : "", output_type_str[i]);98 if (r >= len)99 break;100 str += r;101 len -= r;102 103 output_types &= ~BIT(i);104 }105 106 WARN_ON_ONCE(output_types != 0);107}108 109static const char * const output_format_str[] = {110 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",111 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",112 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",113};114 115const char *intel_output_format_name(enum intel_output_format format)116{117 if (format >= ARRAY_SIZE(output_format_str))118 return "invalid";119 return output_format_str[format];120}121 122static void intel_dump_plane_state(struct drm_printer *p,123 const struct intel_plane_state *plane_state)124{125 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);126 const struct drm_framebuffer *fb = plane_state->hw.fb;127 128 if (!fb) {129 drm_printf(p, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",130 plane->base.base.id, plane->base.name,131 str_yes_no(plane_state->uapi.visible));132 return;133 }134 135 drm_printf(p, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",136 plane->base.base.id, plane->base.name,137 fb->base.id, fb->width, fb->height, &fb->format->format,138 fb->modifier, str_yes_no(plane_state->uapi.visible));139 drm_printf(p, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n",140 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);141 if (plane_state->uapi.visible)142 drm_printf(p, "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",143 DRM_RECT_FP_ARG(&plane_state->uapi.src),144 DRM_RECT_ARG(&plane_state->uapi.dst));145}146 147static void148ilk_dump_csc(struct drm_i915_private *i915,149 struct drm_printer *p,150 const char *name,151 const struct intel_csc_matrix *csc)152{153 int i;154 155 drm_printf(p, "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name,156 csc->preoff[0], csc->preoff[1], csc->preoff[2]);157 158 for (i = 0; i < 3; i++)159 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,160 csc->coeff[3 * i + 0],161 csc->coeff[3 * i + 1],162 csc->coeff[3 * i + 2]);163 164 if (DISPLAY_VER(i915) < 7)165 return;166 167 drm_printf(p, "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name,168 csc->postoff[0], csc->postoff[1], csc->postoff[2]);169}170 171static void172vlv_dump_csc(struct drm_printer *p, const char *name,173 const struct intel_csc_matrix *csc)174{175 int i;176 177 for (i = 0; i < 3; i++)178 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,179 csc->coeff[3 * i + 0],180 csc->coeff[3 * i + 1],181 csc->coeff[3 * i + 2]);182}183 184void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,185 struct intel_atomic_state *state,186 const char *context)187{188 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);189 struct drm_i915_private *i915 = to_i915(crtc->base.dev);190 const struct intel_plane_state *plane_state;191 struct intel_plane *plane;192 struct drm_printer p;193 char buf[64];194 int i;195 196 if (!drm_debug_enabled(DRM_UT_KMS))197 return;198 199 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);200 201 drm_printf(&p, "[CRTC:%d:%s] enable: %s [%s]\n",202 crtc->base.base.id, crtc->base.name,203 str_yes_no(pipe_config->hw.enable), context);204 205 if (!pipe_config->hw.enable)206 goto dump_planes;207 208 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);209 drm_printf(&p, "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",210 str_yes_no(pipe_config->hw.active),211 buf, pipe_config->output_types,212 intel_output_format_name(pipe_config->output_format),213 intel_output_format_name(pipe_config->sink_format));214 215 drm_printf(&p, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",216 transcoder_name(pipe_config->cpu_transcoder),217 pipe_config->pipe_bpp, pipe_config->dither);218 219 drm_printf(&p, "MST master transcoder: %s\n",220 transcoder_name(pipe_config->mst_master_transcoder));221 222 drm_printf(&p, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",223 transcoder_name(pipe_config->master_transcoder),224 pipe_config->sync_mode_slaves_mask);225 226 drm_printf(&p, "joiner: %s, pipes: 0x%x\n",227 intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" :228 intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no",229 pipe_config->joiner_pipes);230 231 drm_printf(&p, "splitter: %s, link count %d, overlap %d\n",232 str_enabled_disabled(pipe_config->splitter.enable),233 pipe_config->splitter.link_count,234 pipe_config->splitter.pixel_overlap);235 236 if (pipe_config->has_pch_encoder)237 intel_dump_m_n_config(&p, pipe_config, "fdi",238 pipe_config->fdi_lanes,239 &pipe_config->fdi_m_n);240 241 if (intel_crtc_has_dp_encoder(pipe_config)) {242 intel_dump_m_n_config(&p, pipe_config, "dp m_n",243 pipe_config->lane_count,244 &pipe_config->dp_m_n);245 intel_dump_m_n_config(&p, pipe_config, "dp m2_n2",246 pipe_config->lane_count,247 &pipe_config->dp_m2_n2);248 drm_printf(&p, "fec: %s, enhanced framing: %s\n",249 str_enabled_disabled(pipe_config->fec_enable),250 str_enabled_disabled(pipe_config->enhanced_framing));251 252 drm_printf(&p, "sdp split: %s\n",253 str_enabled_disabled(pipe_config->sdp_split_enable));254 255 drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n",256 str_enabled_disabled(pipe_config->has_psr &&257 !pipe_config->has_panel_replay),258 str_enabled_disabled(pipe_config->has_sel_update),259 str_enabled_disabled(pipe_config->has_panel_replay),260 str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));261 }262 263 drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n",264 pipe_config->framestart_delay, pipe_config->msa_timing_delay);265 266 drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",267 pipe_config->has_audio, pipe_config->has_infoframe,268 pipe_config->infoframes.enable);269 270 if (pipe_config->infoframes.enable &271 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))272 drm_printf(&p, "GCP: 0x%x\n", pipe_config->infoframes.gcp);273 if (pipe_config->infoframes.enable &274 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))275 intel_dump_infoframe(i915, &pipe_config->infoframes.avi);276 if (pipe_config->infoframes.enable &277 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))278 intel_dump_infoframe(i915, &pipe_config->infoframes.spd);279 if (pipe_config->infoframes.enable &280 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))281 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi);282 if (pipe_config->infoframes.enable &283 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))284 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);285 if (pipe_config->infoframes.enable &286 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))287 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);288 if (pipe_config->infoframes.enable &289 intel_hdmi_infoframe_enable(DP_SDP_VSC))290 drm_dp_vsc_sdp_log(&p, &pipe_config->infoframes.vsc);291 if (pipe_config->infoframes.enable &292 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))293 drm_dp_as_sdp_log(&p, &pipe_config->infoframes.as_sdp);294 295 if (pipe_config->has_audio)296 intel_dump_buffer("ELD: ", pipe_config->eld,297 drm_eld_size(pipe_config->eld));298 299 drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",300 str_yes_no(pipe_config->vrr.enable),301 pipe_config->vrr.vmin, pipe_config->vrr.vmax,302 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,303 pipe_config->vrr.flipline,304 intel_vrr_vmin_vblank_start(pipe_config),305 intel_vrr_vmax_vblank_start(pipe_config));306 307 drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",308 DRM_MODE_ARG(&pipe_config->hw.mode));309 drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n",310 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));311 intel_dump_crtc_timings(&p, &pipe_config->hw.adjusted_mode);312 drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n",313 DRM_MODE_ARG(&pipe_config->hw.pipe_mode));314 intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode);315 drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",316 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),317 pipe_config->pixel_rate);318 319 drm_printf(&p, "linetime: %d, ips linetime: %d\n",320 pipe_config->linetime, pipe_config->ips_linetime);321 322 if (DISPLAY_VER(i915) >= 9)323 drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n",324 crtc->num_scalers,325 pipe_config->scaler_state.scaler_users,326 pipe_config->scaler_state.scaler_id,327 pipe_config->hw.scaling_filter);328 329 if (HAS_GMCH(i915))330 drm_printf(&p, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",331 pipe_config->gmch_pfit.control,332 pipe_config->gmch_pfit.pgm_ratios,333 pipe_config->gmch_pfit.lvds_border_bits);334 else335 drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",336 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),337 str_enabled_disabled(pipe_config->pch_pfit.enabled),338 str_yes_no(pipe_config->pch_pfit.force_thru));339 340 drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n",341 pipe_config->ips_enabled, pipe_config->double_wide,342 pipe_config->has_drrs);343 344 intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state);345 346 if (IS_CHERRYVIEW(i915))347 drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",348 pipe_config->cgm_mode, pipe_config->gamma_mode,349 pipe_config->gamma_enable, pipe_config->csc_enable);350 else351 drm_printf(&p, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",352 pipe_config->csc_mode, pipe_config->gamma_mode,353 pipe_config->gamma_enable, pipe_config->csc_enable);354 355 drm_printf(&p, "pre csc lut: %s%d entries, post csc lut: %d entries\n",356 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut ==357 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "",358 pipe_config->pre_csc_lut ?359 drm_color_lut_size(pipe_config->pre_csc_lut) : 0,360 pipe_config->post_csc_lut ?361 drm_color_lut_size(pipe_config->post_csc_lut) : 0);362 363 if (DISPLAY_VER(i915) >= 11)364 ilk_dump_csc(i915, &p, "output csc", &pipe_config->output_csc);365 366 if (!HAS_GMCH(i915))367 ilk_dump_csc(i915, &p, "pipe csc", &pipe_config->csc);368 else if (IS_CHERRYVIEW(i915))369 vlv_dump_csc(&p, "cgm csc", &pipe_config->csc);370 else if (IS_VALLEYVIEW(i915))371 vlv_dump_csc(&p, "wgc csc", &pipe_config->csc);372 373 intel_vdsc_state_dump(&p, 0, pipe_config);374 375dump_planes:376 if (!state)377 return;378 379 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {380 if (plane->pipe == crtc->pipe)381 intel_dump_plane_state(&p, plane_state);382 }383}384