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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2020 Intel Corporation4 */5#include <linux/kernel.h>6 7#include <drm/drm_atomic_helper.h>8#include <drm/drm_atomic_uapi.h>9#include <drm/drm_blend.h>10#include <drm/drm_damage_helper.h>11#include <drm/drm_fourcc.h>12 13#include "i915_reg.h"14#include "intel_atomic.h"15#include "intel_atomic_plane.h"16#include "intel_cursor.h"17#include "intel_cursor_regs.h"18#include "intel_de.h"19#include "intel_display.h"20#include "intel_display_types.h"21#include "intel_fb.h"22#include "intel_fb_pin.h"23#include "intel_frontbuffer.h"24#include "intel_psr.h"25#include "intel_psr_regs.h"26#include "intel_vblank.h"27#include "skl_watermark.h"28 29#include "gem/i915_gem_object.h"30 31/* Cursor formats */32static const u32 intel_cursor_formats[] = {33 DRM_FORMAT_ARGB8888,34};35 36static u32 intel_cursor_base(const struct intel_plane_state *plane_state)37{38 struct drm_i915_private *dev_priv =39 to_i915(plane_state->uapi.plane->dev);40 u32 base;41 42 if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)43 base = plane_state->phys_dma_addr;44 else45 base = intel_plane_ggtt_offset(plane_state);46 47 return base + plane_state->view.color_plane[0].offset;48}49 50static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,51 const struct intel_plane_state *plane_state,52 bool early_tpt)53{54 int x = plane_state->uapi.dst.x1;55 int y = plane_state->uapi.dst.y1;56 u32 pos = 0;57 58 /*59 * Formula from Bspec:60 * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode61 * select setting> + 1, CUR_POS Y Position - Update region Y position62 */63 if (early_tpt)64 y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,65 y - crtc_state->psr2_su_area.y1);66 67 if (x < 0) {68 pos |= CURSOR_POS_X_SIGN;69 x = -x;70 }71 pos |= CURSOR_POS_X(x);72 73 if (y < 0) {74 pos |= CURSOR_POS_Y_SIGN;75 y = -y;76 }77 pos |= CURSOR_POS_Y(y);78 79 return pos;80}81 82static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)83{84 const struct drm_mode_config *config =85 &plane_state->uapi.plane->dev->mode_config;86 int width = drm_rect_width(&plane_state->uapi.dst);87 int height = drm_rect_height(&plane_state->uapi.dst);88 89 return width > 0 && width <= config->cursor_width &&90 height > 0 && height <= config->cursor_height;91}92 93static int intel_cursor_check_surface(struct intel_plane_state *plane_state)94{95 struct drm_i915_private *dev_priv =96 to_i915(plane_state->uapi.plane->dev);97 unsigned int rotation = plane_state->hw.rotation;98 int src_x, src_y;99 u32 offset;100 int ret;101 102 ret = intel_plane_compute_gtt(plane_state);103 if (ret)104 return ret;105 106 if (!plane_state->uapi.visible)107 return 0;108 109 src_x = plane_state->uapi.src.x1 >> 16;110 src_y = plane_state->uapi.src.y1 >> 16;111 112 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);113 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,114 plane_state, 0);115 116 if (src_x != 0 || src_y != 0) {117 drm_dbg_kms(&dev_priv->drm,118 "Arbitrary cursor panning not supported\n");119 return -EINVAL;120 }121 122 /*123 * Put the final coordinates back so that the src124 * coordinate checks will see the right values.125 */126 drm_rect_translate_to(&plane_state->uapi.src,127 src_x << 16, src_y << 16);128 129 /* ILK+ do this automagically in hardware */130 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {131 const struct drm_framebuffer *fb = plane_state->hw.fb;132 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;133 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;134 135 offset += (src_h * src_w - 1) * fb->format->cpp[0];136 }137 138 plane_state->view.color_plane[0].offset = offset;139 plane_state->view.color_plane[0].x = src_x;140 plane_state->view.color_plane[0].y = src_y;141 142 return 0;143}144 145static int intel_check_cursor(struct intel_crtc_state *crtc_state,146 struct intel_plane_state *plane_state)147{148 const struct drm_framebuffer *fb = plane_state->hw.fb;149 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);150 const struct drm_rect src = plane_state->uapi.src;151 const struct drm_rect dst = plane_state->uapi.dst;152 int ret;153 154 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {155 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");156 return -EINVAL;157 }158 159 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,160 DRM_PLANE_NO_SCALING,161 DRM_PLANE_NO_SCALING,162 true);163 if (ret)164 return ret;165 166 /* Use the unclipped src/dst rectangles, which we program to hw */167 plane_state->uapi.src = src;168 plane_state->uapi.dst = dst;169 170 /* final plane coordinates will be relative to the plane's pipe */171 drm_rect_translate(&plane_state->uapi.dst,172 -crtc_state->pipe_src.x1,173 -crtc_state->pipe_src.y1);174 175 ret = intel_cursor_check_surface(plane_state);176 if (ret)177 return ret;178 179 if (!plane_state->uapi.visible)180 return 0;181 182 ret = intel_plane_check_src_coordinates(plane_state);183 if (ret)184 return ret;185 186 return 0;187}188 189static unsigned int190i845_cursor_max_stride(struct intel_plane *plane,191 u32 pixel_format, u64 modifier,192 unsigned int rotation)193{194 return 2048;195}196 197static unsigned int i845_cursor_min_alignment(struct intel_plane *plane,198 const struct drm_framebuffer *fb,199 int color_plane)200{201 return 32;202}203 204static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)205{206 u32 cntl = 0;207 208 if (crtc_state->gamma_enable)209 cntl |= CURSOR_PIPE_GAMMA_ENABLE;210 211 return cntl;212}213 214static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,215 const struct intel_plane_state *plane_state)216{217 return CURSOR_ENABLE |218 CURSOR_FORMAT_ARGB |219 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);220}221 222static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)223{224 int width = drm_rect_width(&plane_state->uapi.dst);225 226 /*227 * 845g/865g are only limited by the width of their cursors,228 * the height is arbitrary up to the precision of the register.229 */230 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);231}232 233static int i845_check_cursor(struct intel_crtc_state *crtc_state,234 struct intel_plane_state *plane_state)235{236 const struct drm_framebuffer *fb = plane_state->hw.fb;237 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);238 int ret;239 240 ret = intel_check_cursor(crtc_state, plane_state);241 if (ret)242 return ret;243 244 /* if we want to turn off the cursor ignore width and height */245 if (!fb)246 return 0;247 248 /* Check for which cursor types we support */249 if (!i845_cursor_size_ok(plane_state)) {250 drm_dbg_kms(&i915->drm,251 "Cursor dimension %dx%d not supported\n",252 drm_rect_width(&plane_state->uapi.dst),253 drm_rect_height(&plane_state->uapi.dst));254 return -EINVAL;255 }256 257 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&258 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);259 260 switch (fb->pitches[0]) {261 case 256:262 case 512:263 case 1024:264 case 2048:265 break;266 default:267 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",268 fb->pitches[0]);269 return -EINVAL;270 }271 272 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);273 274 return 0;275}276 277/* TODO: split into noarm+arm pair */278static void i845_cursor_update_arm(struct intel_plane *plane,279 const struct intel_crtc_state *crtc_state,280 const struct intel_plane_state *plane_state)281{282 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);283 u32 cntl = 0, base = 0, pos = 0, size = 0;284 285 if (plane_state && plane_state->uapi.visible) {286 unsigned int width = drm_rect_width(&plane_state->uapi.dst);287 unsigned int height = drm_rect_height(&plane_state->uapi.dst);288 289 cntl = plane_state->ctl |290 i845_cursor_ctl_crtc(crtc_state);291 292 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);293 294 base = intel_cursor_base(plane_state);295 pos = intel_cursor_position(crtc_state, plane_state, false);296 }297 298 /* On these chipsets we can only modify the base/size/stride299 * whilst the cursor is disabled.300 */301 if (plane->cursor.base != base ||302 plane->cursor.size != size ||303 plane->cursor.cntl != cntl) {304 intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);305 intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);306 intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size);307 intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);308 intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);309 310 plane->cursor.base = base;311 plane->cursor.size = size;312 plane->cursor.cntl = cntl;313 } else {314 intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);315 }316}317 318static void i845_cursor_disable_arm(struct intel_plane *plane,319 const struct intel_crtc_state *crtc_state)320{321 i845_cursor_update_arm(plane, crtc_state, NULL);322}323 324static bool i845_cursor_get_hw_state(struct intel_plane *plane,325 enum pipe *pipe)326{327 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);328 enum intel_display_power_domain power_domain;329 intel_wakeref_t wakeref;330 bool ret;331 332 power_domain = POWER_DOMAIN_PIPE(PIPE_A);333 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);334 if (!wakeref)335 return false;336 337 ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE;338 339 *pipe = PIPE_A;340 341 intel_display_power_put(dev_priv, power_domain, wakeref);342 343 return ret;344}345 346static unsigned int347i9xx_cursor_max_stride(struct intel_plane *plane,348 u32 pixel_format, u64 modifier,349 unsigned int rotation)350{351 return plane->base.dev->mode_config.cursor_width * 4;352}353 354static unsigned int i830_cursor_min_alignment(struct intel_plane *plane,355 const struct drm_framebuffer *fb,356 int color_plane)357{358 /* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned." */359 return 16 * 1024; /* physical */360}361 362static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane,363 const struct drm_framebuffer *fb,364 int color_plane)365{366 return 256; /* physical */367}368 369static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane,370 const struct drm_framebuffer *fb,371 int color_plane)372{373 return 4 * 1024; /* physical for i915/i945 */374}375 376static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)377{378 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);379 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);380 u32 cntl = 0;381 382 if (DISPLAY_VER(dev_priv) >= 11)383 return cntl;384 385 if (crtc_state->gamma_enable)386 cntl = MCURSOR_PIPE_GAMMA_ENABLE;387 388 if (crtc_state->csc_enable)389 cntl |= MCURSOR_PIPE_CSC_ENABLE;390 391 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))392 cntl |= MCURSOR_PIPE_SEL(crtc->pipe);393 394 return cntl;395}396 397static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,398 const struct intel_plane_state *plane_state)399{400 struct drm_i915_private *dev_priv =401 to_i915(plane_state->uapi.plane->dev);402 u32 cntl = 0;403 404 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))405 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;406 407 switch (drm_rect_width(&plane_state->uapi.dst)) {408 case 64:409 cntl |= MCURSOR_MODE_64_ARGB_AX;410 break;411 case 128:412 cntl |= MCURSOR_MODE_128_ARGB_AX;413 break;414 case 256:415 cntl |= MCURSOR_MODE_256_ARGB_AX;416 break;417 default:418 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));419 return 0;420 }421 422 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)423 cntl |= MCURSOR_ROTATE_180;424 425 /* Wa_22012358565:adl-p */426 if (DISPLAY_VER(dev_priv) == 13)427 cntl |= MCURSOR_ARB_SLOTS(1);428 429 return cntl;430}431 432static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)433{434 struct drm_i915_private *dev_priv =435 to_i915(plane_state->uapi.plane->dev);436 int width = drm_rect_width(&plane_state->uapi.dst);437 int height = drm_rect_height(&plane_state->uapi.dst);438 439 if (!intel_cursor_size_ok(plane_state))440 return false;441 442 /* Cursor width is limited to a few power-of-two sizes */443 switch (width) {444 case 256:445 case 128:446 case 64:447 break;448 default:449 return false;450 }451 452 /*453 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor454 * height from 8 lines up to the cursor width, when the455 * cursor is not rotated. Everything else requires square456 * cursors.457 */458 if (HAS_CUR_FBC(dev_priv) &&459 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {460 if (height < 8 || height > width)461 return false;462 } else {463 if (height != width)464 return false;465 }466 467 return true;468}469 470static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,471 struct intel_plane_state *plane_state)472{473 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);474 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);475 const struct drm_framebuffer *fb = plane_state->hw.fb;476 enum pipe pipe = plane->pipe;477 int ret;478 479 ret = intel_check_cursor(crtc_state, plane_state);480 if (ret)481 return ret;482 483 /* if we want to turn off the cursor ignore width and height */484 if (!fb)485 return 0;486 487 /* Check for which cursor types we support */488 if (!i9xx_cursor_size_ok(plane_state)) {489 drm_dbg(&dev_priv->drm,490 "Cursor dimension %dx%d not supported\n",491 drm_rect_width(&plane_state->uapi.dst),492 drm_rect_height(&plane_state->uapi.dst));493 return -EINVAL;494 }495 496 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&497 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);498 499 if (fb->pitches[0] !=500 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {501 drm_dbg_kms(&dev_priv->drm,502 "Invalid cursor stride (%u) (cursor width %d)\n",503 fb->pitches[0],504 drm_rect_width(&plane_state->uapi.dst));505 return -EINVAL;506 }507 508 /*509 * There's something wrong with the cursor on CHV pipe C.510 * If it straddles the left edge of the screen then511 * moving it away from the edge or disabling it often512 * results in a pipe underrun, and often that can lead to513 * dead pipe (constant underrun reported, and it scans514 * out just a solid color). To recover from that, the515 * display power well must be turned off and on again.516 * Refuse the put the cursor into that compromised position.517 */518 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&519 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {520 drm_dbg_kms(&dev_priv->drm,521 "CHV cursor C not allowed to straddle the left screen edge\n");522 return -EINVAL;523 }524 525 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);526 527 return 0;528}529 530static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,531 const struct intel_crtc_state *crtc_state)532{533 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);534 enum pipe pipe = plane->pipe;535 536 if (!crtc_state->enable_psr2_sel_fetch)537 return;538 539 intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);540}541 542static void wa_16021440873(struct intel_plane *plane,543 const struct intel_crtc_state *crtc_state,544 const struct intel_plane_state *plane_state)545{546 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);547 u32 ctl = plane_state->ctl;548 int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1;549 enum pipe pipe = plane->pipe;550 551 ctl &= ~MCURSOR_MODE_MASK;552 ctl |= MCURSOR_MODE_64_2B;553 554 intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);555 556 intel_de_write(dev_priv, CURPOS_ERLY_TPT(dev_priv, pipe),557 CURSOR_POS_Y(et_y_position));558}559 560static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,561 const struct intel_crtc_state *crtc_state,562 const struct intel_plane_state *plane_state)563{564 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);565 enum pipe pipe = plane->pipe;566 567 if (!crtc_state->enable_psr2_sel_fetch)568 return;569 570 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {571 if (crtc_state->enable_psr2_su_region_et) {572 u32 val = intel_cursor_position(crtc_state, plane_state,573 true);574 intel_de_write_fw(dev_priv,575 CURPOS_ERLY_TPT(dev_priv, pipe),576 val);577 }578 579 intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),580 plane_state->ctl);581 } else {582 /* Wa_16021440873 */583 if (crtc_state->enable_psr2_su_region_et)584 wa_16021440873(plane, crtc_state, plane_state);585 else586 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);587 }588}589 590static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)591{592 if (!entry->end)593 return 0;594 595 return CUR_BUF_END(entry->end - 1) |596 CUR_BUF_START(entry->start);597}598 599static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)600{601 u32 val = 0;602 603 if (level->enable)604 val |= CUR_WM_EN;605 if (level->ignore_lines)606 val |= CUR_WM_IGNORE_LINES;607 val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);608 val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);609 610 return val;611}612 613static void skl_write_cursor_wm(struct intel_plane *plane,614 const struct intel_crtc_state *crtc_state)615{616 struct drm_i915_private *i915 = to_i915(plane->base.dev);617 enum plane_id plane_id = plane->id;618 enum pipe pipe = plane->pipe;619 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;620 const struct skl_ddb_entry *ddb =621 &crtc_state->wm.skl.plane_ddb[plane_id];622 int level;623 624 for (level = 0; level < i915->display.wm.num_levels; level++)625 intel_de_write_fw(i915, CUR_WM(pipe, level),626 skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));627 628 intel_de_write_fw(i915, CUR_WM_TRANS(pipe),629 skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));630 631 if (HAS_HW_SAGV_WM(i915)) {632 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];633 634 intel_de_write_fw(i915, CUR_WM_SAGV(pipe),635 skl_cursor_wm_reg_val(&wm->sagv.wm0));636 intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),637 skl_cursor_wm_reg_val(&wm->sagv.trans_wm));638 }639 640 intel_de_write_fw(i915, CUR_BUF_CFG(pipe),641 skl_cursor_ddb_reg_val(ddb));642}643 644/* TODO: split into noarm+arm pair */645static void i9xx_cursor_update_arm(struct intel_plane *plane,646 const struct intel_crtc_state *crtc_state,647 const struct intel_plane_state *plane_state)648{649 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);650 enum pipe pipe = plane->pipe;651 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;652 653 if (plane_state && plane_state->uapi.visible) {654 int width = drm_rect_width(&plane_state->uapi.dst);655 int height = drm_rect_height(&plane_state->uapi.dst);656 657 cntl = plane_state->ctl |658 i9xx_cursor_ctl_crtc(crtc_state);659 660 if (width != height)661 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);662 663 base = intel_cursor_base(plane_state);664 pos = intel_cursor_position(crtc_state, plane_state, false);665 }666 667 /*668 * On some platforms writing CURCNTR first will also669 * cause CURPOS to be armed by the CURBASE write.670 * Without the CURCNTR write the CURPOS write would671 * arm itself. Thus we always update CURCNTR before672 * CURPOS.673 *674 * On other platforms CURPOS always requires the675 * CURBASE write to arm the update. Additonally676 * a write to any of the cursor register will cancel677 * an already armed cursor update. Thus leaving out678 * the CURBASE write after CURPOS could lead to a679 * cursor that doesn't appear to move, or even change680 * shape. Thus we always write CURBASE.681 *682 * The other registers are armed by the CURBASE write683 * except when the plane is getting enabled at which time684 * the CURCNTR write arms the update.685 */686 687 if (DISPLAY_VER(dev_priv) >= 9)688 skl_write_cursor_wm(plane, crtc_state);689 690 if (plane_state)691 i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,692 plane_state);693 else694 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);695 696 if (plane->cursor.base != base ||697 plane->cursor.size != fbc_ctl ||698 plane->cursor.cntl != cntl) {699 if (HAS_CUR_FBC(dev_priv))700 intel_de_write_fw(dev_priv,701 CUR_FBC_CTL(dev_priv, pipe),702 fbc_ctl);703 intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);704 intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);705 intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);706 707 plane->cursor.base = base;708 plane->cursor.size = fbc_ctl;709 plane->cursor.cntl = cntl;710 } else {711 intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);712 intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);713 }714}715 716static void i9xx_cursor_disable_arm(struct intel_plane *plane,717 const struct intel_crtc_state *crtc_state)718{719 i9xx_cursor_update_arm(plane, crtc_state, NULL);720}721 722static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,723 enum pipe *pipe)724{725 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);726 enum intel_display_power_domain power_domain;727 intel_wakeref_t wakeref;728 bool ret;729 u32 val;730 731 /*732 * Not 100% correct for planes that can move between pipes,733 * but that's only the case for gen2-3 which don't have any734 * display power wells.735 */736 power_domain = POWER_DOMAIN_PIPE(plane->pipe);737 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);738 if (!wakeref)739 return false;740 741 val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe));742 743 ret = val & MCURSOR_MODE_MASK;744 745 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))746 *pipe = plane->pipe;747 else748 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);749 750 intel_display_power_put(dev_priv, power_domain, wakeref);751 752 return ret;753}754 755static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,756 u32 format, u64 modifier)757{758 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))759 return false;760 761 return format == DRM_FORMAT_ARGB8888;762}763 764void intel_cursor_unpin_work(struct kthread_work *base)765{766 struct drm_vblank_work *work = to_drm_vblank_work(base);767 struct intel_plane_state *plane_state =768 container_of(work, typeof(*plane_state), unpin_work);769 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);770 771 intel_plane_unpin_fb(plane_state);772 intel_plane_destroy_state(&plane->base, &plane_state->uapi);773}774 775static int776intel_legacy_cursor_update(struct drm_plane *_plane,777 struct drm_crtc *_crtc,778 struct drm_framebuffer *fb,779 int crtc_x, int crtc_y,780 unsigned int crtc_w, unsigned int crtc_h,781 u32 src_x, u32 src_y,782 u32 src_w, u32 src_h,783 struct drm_modeset_acquire_ctx *ctx)784{785 struct intel_plane *plane = to_intel_plane(_plane);786 struct intel_crtc *crtc = to_intel_crtc(_crtc);787 struct drm_i915_private *i915 = to_i915(plane->base.dev);788 struct intel_plane_state *old_plane_state =789 to_intel_plane_state(plane->base.state);790 struct intel_plane_state *new_plane_state;791 struct intel_crtc_state *crtc_state =792 to_intel_crtc_state(crtc->base.state);793 struct intel_crtc_state *new_crtc_state;794 struct intel_vblank_evade_ctx evade;795 int ret;796 797 /*798 * When crtc is inactive or there is a modeset pending,799 * wait for it to complete in the slowpath.800 * PSR2 selective fetch also requires the slow path as801 * PSR2 plane and transcoder registers can only be updated during802 * vblank.803 *804 * FIXME joiner fastpath would be good805 */806 if (!crtc_state->hw.active ||807 intel_crtc_needs_modeset(crtc_state) ||808 intel_crtc_needs_fastset(crtc_state) ||809 crtc_state->joiner_pipes)810 goto slow;811 812 /*813 * Don't do an async update if there is an outstanding commit modifying814 * the plane. This prevents our async update's changes from getting815 * overridden by a previous synchronous update's state.816 */817 if (old_plane_state->uapi.commit &&818 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))819 goto slow;820 821 /*822 * If any parameters change that may affect watermarks,823 * take the slowpath. Only changing fb or position should be824 * in the fastpath.825 */826 if (old_plane_state->uapi.crtc != &crtc->base ||827 old_plane_state->uapi.src_w != src_w ||828 old_plane_state->uapi.src_h != src_h ||829 old_plane_state->uapi.crtc_w != crtc_w ||830 old_plane_state->uapi.crtc_h != crtc_h ||831 !old_plane_state->uapi.fb != !fb)832 goto slow;833 834 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));835 if (!new_plane_state)836 return -ENOMEM;837 838 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));839 if (!new_crtc_state) {840 ret = -ENOMEM;841 goto out_free;842 }843 844 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);845 846 new_plane_state->uapi.src_x = src_x;847 new_plane_state->uapi.src_y = src_y;848 new_plane_state->uapi.src_w = src_w;849 new_plane_state->uapi.src_h = src_h;850 new_plane_state->uapi.crtc_x = crtc_x;851 new_plane_state->uapi.crtc_y = crtc_y;852 new_plane_state->uapi.crtc_w = crtc_w;853 new_plane_state->uapi.crtc_h = crtc_h;854 855 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);856 857 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,858 old_plane_state, new_plane_state);859 if (ret)860 goto out_free;861 862 ret = intel_plane_pin_fb(new_plane_state);863 if (ret)864 goto out_free;865 866 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),867 ORIGIN_CURSOR_UPDATE);868 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),869 to_intel_frontbuffer(new_plane_state->hw.fb),870 plane->frontbuffer_bit);871 872 /* Swap plane state */873 plane->base.state = &new_plane_state->uapi;874 875 /*876 * We cannot swap crtc_state as it may be in use by an atomic commit or877 * page flip that's running simultaneously. If we swap crtc_state and878 * destroy the old state, we will cause a use-after-free there.879 *880 * Only update active_planes, which is needed for our internal881 * bookkeeping. Either value will do the right thing when updating882 * planes atomically. If the cursor was part of the atomic update then883 * we would have taken the slowpath.884 */885 crtc_state->active_planes = new_crtc_state->active_planes;886 887 intel_vblank_evade_init(crtc_state, crtc_state, &evade);888 889 intel_psr_lock(crtc_state);890 891 if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) {892 /*893 * TODO: maybe check if we're still in PSR894 * and skip the vblank evasion entirely?895 */896 intel_psr_wait_for_idle_locked(crtc_state);897 898 local_irq_disable();899 900 intel_vblank_evade(&evade);901 902 drm_crtc_vblank_put(&crtc->base);903 } else {904 local_irq_disable();905 }906 907 if (new_plane_state->uapi.visible) {908 intel_plane_update_noarm(plane, crtc_state, new_plane_state);909 intel_plane_update_arm(plane, crtc_state, new_plane_state);910 } else {911 intel_plane_disable_arm(plane, crtc_state);912 }913 914 local_irq_enable();915 916 intel_psr_unlock(crtc_state);917 918 if (old_plane_state->ggtt_vma != new_plane_state->ggtt_vma) {919 drm_vblank_work_init(&old_plane_state->unpin_work, &crtc->base,920 intel_cursor_unpin_work);921 922 drm_vblank_work_schedule(&old_plane_state->unpin_work,923 drm_crtc_accurate_vblank_count(&crtc->base) + 1,924 false);925 926 old_plane_state = NULL;927 } else {928 intel_plane_unpin_fb(old_plane_state);929 }930 931out_free:932 if (new_crtc_state)933 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);934 if (ret)935 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);936 else if (old_plane_state)937 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);938 return ret;939 940slow:941 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,942 crtc_x, crtc_y, crtc_w, crtc_h,943 src_x, src_y, src_w, src_h, ctx);944}945 946static const struct drm_plane_funcs intel_cursor_plane_funcs = {947 .update_plane = intel_legacy_cursor_update,948 .disable_plane = drm_atomic_helper_disable_plane,949 .destroy = intel_plane_destroy,950 .atomic_duplicate_state = intel_plane_duplicate_state,951 .atomic_destroy_state = intel_plane_destroy_state,952 .format_mod_supported = intel_cursor_format_mod_supported,953};954 955static void intel_cursor_add_size_hints_property(struct intel_plane *plane)956{957 struct drm_i915_private *i915 = to_i915(plane->base.dev);958 const struct drm_mode_config *config = &i915->drm.mode_config;959 struct drm_plane_size_hint hints[4];960 int size, max_size, num_hints = 0;961 962 max_size = min(config->cursor_width, config->cursor_height);963 964 /* for simplicity only enumerate the supported square+POT sizes */965 for (size = 64; size <= max_size; size *= 2) {966 if (drm_WARN_ON(&i915->drm, num_hints >= ARRAY_SIZE(hints)))967 break;968 969 hints[num_hints].width = size;970 hints[num_hints].height = size;971 num_hints++;972 }973 974 drm_plane_add_size_hints_property(&plane->base, hints, num_hints);975}976 977struct intel_plane *978intel_cursor_plane_create(struct drm_i915_private *dev_priv,979 enum pipe pipe)980{981 struct intel_plane *cursor;982 int ret, zpos;983 u64 *modifiers;984 985 cursor = intel_plane_alloc();986 if (IS_ERR(cursor))987 return cursor;988 989 cursor->pipe = pipe;990 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;991 cursor->id = PLANE_CURSOR;992 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);993 994 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {995 cursor->max_stride = i845_cursor_max_stride;996 cursor->min_alignment = i845_cursor_min_alignment;997 cursor->update_arm = i845_cursor_update_arm;998 cursor->disable_arm = i845_cursor_disable_arm;999 cursor->get_hw_state = i845_cursor_get_hw_state;1000 cursor->check_plane = i845_check_cursor;1001 } else {1002 cursor->max_stride = i9xx_cursor_max_stride;1003 1004 if (IS_I830(dev_priv))1005 cursor->min_alignment = i830_cursor_min_alignment;1006 else if (IS_I85X(dev_priv))1007 cursor->min_alignment = i85x_cursor_min_alignment;1008 else1009 cursor->min_alignment = i9xx_cursor_min_alignment;1010 1011 cursor->update_arm = i9xx_cursor_update_arm;1012 cursor->disable_arm = i9xx_cursor_disable_arm;1013 cursor->get_hw_state = i9xx_cursor_get_hw_state;1014 cursor->check_plane = i9xx_check_cursor;1015 }1016 1017 cursor->cursor.base = ~0;1018 cursor->cursor.cntl = ~0;1019 1020 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))1021 cursor->cursor.size = ~0;1022 1023 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);1024 1025 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,1026 0, &intel_cursor_plane_funcs,1027 intel_cursor_formats,1028 ARRAY_SIZE(intel_cursor_formats),1029 modifiers,1030 DRM_PLANE_TYPE_CURSOR,1031 "cursor %c", pipe_name(pipe));1032 1033 kfree(modifiers);1034 1035 if (ret)1036 goto fail;1037 1038 if (DISPLAY_VER(dev_priv) >= 4)1039 drm_plane_create_rotation_property(&cursor->base,1040 DRM_MODE_ROTATE_0,1041 DRM_MODE_ROTATE_0 |1042 DRM_MODE_ROTATE_180);1043 1044 intel_cursor_add_size_hints_property(cursor);1045 1046 zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;1047 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);1048 1049 if (DISPLAY_VER(dev_priv) >= 12)1050 drm_plane_enable_fb_damage_clips(&cursor->base);1051 1052 intel_plane_helper_add(cursor);1053 1054 return cursor;1055 1056fail:1057 intel_plane_free(cursor);1058 1059 return ERR_PTR(ret);1060}1061