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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2019 Intel Corporation4 */5 6#ifndef __INTEL_DE_H__7#define __INTEL_DE_H__8 9#include "i915_drv.h"10#include "i915_trace.h"11#include "intel_uncore.h"12 13static inline struct intel_uncore *__to_uncore(struct intel_display *display)14{15 return &to_i915(display->drm)->uncore;16}17 18static inline u3219__intel_de_read(struct intel_display *display, i915_reg_t reg)20{21 u32 val;22 23 intel_dmc_wl_get(display, reg);24 25 val = intel_uncore_read(__to_uncore(display), reg);26 27 intel_dmc_wl_put(display, reg);28 29 return val;30}31#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)32 33static inline u834__intel_de_read8(struct intel_display *display, i915_reg_t reg)35{36 u8 val;37 38 intel_dmc_wl_get(display, reg);39 40 val = intel_uncore_read8(__to_uncore(display), reg);41 42 intel_dmc_wl_put(display, reg);43 44 return val;45}46#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__)47 48static inline u6449__intel_de_read64_2x32(struct intel_display *display,50 i915_reg_t lower_reg, i915_reg_t upper_reg)51{52 u64 val;53 54 intel_dmc_wl_get(display, lower_reg);55 intel_dmc_wl_get(display, upper_reg);56 57 val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,58 upper_reg);59 60 intel_dmc_wl_put(display, upper_reg);61 intel_dmc_wl_put(display, lower_reg);62 63 return val;64}65#define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)66 67static inline void68__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)69{70 intel_dmc_wl_get(display, reg);71 72 intel_uncore_posting_read(__to_uncore(display), reg);73 74 intel_dmc_wl_put(display, reg);75}76#define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__)77 78static inline void79__intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)80{81 intel_dmc_wl_get(display, reg);82 83 intel_uncore_write(__to_uncore(display), reg, val);84 85 intel_dmc_wl_put(display, reg);86}87#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)88 89static inline u3290____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,91 u32 clear, u32 set)92{93 return intel_uncore_rmw(__to_uncore(display), reg, clear, set);94}95#define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__)96 97static inline u3298__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,99 u32 set)100{101 u32 val;102 103 intel_dmc_wl_get(display, reg);104 105 val = __intel_de_rmw_nowl(display, reg, clear, set);106 107 intel_dmc_wl_put(display, reg);108 109 return val;110}111#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)112 113static inline int114____intel_de_wait_for_register_nowl(struct intel_display *display,115 i915_reg_t reg,116 u32 mask, u32 value, unsigned int timeout)117{118 return intel_wait_for_register(__to_uncore(display), reg, mask,119 value, timeout);120}121#define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__)122 123static inline int124__intel_de_wait(struct intel_display *display, i915_reg_t reg,125 u32 mask, u32 value, unsigned int timeout)126{127 int ret;128 129 intel_dmc_wl_get(display, reg);130 131 ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,132 timeout);133 134 intel_dmc_wl_put(display, reg);135 136 return ret;137}138#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__)139 140static inline int141__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,142 u32 mask, u32 value, unsigned int timeout)143{144 int ret;145 146 intel_dmc_wl_get(display, reg);147 148 ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,149 value, timeout);150 151 intel_dmc_wl_put(display, reg);152 153 return ret;154}155#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__)156 157static inline int158__intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,159 u32 mask, u32 value,160 unsigned int fast_timeout_us,161 unsigned int slow_timeout_ms, u32 *out_value)162{163 int ret;164 165 intel_dmc_wl_get(display, reg);166 167 ret = __intel_wait_for_register(__to_uncore(display), reg, mask,168 value,169 fast_timeout_us, slow_timeout_ms, out_value);170 171 intel_dmc_wl_put(display, reg);172 173 return ret;174}175#define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__)176 177static inline int178__intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,179 u32 mask, unsigned int timeout)180{181 return intel_de_wait(display, reg, mask, mask, timeout);182}183#define intel_de_wait_for_set(p,...) __intel_de_wait_for_set(__to_intel_display(p), __VA_ARGS__)184 185static inline int186__intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,187 u32 mask, unsigned int timeout)188{189 return intel_de_wait(display, reg, mask, 0, timeout);190}191#define intel_de_wait_for_clear(p,...) __intel_de_wait_for_clear(__to_intel_display(p), __VA_ARGS__)192 193/*194 * Unlocked mmio-accessors, think carefully before using these.195 *196 * Certain architectures will die if the same cacheline is concurrently accessed197 * by different clients (e.g. on Ivybridge). Access to registers should198 * therefore generally be serialised, by either the dev_priv->uncore.lock or199 * a more localised lock guarding all access to that bank of registers.200 */201static inline u32202__intel_de_read_fw(struct intel_display *display, i915_reg_t reg)203{204 u32 val;205 206 val = intel_uncore_read_fw(__to_uncore(display), reg);207 trace_i915_reg_rw(false, reg, val, sizeof(val), true);208 209 return val;210}211#define intel_de_read_fw(p,...) __intel_de_read_fw(__to_intel_display(p), __VA_ARGS__)212 213static inline void214__intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)215{216 trace_i915_reg_rw(true, reg, val, sizeof(val), true);217 intel_uncore_write_fw(__to_uncore(display), reg, val);218}219#define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)220 221static inline u32222__intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)223{224 return intel_uncore_read_notrace(__to_uncore(display), reg);225}226#define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__)227 228static inline void229__intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,230 u32 val)231{232 intel_uncore_write_notrace(__to_uncore(display), reg, val);233}234#define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)235 236#endif /* __INTEL_DE_H__ */237