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1/*2 * Copyright © 2006-2019 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS21 * IN THE SOFTWARE.22 *23 */24 25#ifndef _INTEL_DISPLAY_H_26#define _INTEL_DISPLAY_H_27 28#include <drm/drm_util.h>29 30#include "i915_reg_defs.h"31#include "intel_display_limits.h"32 33enum drm_scaling_filter;34struct dpll;35struct drm_atomic_state;36struct drm_connector;37struct drm_device;38struct drm_display_mode;39struct drm_encoder;40struct drm_file;41struct drm_format_info;42struct drm_framebuffer;43struct drm_i915_gem_object;44struct drm_i915_private;45struct drm_mode_fb_cmd2;46struct drm_modeset_acquire_ctx;47struct drm_plane;48struct drm_plane_state;49struct i915_address_space;50struct i915_gtt_view;51struct intel_atomic_state;52struct intel_crtc;53struct intel_crtc_state;54struct intel_digital_port;55struct intel_dp;56struct intel_encoder;57struct intel_initial_plane_config;58struct intel_link_m_n;59struct intel_plane;60struct intel_plane_state;61struct intel_power_domain_mask;62struct intel_remapped_info;63struct intel_rotation_info;64struct pci_dev;65struct work_struct;66 67 68#define pipe_name(p) ((p) + 'A')69 70static inline const char *transcoder_name(enum transcoder transcoder)71{72 switch (transcoder) {73 case TRANSCODER_A:74 return "A";75 case TRANSCODER_B:76 return "B";77 case TRANSCODER_C:78 return "C";79 case TRANSCODER_D:80 return "D";81 case TRANSCODER_EDP:82 return "EDP";83 case TRANSCODER_DSI_A:84 return "DSI A";85 case TRANSCODER_DSI_C:86 return "DSI C";87 default:88 return "<invalid>";89 }90}91 92static inline bool transcoder_is_dsi(enum transcoder transcoder)93{94 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;95}96 97/*98 * Global legacy plane identifier. Valid only for primary/sprite99 * planes on pre-g4x, and only for primary planes on g4x-bdw.100 */101enum i9xx_plane_id {102 PLANE_A,103 PLANE_B,104 PLANE_C,105};106 107#define plane_name(p) ((p) + 'A')108 109#define for_each_plane_id_on_crtc(__crtc, __p) \110 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \111 for_each_if((__crtc)->plane_ids_mask & BIT(__p))112 113#define for_each_dbuf_slice(__dev_priv, __slice) \114 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \115 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))116 117#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \118 for_each_dbuf_slice((__dev_priv), (__slice)) \119 for_each_if((__mask) & BIT(__slice))120 121#define port_name(p) ((p) + 'A')122 123/*124 * Ports identifier referenced from other drivers.125 * Expected to remain stable over time126 */127static inline const char *port_identifier(enum port port)128{129 switch (port) {130 case PORT_A:131 return "Port A";132 case PORT_B:133 return "Port B";134 case PORT_C:135 return "Port C";136 case PORT_D:137 return "Port D";138 case PORT_E:139 return "Port E";140 case PORT_F:141 return "Port F";142 case PORT_G:143 return "Port G";144 case PORT_H:145 return "Port H";146 case PORT_I:147 return "Port I";148 default:149 return "<invalid>";150 }151}152 153enum tc_port {154 TC_PORT_NONE = -1,155 156 TC_PORT_1 = 0,157 TC_PORT_2,158 TC_PORT_3,159 TC_PORT_4,160 TC_PORT_5,161 TC_PORT_6,162 163 I915_MAX_TC_PORTS164};165 166enum aux_ch {167 AUX_CH_NONE = -1,168 169 AUX_CH_A,170 AUX_CH_B,171 AUX_CH_C,172 AUX_CH_D,173 AUX_CH_E, /* ICL+ */174 AUX_CH_F,175 AUX_CH_G,176 AUX_CH_H,177 AUX_CH_I,178 179 /* tgl+ */180 AUX_CH_USBC1 = AUX_CH_D,181 AUX_CH_USBC2,182 AUX_CH_USBC3,183 AUX_CH_USBC4,184 AUX_CH_USBC5,185 AUX_CH_USBC6,186 187 /* XE_LPD repositions D/E offsets and bitfields */188 AUX_CH_D_XELPD = AUX_CH_USBC5,189 AUX_CH_E_XELPD,190};191 192enum phy {193 PHY_NONE = -1,194 195 PHY_A = 0,196 PHY_B,197 PHY_C,198 PHY_D,199 PHY_E,200 PHY_F,201 PHY_G,202 PHY_H,203 PHY_I,204 205 I915_MAX_PHYS206};207 208#define phy_name(a) ((a) + 'A')209 210enum phy_fia {211 FIA1,212 FIA2,213 FIA3,214};215 216#define for_each_hpd_pin(__pin) \217 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)218 219#define for_each_pipe(__dev_priv, __p) \220 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \221 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))222 223#define for_each_pipe_masked(__dev_priv, __p, __mask) \224 for_each_pipe(__dev_priv, __p) \225 for_each_if((__mask) & BIT(__p))226 227#define for_each_cpu_transcoder(__dev_priv, __t) \228 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \229 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))230 231#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \232 for_each_cpu_transcoder(__dev_priv, __t) \233 for_each_if ((__mask) & BIT(__t))234 235#define for_each_sprite(__dev_priv, __p, __s) \236 for ((__s) = 0; \237 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \238 (__s)++)239 240#define for_each_port(__port) \241 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)242 243#define for_each_port_masked(__port, __ports_mask) \244 for_each_port(__port) \245 for_each_if((__ports_mask) & BIT(__port))246 247#define for_each_phy_masked(__phy, __phys_mask) \248 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \249 for_each_if((__phys_mask) & BIT(__phy))250 251#define for_each_crtc(dev, crtc) \252 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)253 254#define for_each_intel_plane(dev, intel_plane) \255 list_for_each_entry(intel_plane, \256 &(dev)->mode_config.plane_list, \257 base.head)258 259#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \260 list_for_each_entry(intel_plane, \261 &(dev)->mode_config.plane_list, \262 base.head) \263 for_each_if((plane_mask) & \264 drm_plane_mask(&intel_plane->base))265 266#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \267 list_for_each_entry(intel_plane, \268 &(dev)->mode_config.plane_list, \269 base.head) \270 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)271 272#define for_each_intel_crtc(dev, intel_crtc) \273 list_for_each_entry(intel_crtc, \274 &(dev)->mode_config.crtc_list, \275 base.head)276 277#define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \278 list_for_each_entry(intel_crtc, \279 &(dev)->mode_config.crtc_list, \280 base.head) \281 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))282 283#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \284 list_for_each_entry_reverse((intel_crtc), \285 &(dev)->mode_config.crtc_list, \286 base.head) \287 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))288 289#define for_each_intel_encoder(dev, intel_encoder) \290 list_for_each_entry(intel_encoder, \291 &(dev)->mode_config.encoder_list, \292 base.head)293 294#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \295 list_for_each_entry(intel_encoder, \296 &(dev)->mode_config.encoder_list, \297 base.head) \298 for_each_if((encoder_mask) & \299 drm_encoder_mask(&intel_encoder->base))300 301#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \302 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \303 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \304 intel_encoder_can_psr(intel_encoder))305 306#define for_each_intel_dp(dev, intel_encoder) \307 for_each_intel_encoder(dev, intel_encoder) \308 for_each_if(intel_encoder_is_dp(intel_encoder))309 310#define for_each_intel_encoder_with_psr(dev, intel_encoder) \311 for_each_intel_encoder((dev), (intel_encoder)) \312 for_each_if(intel_encoder_can_psr(intel_encoder))313 314#define for_each_intel_connector_iter(intel_connector, iter) \315 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))316 317#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \318 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \319 for_each_if((intel_encoder)->base.crtc == (__crtc))320 321#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \322 for ((__i) = 0; \323 (__i) < (__state)->base.dev->mode_config.num_total_plane && \324 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \325 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \326 (__i)++) \327 for_each_if(plane)328 329#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \330 for ((__i) = 0; \331 (__i) < (__state)->base.dev->mode_config.num_crtc && \332 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \333 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \334 (__i)++) \335 for_each_if(crtc)336 337#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \338 for ((__i) = 0; \339 (__i) < (__state)->base.dev->mode_config.num_total_plane && \340 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \341 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \342 (__i)++) \343 for_each_if(plane)344 345#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \346 for ((__i) = 0; \347 (__i) < (__state)->base.dev->mode_config.num_crtc && \348 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \349 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \350 (__i)++) \351 for_each_if(crtc)352 353#define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \354 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \355 (__i) >= 0 && \356 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \357 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \358 (__i)--) \359 for_each_if(crtc)360 361#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \362 for ((__i) = 0; \363 (__i) < (__state)->base.dev->mode_config.num_total_plane && \364 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \365 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \366 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \367 (__i)++) \368 for_each_if(plane)369 370#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \371 for ((__i) = 0; \372 (__i) < (__state)->base.dev->mode_config.num_crtc && \373 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \374 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \375 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \376 (__i)++) \377 for_each_if(crtc)378 379#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \380 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \381 (__i) >= 0 && \382 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \383 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \384 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \385 (__i)--) \386 for_each_if(crtc)387 388#define intel_atomic_crtc_state_for_each_plane_state( \389 plane, plane_state, \390 crtc_state) \391 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \392 ((crtc_state)->uapi.plane_mask)) \393 for_each_if ((plane_state = \394 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))395 396#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \397 for ((__i) = 0; \398 (__i) < (__state)->base.num_connector; \399 (__i)++) \400 for_each_if ((__state)->base.connectors[__i].ptr && \401 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \402 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))403 404int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);405int intel_atomic_add_affected_planes(struct intel_atomic_state *state,406 struct intel_crtc *crtc);407u8 intel_calc_active_pipes(struct intel_atomic_state *state,408 u8 active_pipes);409void intel_link_compute_m_n(u16 bpp, int nlanes,410 int pixel_clock, int link_clock,411 int bw_overhead,412 struct intel_link_m_n *m_n);413u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,414 u32 pixel_format, u64 modifier);415enum drm_mode_status416intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,417 const struct drm_display_mode *mode,418 bool joiner);419enum drm_mode_status420intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,421 const struct drm_display_mode *mode);422enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);423bool is_trans_port_sync_mode(const struct intel_crtc_state *state);424bool is_trans_port_sync_master(const struct intel_crtc_state *state);425u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);426bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);427bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);428u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);429struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);430bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);431bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,432 const struct intel_crtc_state *pipe_config,433 bool fastset);434 435void intel_plane_destroy(struct drm_plane *plane);436void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);437void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);438void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);439void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);440void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);441void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);442int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);443int vlv_get_cck_clock(struct drm_i915_private *dev_priv,444 const char *name, u32 reg, int ref_freq);445int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,446 const char *name, u32 reg);447void intel_init_display_hooks(struct drm_i915_private *dev_priv);448unsigned int intel_fb_xy_to_linear(int x, int y,449 const struct intel_plane_state *state,450 int plane);451void intel_add_fb_offsets(int *x, int *y,452 const struct intel_plane_state *state, int plane);453unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);454unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);455bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);456void intel_encoder_destroy(struct drm_encoder *encoder);457struct drm_display_mode *458intel_encoder_current_mode(struct intel_encoder *encoder);459void intel_encoder_get_config(struct intel_encoder *encoder,460 struct intel_crtc_state *crtc_state);461bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);462bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);463bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);464enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,465 enum port port);466 467enum phy intel_encoder_to_phy(struct intel_encoder *encoder);468bool intel_encoder_is_combo(struct intel_encoder *encoder);469bool intel_encoder_is_snps(struct intel_encoder *encoder);470bool intel_encoder_is_tc(struct intel_encoder *encoder);471enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);472 473int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,474 struct drm_file *file_priv);475 476int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);477void vlv_wait_port_ready(struct drm_i915_private *dev_priv,478 struct intel_digital_port *dig_port,479 unsigned int expected_mask);480struct drm_framebuffer *481intel_framebuffer_create(struct drm_i915_gem_object *obj,482 struct drm_mode_fb_cmd2 *mode_cmd);483 484bool intel_fuzzy_clock_check(int clock1, int clock2);485 486void intel_zero_m_n(struct intel_link_m_n *m_n);487void intel_set_m_n(struct drm_i915_private *i915,488 const struct intel_link_m_n *m_n,489 i915_reg_t data_m_reg, i915_reg_t data_n_reg,490 i915_reg_t link_m_reg, i915_reg_t link_n_reg);491void intel_get_m_n(struct drm_i915_private *i915,492 struct intel_link_m_n *m_n,493 i915_reg_t data_m_reg, i915_reg_t data_n_reg,494 i915_reg_t link_m_reg, i915_reg_t link_n_reg);495bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,496 enum transcoder transcoder);497void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,498 enum transcoder cpu_transcoder,499 const struct intel_link_m_n *m_n);500void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,501 enum transcoder cpu_transcoder,502 const struct intel_link_m_n *m_n);503void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,504 enum transcoder cpu_transcoder,505 struct intel_link_m_n *m_n);506void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,507 enum transcoder cpu_transcoder,508 struct intel_link_m_n *m_n);509int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);510int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);511enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);512enum intel_display_power_domain513intel_aux_power_domain(struct intel_digital_port *dig_port);514void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,515 struct intel_crtc_state *crtc_state);516void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);517 518int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);519unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);520 521bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);522 523struct intel_encoder *524intel_get_crtc_new_encoder(const struct intel_atomic_state *state,525 const struct intel_crtc_state *crtc_state);526void intel_plane_disable_noatomic(struct intel_crtc *crtc,527 struct intel_plane *plane);528void intel_set_plane_visible(struct intel_crtc_state *crtc_state,529 struct intel_plane_state *plane_state,530 bool visible);531void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);532 533void intel_update_watermarks(struct drm_i915_private *i915);534 535bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,536 struct intel_crtc *crtc);537 538/* modesetting */539int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,540 const char *reason, u8 pipe_mask);541int intel_modeset_all_pipes_late(struct intel_atomic_state *state,542 const char *reason);543int intel_modeset_commit_pipes(struct drm_i915_private *i915,544 u8 pipe_mask,545 struct drm_modeset_acquire_ctx *ctx);546void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,547 struct intel_power_domain_mask *old_domains);548void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,549 struct intel_power_domain_mask *domains);550 551/* interface for intel_display_driver.c */552void intel_setup_outputs(struct drm_i915_private *i915);553int intel_initial_commit(struct drm_device *dev);554void intel_panel_sanitize_ssc(struct drm_i915_private *i915);555void intel_update_czclk(struct drm_i915_private *i915);556void intel_atomic_helper_free_state_worker(struct work_struct *work);557enum drm_mode_status intel_mode_valid(struct drm_device *dev,558 const struct drm_display_mode *mode);559int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,560 bool nonblock);561 562void intel_hpd_poll_fini(struct drm_i915_private *i915);563 564/* modesetting asserts */565void assert_transcoder(struct drm_i915_private *dev_priv,566 enum transcoder cpu_transcoder, bool state);567#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)568#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)569 570bool assert_port_valid(struct drm_i915_private *i915, enum port port);571 572/*573 * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity574 * checks to check for unexpected conditions which may not necessarily be a user575 * visible problem. This will either WARN() or DRM_ERROR() depending on the576 * verbose_state_checks module param, to enable distros and users to tailor577 * their preferred amount of i915 abrt spam.578 */579#define I915_STATE_WARN(__i915, condition, format...) ({ \580 struct drm_device *drm = &(__i915)->drm; \581 int __ret_warn_on = !!(condition); \582 if (unlikely(__ret_warn_on)) \583 if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \584 drm_err(drm, format); \585 unlikely(__ret_warn_on); \586})587 588bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);589 590#endif591