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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2023 Intel Corporation4 */5 6#include "gt/intel_rps.h"7#include "i915_drv.h"8#include "i915_irq.h"9#include "i915_reg.h"10#include "icl_dsi_regs.h"11#include "intel_crtc.h"12#include "intel_de.h"13#include "intel_display_irq.h"14#include "intel_display_trace.h"15#include "intel_display_types.h"16#include "intel_dp_aux.h"17#include "intel_dsb.h"18#include "intel_fdi_regs.h"19#include "intel_fifo_underrun.h"20#include "intel_gmbus.h"21#include "intel_hotplug_irq.h"22#include "intel_pipe_crc_regs.h"23#include "intel_pmdemand.h"24#include "intel_psr.h"25#include "intel_psr_regs.h"26 27static void28intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)29{30 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);31 32 drm_crtc_handle_vblank(&crtc->base);33}34 35/**36 * ilk_update_display_irq - update DEIMR37 * @dev_priv: driver private38 * @interrupt_mask: mask of interrupt bits to update39 * @enabled_irq_mask: mask of interrupt bits to enable40 */41void ilk_update_display_irq(struct drm_i915_private *dev_priv,42 u32 interrupt_mask, u32 enabled_irq_mask)43{44 u32 new_val;45 46 lockdep_assert_held(&dev_priv->irq_lock);47 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);48 49 new_val = dev_priv->irq_mask;50 new_val &= ~interrupt_mask;51 new_val |= (~enabled_irq_mask & interrupt_mask);52 53 if (new_val != dev_priv->irq_mask &&54 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {55 dev_priv->irq_mask = new_val;56 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask);57 intel_uncore_posting_read(&dev_priv->uncore, DEIMR);58 }59}60 61void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits)62{63 ilk_update_display_irq(i915, bits, bits);64}65 66void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits)67{68 ilk_update_display_irq(i915, bits, 0);69}70 71/**72 * bdw_update_port_irq - update DE port interrupt73 * @dev_priv: driver private74 * @interrupt_mask: mask of interrupt bits to update75 * @enabled_irq_mask: mask of interrupt bits to enable76 */77void bdw_update_port_irq(struct drm_i915_private *dev_priv,78 u32 interrupt_mask, u32 enabled_irq_mask)79{80 u32 new_val;81 u32 old_val;82 83 lockdep_assert_held(&dev_priv->irq_lock);84 85 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);86 87 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))88 return;89 90 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);91 92 new_val = old_val;93 new_val &= ~interrupt_mask;94 new_val |= (~enabled_irq_mask & interrupt_mask);95 96 if (new_val != old_val) {97 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val);98 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR);99 }100}101 102/**103 * bdw_update_pipe_irq - update DE pipe interrupt104 * @dev_priv: driver private105 * @pipe: pipe whose interrupt to update106 * @interrupt_mask: mask of interrupt bits to update107 * @enabled_irq_mask: mask of interrupt bits to enable108 */109static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,110 enum pipe pipe, u32 interrupt_mask,111 u32 enabled_irq_mask)112{113 u32 new_val;114 115 lockdep_assert_held(&dev_priv->irq_lock);116 117 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);118 119 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))120 return;121 122 new_val = dev_priv->display.irq.de_irq_mask[pipe];123 new_val &= ~interrupt_mask;124 new_val |= (~enabled_irq_mask & interrupt_mask);125 126 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) {127 dev_priv->display.irq.de_irq_mask[pipe] = new_val;128 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe),129 dev_priv->display.irq.de_irq_mask[pipe]);130 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe));131 }132}133 134void bdw_enable_pipe_irq(struct drm_i915_private *i915,135 enum pipe pipe, u32 bits)136{137 bdw_update_pipe_irq(i915, pipe, bits, bits);138}139 140void bdw_disable_pipe_irq(struct drm_i915_private *i915,141 enum pipe pipe, u32 bits)142{143 bdw_update_pipe_irq(i915, pipe, bits, 0);144}145 146/**147 * ibx_display_interrupt_update - update SDEIMR148 * @dev_priv: driver private149 * @interrupt_mask: mask of interrupt bits to update150 * @enabled_irq_mask: mask of interrupt bits to enable151 */152void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,153 u32 interrupt_mask,154 u32 enabled_irq_mask)155{156 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR);157 158 sdeimr &= ~interrupt_mask;159 sdeimr |= (~enabled_irq_mask & interrupt_mask);160 161 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);162 163 lockdep_assert_held(&dev_priv->irq_lock);164 165 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))166 return;167 168 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr);169 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR);170}171 172void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits)173{174 ibx_display_interrupt_update(i915, bits, bits);175}176 177void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits)178{179 ibx_display_interrupt_update(i915, bits, 0);180}181 182u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,183 enum pipe pipe)184{185 u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe];186 u32 enable_mask = status_mask << 16;187 188 lockdep_assert_held(&dev_priv->irq_lock);189 190 if (DISPLAY_VER(dev_priv) < 5)191 goto out;192 193 /*194 * On pipe A we don't support the PSR interrupt yet,195 * on pipe B and C the same bit MBZ.196 */197 if (drm_WARN_ON_ONCE(&dev_priv->drm,198 status_mask & PIPE_A_PSR_STATUS_VLV))199 return 0;200 /*201 * On pipe B and C we don't support the PSR interrupt yet, on pipe202 * A the same bit is for perf counters which we don't use either.203 */204 if (drm_WARN_ON_ONCE(&dev_priv->drm,205 status_mask & PIPE_B_PSR_STATUS_VLV))206 return 0;207 208 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |209 SPRITE0_FLIP_DONE_INT_EN_VLV |210 SPRITE1_FLIP_DONE_INT_EN_VLV);211 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)212 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;213 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)214 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;215 216out:217 drm_WARN_ONCE(&dev_priv->drm,218 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||219 status_mask & ~PIPESTAT_INT_STATUS_MASK,220 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",221 pipe_name(pipe), enable_mask, status_mask);222 223 return enable_mask;224}225 226void i915_enable_pipestat(struct drm_i915_private *dev_priv,227 enum pipe pipe, u32 status_mask)228{229 i915_reg_t reg = PIPESTAT(dev_priv, pipe);230 u32 enable_mask;231 232 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,233 "pipe %c: status_mask=0x%x\n",234 pipe_name(pipe), status_mask);235 236 lockdep_assert_held(&dev_priv->irq_lock);237 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));238 239 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask)240 return;241 242 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask;243 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);244 245 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);246 intel_uncore_posting_read(&dev_priv->uncore, reg);247}248 249void i915_disable_pipestat(struct drm_i915_private *dev_priv,250 enum pipe pipe, u32 status_mask)251{252 i915_reg_t reg = PIPESTAT(dev_priv, pipe);253 u32 enable_mask;254 255 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,256 "pipe %c: status_mask=0x%x\n",257 pipe_name(pipe), status_mask);258 259 lockdep_assert_held(&dev_priv->irq_lock);260 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));261 262 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0)263 return;264 265 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask;266 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);267 268 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask);269 intel_uncore_posting_read(&dev_priv->uncore, reg);270}271 272static bool i915_has_asle(struct drm_i915_private *i915)273{274 struct intel_display *display = &i915->display;275 276 if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915))277 return false;278 279 return intel_opregion_asle_present(display);280}281 282/**283 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion284 * @dev_priv: i915 device private285 */286void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)287{288 if (!i915_has_asle(dev_priv))289 return;290 291 spin_lock_irq(&dev_priv->irq_lock);292 293 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);294 if (DISPLAY_VER(dev_priv) >= 4)295 i915_enable_pipestat(dev_priv, PIPE_A,296 PIPE_LEGACY_BLC_EVENT_STATUS);297 298 spin_unlock_irq(&dev_priv->irq_lock);299}300 301#if defined(CONFIG_DEBUG_FS)302static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,303 enum pipe pipe,304 u32 crc0, u32 crc1,305 u32 crc2, u32 crc3,306 u32 crc4)307{308 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);309 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;310 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };311 312 trace_intel_pipe_crc(crtc, crcs);313 314 spin_lock(&pipe_crc->lock);315 /*316 * For some not yet identified reason, the first CRC is317 * bonkers. So let's just wait for the next vblank and read318 * out the buggy result.319 *320 * On GEN8+ sometimes the second CRC is bonkers as well, so321 * don't trust that one either.322 */323 if (pipe_crc->skipped <= 0 ||324 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {325 pipe_crc->skipped++;326 spin_unlock(&pipe_crc->lock);327 return;328 }329 spin_unlock(&pipe_crc->lock);330 331 drm_crtc_add_crc_entry(&crtc->base, true,332 drm_crtc_accurate_vblank_count(&crtc->base),333 crcs);334}335#else336static inline void337display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,338 enum pipe pipe,339 u32 crc0, u32 crc1,340 u32 crc2, u32 crc3,341 u32 crc4) {}342#endif343 344static void flip_done_handler(struct drm_i915_private *i915,345 enum pipe pipe)346{347 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);348 349 spin_lock(&i915->drm.event_lock);350 351 if (crtc->flip_done_event) {352 trace_intel_crtc_flip_done(crtc);353 drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event);354 crtc->flip_done_event = NULL;355 }356 357 spin_unlock(&i915->drm.event_lock);358}359 360static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,361 enum pipe pipe)362{363 display_pipe_crc_irq_handler(dev_priv, pipe,364 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)),365 0, 0, 0, 0);366}367 368static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,369 enum pipe pipe)370{371 display_pipe_crc_irq_handler(dev_priv, pipe,372 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),373 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)),374 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)),375 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)),376 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe)));377}378 379static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,380 enum pipe pipe)381{382 u32 res1, res2;383 384 if (DISPLAY_VER(dev_priv) >= 3)385 res1 = intel_uncore_read(&dev_priv->uncore,386 PIPE_CRC_RES_RES1_I915(dev_priv, pipe));387 else388 res1 = 0;389 390 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))391 res2 = intel_uncore_read(&dev_priv->uncore,392 PIPE_CRC_RES_RES2_G4X(dev_priv, pipe));393 else394 res2 = 0;395 396 display_pipe_crc_irq_handler(dev_priv, pipe,397 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)),398 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)),399 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)),400 res1, res2);401}402 403void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)404{405 enum pipe pipe;406 407 for_each_pipe(dev_priv, pipe) {408 intel_uncore_write(&dev_priv->uncore,409 PIPESTAT(dev_priv, pipe),410 PIPESTAT_INT_STATUS_MASK |411 PIPE_FIFO_UNDERRUN_STATUS);412 413 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0;414 }415}416 417void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,418 u32 iir, u32 pipe_stats[I915_MAX_PIPES])419{420 enum pipe pipe;421 422 spin_lock(&dev_priv->irq_lock);423 424 if (!dev_priv->display.irq.display_irqs_enabled) {425 spin_unlock(&dev_priv->irq_lock);426 return;427 }428 429 for_each_pipe(dev_priv, pipe) {430 i915_reg_t reg;431 u32 status_mask, enable_mask, iir_bit = 0;432 433 /*434 * PIPESTAT bits get signalled even when the interrupt is435 * disabled with the mask bits, and some of the status bits do436 * not generate interrupts at all (like the underrun bit). Hence437 * we need to be careful that we only handle what we want to438 * handle.439 */440 441 /* fifo underruns are filterered in the underrun handler. */442 status_mask = PIPE_FIFO_UNDERRUN_STATUS;443 444 switch (pipe) {445 default:446 case PIPE_A:447 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;448 break;449 case PIPE_B:450 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;451 break;452 case PIPE_C:453 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;454 break;455 }456 if (iir & iir_bit)457 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe];458 459 if (!status_mask)460 continue;461 462 reg = PIPESTAT(dev_priv, pipe);463 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;464 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);465 466 /*467 * Clear the PIPE*STAT regs before the IIR468 *469 * Toggle the enable bits to make sure we get an470 * edge in the ISR pipe event bit if we don't clear471 * all the enabled status bits. Otherwise the edge472 * triggered IIR on i965/g4x wouldn't notice that473 * an interrupt is still pending.474 */475 if (pipe_stats[pipe]) {476 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);477 intel_uncore_write(&dev_priv->uncore, reg, enable_mask);478 }479 }480 spin_unlock(&dev_priv->irq_lock);481}482 483void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,484 u16 iir, u32 pipe_stats[I915_MAX_PIPES])485{486 enum pipe pipe;487 488 for_each_pipe(dev_priv, pipe) {489 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)490 intel_handle_vblank(dev_priv, pipe);491 492 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)493 i9xx_pipe_crc_irq_handler(dev_priv, pipe);494 495 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)496 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);497 }498}499 500void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,501 u32 iir, u32 pipe_stats[I915_MAX_PIPES])502{503 struct intel_display *display = &dev_priv->display;504 505 bool blc_event = false;506 enum pipe pipe;507 508 for_each_pipe(dev_priv, pipe) {509 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)510 intel_handle_vblank(dev_priv, pipe);511 512 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)513 blc_event = true;514 515 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)516 i9xx_pipe_crc_irq_handler(dev_priv, pipe);517 518 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)519 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);520 }521 522 if (blc_event || (iir & I915_ASLE_INTERRUPT))523 intel_opregion_asle_intr(display);524}525 526void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,527 u32 iir, u32 pipe_stats[I915_MAX_PIPES])528{529 struct intel_display *display = &dev_priv->display;530 bool blc_event = false;531 enum pipe pipe;532 533 for_each_pipe(dev_priv, pipe) {534 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)535 intel_handle_vblank(dev_priv, pipe);536 537 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)538 blc_event = true;539 540 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)541 i9xx_pipe_crc_irq_handler(dev_priv, pipe);542 543 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)544 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);545 }546 547 if (blc_event || (iir & I915_ASLE_INTERRUPT))548 intel_opregion_asle_intr(display);549 550 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)551 intel_gmbus_irq_handler(dev_priv);552}553 554void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,555 u32 pipe_stats[I915_MAX_PIPES])556{557 enum pipe pipe;558 559 for_each_pipe(dev_priv, pipe) {560 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)561 intel_handle_vblank(dev_priv, pipe);562 563 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)564 flip_done_handler(dev_priv, pipe);565 566 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)567 i9xx_pipe_crc_irq_handler(dev_priv, pipe);568 569 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)570 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);571 }572 573 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)574 intel_gmbus_irq_handler(dev_priv);575}576 577static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)578{579 struct intel_display *display = &dev_priv->display;580 enum pipe pipe;581 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;582 583 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);584 585 if (pch_iir & SDE_AUDIO_POWER_MASK) {586 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>587 SDE_AUDIO_POWER_SHIFT);588 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",589 port_name(port));590 }591 592 if (pch_iir & SDE_AUX_MASK)593 intel_dp_aux_irq_handler(display);594 595 if (pch_iir & SDE_GMBUS)596 intel_gmbus_irq_handler(dev_priv);597 598 if (pch_iir & SDE_AUDIO_HDCP_MASK)599 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");600 601 if (pch_iir & SDE_AUDIO_TRANS_MASK)602 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");603 604 if (pch_iir & SDE_POISON)605 drm_err(&dev_priv->drm, "PCH poison interrupt\n");606 607 if (pch_iir & SDE_FDI_MASK) {608 for_each_pipe(dev_priv, pipe)609 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",610 pipe_name(pipe),611 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));612 }613 614 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))615 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");616 617 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))618 drm_dbg(&dev_priv->drm,619 "PCH transcoder CRC error interrupt\n");620 621 if (pch_iir & SDE_TRANSA_FIFO_UNDER)622 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);623 624 if (pch_iir & SDE_TRANSB_FIFO_UNDER)625 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);626}627 628static void ivb_err_int_handler(struct drm_i915_private *dev_priv)629{630 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT);631 enum pipe pipe;632 633 if (err_int & ERR_INT_POISON)634 drm_err(&dev_priv->drm, "Poison interrupt\n");635 636 for_each_pipe(dev_priv, pipe) {637 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))638 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);639 640 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {641 if (IS_IVYBRIDGE(dev_priv))642 ivb_pipe_crc_irq_handler(dev_priv, pipe);643 else644 hsw_pipe_crc_irq_handler(dev_priv, pipe);645 }646 }647 648 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int);649}650 651static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)652{653 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT);654 enum pipe pipe;655 656 if (serr_int & SERR_INT_POISON)657 drm_err(&dev_priv->drm, "PCH poison interrupt\n");658 659 for_each_pipe(dev_priv, pipe)660 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))661 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);662 663 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int);664}665 666static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)667{668 struct intel_display *display = &dev_priv->display;669 enum pipe pipe;670 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;671 672 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);673 674 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {675 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>676 SDE_AUDIO_POWER_SHIFT_CPT);677 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",678 port_name(port));679 }680 681 if (pch_iir & SDE_AUX_MASK_CPT)682 intel_dp_aux_irq_handler(display);683 684 if (pch_iir & SDE_GMBUS_CPT)685 intel_gmbus_irq_handler(dev_priv);686 687 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)688 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");689 690 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)691 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");692 693 if (pch_iir & SDE_FDI_MASK_CPT) {694 for_each_pipe(dev_priv, pipe)695 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",696 pipe_name(pipe),697 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe)));698 }699 700 if (pch_iir & SDE_ERROR_CPT)701 cpt_serr_int_handler(dev_priv);702}703 704void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)705{706 struct intel_display *display = &dev_priv->display;707 enum pipe pipe;708 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;709 710 if (hotplug_trigger)711 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);712 713 if (de_iir & DE_AUX_CHANNEL_A)714 intel_dp_aux_irq_handler(display);715 716 if (de_iir & DE_GSE)717 intel_opregion_asle_intr(display);718 719 if (de_iir & DE_POISON)720 drm_err(&dev_priv->drm, "Poison interrupt\n");721 722 for_each_pipe(dev_priv, pipe) {723 if (de_iir & DE_PIPE_VBLANK(pipe))724 intel_handle_vblank(dev_priv, pipe);725 726 if (de_iir & DE_PLANE_FLIP_DONE(pipe))727 flip_done_handler(dev_priv, pipe);728 729 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))730 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);731 732 if (de_iir & DE_PIPE_CRC_DONE(pipe))733 i9xx_pipe_crc_irq_handler(dev_priv, pipe);734 }735 736 /* check event from PCH */737 if (de_iir & DE_PCH_EVENT) {738 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);739 740 if (HAS_PCH_CPT(dev_priv))741 cpt_irq_handler(dev_priv, pch_iir);742 else743 ibx_irq_handler(dev_priv, pch_iir);744 745 /* should clear PCH hotplug event before clear CPU irq */746 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);747 }748 749 if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)750 gen5_rps_irq_handler(&to_gt(dev_priv)->rps);751}752 753void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)754{755 struct intel_display *display = &dev_priv->display;756 enum pipe pipe;757 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;758 759 if (hotplug_trigger)760 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);761 762 if (de_iir & DE_ERR_INT_IVB)763 ivb_err_int_handler(dev_priv);764 765 if (de_iir & DE_EDP_PSR_INT_HSW) {766 struct intel_encoder *encoder;767 768 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {769 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);770 u32 psr_iir;771 772 psr_iir = intel_uncore_rmw(&dev_priv->uncore,773 EDP_PSR_IIR, 0, 0);774 intel_psr_irq_handler(intel_dp, psr_iir);775 break;776 }777 }778 779 if (de_iir & DE_AUX_CHANNEL_A_IVB)780 intel_dp_aux_irq_handler(display);781 782 if (de_iir & DE_GSE_IVB)783 intel_opregion_asle_intr(display);784 785 for_each_pipe(dev_priv, pipe) {786 if (de_iir & DE_PIPE_VBLANK_IVB(pipe))787 intel_handle_vblank(dev_priv, pipe);788 789 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))790 flip_done_handler(dev_priv, pipe);791 }792 793 /* check event from PCH */794 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {795 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR);796 797 cpt_irq_handler(dev_priv, pch_iir);798 799 /* clear PCH hotplug event before clear CPU irq */800 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);801 }802}803 804static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)805{806 u32 mask;807 808 if (DISPLAY_VER(dev_priv) >= 20)809 return 0;810 else if (DISPLAY_VER(dev_priv) >= 14)811 return TGL_DE_PORT_AUX_DDIA |812 TGL_DE_PORT_AUX_DDIB;813 else if (DISPLAY_VER(dev_priv) >= 13)814 return TGL_DE_PORT_AUX_DDIA |815 TGL_DE_PORT_AUX_DDIB |816 TGL_DE_PORT_AUX_DDIC |817 XELPD_DE_PORT_AUX_DDID |818 XELPD_DE_PORT_AUX_DDIE |819 TGL_DE_PORT_AUX_USBC1 |820 TGL_DE_PORT_AUX_USBC2 |821 TGL_DE_PORT_AUX_USBC3 |822 TGL_DE_PORT_AUX_USBC4;823 else if (DISPLAY_VER(dev_priv) >= 12)824 return TGL_DE_PORT_AUX_DDIA |825 TGL_DE_PORT_AUX_DDIB |826 TGL_DE_PORT_AUX_DDIC |827 TGL_DE_PORT_AUX_USBC1 |828 TGL_DE_PORT_AUX_USBC2 |829 TGL_DE_PORT_AUX_USBC3 |830 TGL_DE_PORT_AUX_USBC4 |831 TGL_DE_PORT_AUX_USBC5 |832 TGL_DE_PORT_AUX_USBC6;833 834 mask = GEN8_AUX_CHANNEL_A;835 if (DISPLAY_VER(dev_priv) >= 9)836 mask |= GEN9_AUX_CHANNEL_B |837 GEN9_AUX_CHANNEL_C |838 GEN9_AUX_CHANNEL_D;839 840 if (DISPLAY_VER(dev_priv) == 11) {841 mask |= ICL_AUX_CHANNEL_F;842 mask |= ICL_AUX_CHANNEL_E;843 }844 845 return mask;846}847 848static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)849{850 if (DISPLAY_VER(dev_priv) >= 14)851 return MTL_PIPEDMC_ATS_FAULT |852 MTL_PLANE_ATS_FAULT |853 GEN12_PIPEDMC_FAULT |854 GEN9_PIPE_CURSOR_FAULT |855 GEN11_PIPE_PLANE5_FAULT |856 GEN9_PIPE_PLANE4_FAULT |857 GEN9_PIPE_PLANE3_FAULT |858 GEN9_PIPE_PLANE2_FAULT |859 GEN9_PIPE_PLANE1_FAULT;860 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))861 return GEN12_PIPEDMC_FAULT |862 GEN9_PIPE_CURSOR_FAULT |863 GEN11_PIPE_PLANE5_FAULT |864 GEN9_PIPE_PLANE4_FAULT |865 GEN9_PIPE_PLANE3_FAULT |866 GEN9_PIPE_PLANE2_FAULT |867 GEN9_PIPE_PLANE1_FAULT;868 else if (DISPLAY_VER(dev_priv) == 12)869 return GEN12_PIPEDMC_FAULT |870 GEN9_PIPE_CURSOR_FAULT |871 GEN11_PIPE_PLANE7_FAULT |872 GEN11_PIPE_PLANE6_FAULT |873 GEN11_PIPE_PLANE5_FAULT |874 GEN9_PIPE_PLANE4_FAULT |875 GEN9_PIPE_PLANE3_FAULT |876 GEN9_PIPE_PLANE2_FAULT |877 GEN9_PIPE_PLANE1_FAULT;878 else if (DISPLAY_VER(dev_priv) == 11)879 return GEN9_PIPE_CURSOR_FAULT |880 GEN11_PIPE_PLANE7_FAULT |881 GEN11_PIPE_PLANE6_FAULT |882 GEN11_PIPE_PLANE5_FAULT |883 GEN9_PIPE_PLANE4_FAULT |884 GEN9_PIPE_PLANE3_FAULT |885 GEN9_PIPE_PLANE2_FAULT |886 GEN9_PIPE_PLANE1_FAULT;887 else if (DISPLAY_VER(dev_priv) >= 9)888 return GEN9_PIPE_CURSOR_FAULT |889 GEN9_PIPE_PLANE4_FAULT |890 GEN9_PIPE_PLANE3_FAULT |891 GEN9_PIPE_PLANE2_FAULT |892 GEN9_PIPE_PLANE1_FAULT;893 else894 return GEN8_PIPE_CURSOR_FAULT |895 GEN8_PIPE_SPRITE_FAULT |896 GEN8_PIPE_PRIMARY_FAULT;897}898 899static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)900{901 wake_up_all(&dev_priv->display.pmdemand.waitqueue);902}903 904static void905gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)906{907 struct intel_display *display = &dev_priv->display;908 bool found = false;909 910 if (DISPLAY_VER(dev_priv) >= 14) {911 if (iir & (XELPDP_PMDEMAND_RSP |912 XELPDP_PMDEMAND_RSPTOUT_ERR)) {913 if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)914 drm_dbg(&dev_priv->drm,915 "Error waiting for Punit PM Demand Response\n");916 917 intel_pmdemand_irq_handler(dev_priv);918 found = true;919 }920 921 if (iir & XELPDP_RM_TIMEOUT) {922 u32 val = intel_uncore_read(&dev_priv->uncore,923 RM_TIMEOUT_REG_CAPTURE);924 drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val);925 found = true;926 }927 } else if (iir & GEN8_DE_MISC_GSE) {928 intel_opregion_asle_intr(display);929 found = true;930 }931 932 if (iir & GEN8_DE_EDP_PSR) {933 struct intel_encoder *encoder;934 u32 psr_iir;935 i915_reg_t iir_reg;936 937 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {938 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);939 940 if (DISPLAY_VER(dev_priv) >= 12)941 iir_reg = TRANS_PSR_IIR(dev_priv,942 intel_dp->psr.transcoder);943 else944 iir_reg = EDP_PSR_IIR;945 946 psr_iir = intel_uncore_rmw(&dev_priv->uncore, iir_reg, 0, 0);947 948 if (psr_iir)949 found = true;950 951 intel_psr_irq_handler(intel_dp, psr_iir);952 953 /* prior GEN12 only have one EDP PSR */954 if (DISPLAY_VER(dev_priv) < 12)955 break;956 }957 }958 959 if (!found)960 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);961}962 963static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,964 u32 te_trigger)965{966 enum pipe pipe = INVALID_PIPE;967 enum transcoder dsi_trans;968 enum port port;969 u32 val;970 971 /*972 * Incase of dual link, TE comes from DSI_1973 * this is to check if dual link is enabled974 */975 val = intel_uncore_read(&dev_priv->uncore,976 TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0));977 val &= PORT_SYNC_MODE_ENABLE;978 979 /*980 * if dual link is enabled, then read DSI_0981 * transcoder registers982 */983 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?984 PORT_A : PORT_B;985 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;986 987 /* Check if DSI configured in command mode */988 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans));989 val = val & OP_MODE_MASK;990 991 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {992 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");993 return;994 }995 996 /* Get PIPE for handling VBLANK event */997 val = intel_uncore_read(&dev_priv->uncore,998 TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));999 switch (val & TRANS_DDI_EDP_INPUT_MASK) {1000 case TRANS_DDI_EDP_INPUT_A_ON:1001 pipe = PIPE_A;1002 break;1003 case TRANS_DDI_EDP_INPUT_B_ONOFF:1004 pipe = PIPE_B;1005 break;1006 case TRANS_DDI_EDP_INPUT_C_ONOFF:1007 pipe = PIPE_C;1008 break;1009 default:1010 drm_err(&dev_priv->drm, "Invalid PIPE\n");1011 return;1012 }1013 1014 intel_handle_vblank(dev_priv, pipe);1015 1016 /* clear TE in dsi IIR */1017 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;1018 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0);1019}1020 1021static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)1022{1023 if (DISPLAY_VER(i915) >= 9)1024 return GEN9_PIPE_PLANE1_FLIP_DONE;1025 else1026 return GEN8_PIPE_PRIMARY_FLIP_DONE;1027}1028 1029u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)1030{1031 u32 mask = GEN8_PIPE_FIFO_UNDERRUN;1032 1033 if (DISPLAY_VER(dev_priv) >= 13)1034 mask |= XELPD_PIPE_SOFT_UNDERRUN |1035 XELPD_PIPE_HARD_UNDERRUN;1036 1037 return mask;1038}1039 1040static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir)1041{1042 u32 pica_ier = 0;1043 1044 *pica_iir = 0;1045 *pch_iir = intel_de_read(i915, SDEIIR);1046 if (!*pch_iir)1047 return;1048 1049 /**1050 * PICA IER must be disabled/re-enabled around clearing PICA IIR and1051 * SDEIIR, to avoid losing PICA IRQs and to ensure that such IRQs set1052 * their flags both in the PICA and SDE IIR.1053 */1054 if (*pch_iir & SDE_PICAINTERRUPT) {1055 drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL);1056 1057 pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);1058 *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);1059 intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir);1060 }1061 1062 intel_de_write(i915, SDEIIR, *pch_iir);1063 1064 if (pica_ier)1065 intel_de_write(i915, PICAINTERRUPT_IER, pica_ier);1066}1067 1068void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)1069{1070 struct intel_display *display = &dev_priv->display;1071 u32 iir;1072 enum pipe pipe;1073 1074 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));1075 1076 if (master_ctl & GEN8_DE_MISC_IRQ) {1077 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);1078 if (iir) {1079 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);1080 gen8_de_misc_irq_handler(dev_priv, iir);1081 } else {1082 drm_err_ratelimited(&dev_priv->drm,1083 "The master control interrupt lied (DE MISC)!\n");1084 }1085 }1086 1087 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {1088 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);1089 if (iir) {1090 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);1091 gen11_hpd_irq_handler(dev_priv, iir);1092 } else {1093 drm_err_ratelimited(&dev_priv->drm,1094 "The master control interrupt lied, (DE HPD)!\n");1095 }1096 }1097 1098 if (master_ctl & GEN8_DE_PORT_IRQ) {1099 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);1100 if (iir) {1101 bool found = false;1102 1103 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);1104 1105 if (iir & gen8_de_port_aux_mask(dev_priv)) {1106 intel_dp_aux_irq_handler(display);1107 found = true;1108 }1109 1110 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {1111 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;1112 1113 if (hotplug_trigger) {1114 bxt_hpd_irq_handler(dev_priv, hotplug_trigger);1115 found = true;1116 }1117 } else if (IS_BROADWELL(dev_priv)) {1118 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;1119 1120 if (hotplug_trigger) {1121 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);1122 found = true;1123 }1124 }1125 1126 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&1127 (iir & BXT_DE_PORT_GMBUS)) {1128 intel_gmbus_irq_handler(dev_priv);1129 found = true;1130 }1131 1132 if (DISPLAY_VER(dev_priv) >= 11) {1133 u32 te_trigger = iir & (DSI0_TE | DSI1_TE);1134 1135 if (te_trigger) {1136 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);1137 found = true;1138 }1139 }1140 1141 if (!found)1142 drm_err_ratelimited(&dev_priv->drm,1143 "Unexpected DE Port interrupt\n");1144 } else {1145 drm_err_ratelimited(&dev_priv->drm,1146 "The master control interrupt lied (DE PORT)!\n");1147 }1148 }1149 1150 for_each_pipe(dev_priv, pipe) {1151 u32 fault_errors;1152 1153 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))1154 continue;1155 1156 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));1157 if (!iir) {1158 drm_err_ratelimited(&dev_priv->drm,1159 "The master control interrupt lied (DE PIPE)!\n");1160 continue;1161 }1162 1163 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);1164 1165 if (iir & GEN8_PIPE_VBLANK)1166 intel_handle_vblank(dev_priv, pipe);1167 1168 if (iir & gen8_de_pipe_flip_done_mask(dev_priv))1169 flip_done_handler(dev_priv, pipe);1170 1171 if (HAS_DSB(dev_priv)) {1172 if (iir & GEN12_DSB_INT(INTEL_DSB_0))1173 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0);1174 1175 if (iir & GEN12_DSB_INT(INTEL_DSB_1))1176 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1);1177 1178 if (iir & GEN12_DSB_INT(INTEL_DSB_2))1179 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2);1180 }1181 1182 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)1183 hsw_pipe_crc_irq_handler(dev_priv, pipe);1184 1185 if (iir & gen8_de_pipe_underrun_mask(dev_priv))1186 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);1187 1188 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);1189 if (fault_errors)1190 drm_err_ratelimited(&dev_priv->drm,1191 "Fault errors on pipe %c: 0x%08x\n",1192 pipe_name(pipe),1193 fault_errors);1194 }1195 1196 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&1197 master_ctl & GEN8_DE_PCH_IRQ) {1198 u32 pica_iir;1199 1200 /*1201 * FIXME(BDW): Assume for now that the new interrupt handling1202 * scheme also closed the SDE interrupt handling race we've seen1203 * on older pch-split platforms. But this needs testing.1204 */1205 gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);1206 if (iir) {1207 if (pica_iir)1208 xelpdp_pica_irq_handler(dev_priv, pica_iir);1209 1210 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)1211 icp_irq_handler(dev_priv, iir);1212 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)1213 spt_irq_handler(dev_priv, iir);1214 else1215 cpt_irq_handler(dev_priv, iir);1216 } else {1217 /*1218 * Like on previous PCH there seems to be something1219 * fishy going on with forwarding PCH interrupts.1220 */1221 drm_dbg(&dev_priv->drm,1222 "The master control interrupt lied (SDE)!\n");1223 }1224 }1225}1226 1227u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)1228{1229 void __iomem * const regs = intel_uncore_regs(&i915->uncore);1230 u32 iir;1231 1232 if (!(master_ctl & GEN11_GU_MISC_IRQ))1233 return 0;1234 1235 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);1236 if (likely(iir))1237 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);1238 1239 return iir;1240}1241 1242void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)1243{1244 struct intel_display *display = &i915->display;1245 1246 if (iir & GEN11_GU_MISC_GSE)1247 intel_opregion_asle_intr(display);1248}1249 1250void gen11_display_irq_handler(struct drm_i915_private *i915)1251{1252 void __iomem * const regs = intel_uncore_regs(&i915->uncore);1253 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);1254 1255 disable_rpm_wakeref_asserts(&i915->runtime_pm);1256 /*1257 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ1258 * for the display related bits.1259 */1260 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);1261 gen8_de_irq_handler(i915, disp_ctl);1262 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,1263 GEN11_DISPLAY_IRQ_ENABLE);1264 1265 enable_rpm_wakeref_asserts(&i915->runtime_pm);1266}1267 1268/* Called from drm generic code, passed 'crtc' which1269 * we use as a pipe index1270 */1271int i8xx_enable_vblank(struct drm_crtc *crtc)1272{1273 struct drm_i915_private *dev_priv = to_i915(crtc->dev);1274 enum pipe pipe = to_intel_crtc(crtc)->pipe;1275 unsigned long irqflags;1276 1277 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1278 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);1279 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1280 1281 return 0;1282}1283 1284int i915gm_enable_vblank(struct drm_crtc *crtc)1285{1286 struct drm_i915_private *i915 = to_i915(crtc->dev);1287 1288 /*1289 * Vblank interrupts fail to wake the device up from C2+.1290 * Disabling render clock gating during C-states avoids1291 * the problem. There is a small power cost so we do this1292 * only when vblank interrupts are actually enabled.1293 */1294 if (i915->display.irq.vblank_enabled++ == 0)1295 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));1296 1297 return i8xx_enable_vblank(crtc);1298}1299 1300int i965_enable_vblank(struct drm_crtc *crtc)1301{1302 struct drm_i915_private *dev_priv = to_i915(crtc->dev);1303 enum pipe pipe = to_intel_crtc(crtc)->pipe;1304 unsigned long irqflags;1305 1306 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1307 i915_enable_pipestat(dev_priv, pipe,1308 PIPE_START_VBLANK_INTERRUPT_STATUS);1309 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1310 1311 return 0;1312}1313 1314int ilk_enable_vblank(struct drm_crtc *crtc)1315{1316 struct drm_i915_private *dev_priv = to_i915(crtc->dev);1317 enum pipe pipe = to_intel_crtc(crtc)->pipe;1318 unsigned long irqflags;1319 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?1320 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);1321 1322 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1323 ilk_enable_display_irq(dev_priv, bit);1324 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1325 1326 /* Even though there is no DMC, frame counter can get stuck when1327 * PSR is active as no frames are generated.1328 */1329 if (HAS_PSR(dev_priv))1330 drm_crtc_vblank_restore(crtc);1331 1332 return 0;1333}1334 1335static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,1336 bool enable)1337{1338 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);1339 enum port port;1340 1341 if (!(intel_crtc->mode_flags &1342 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))1343 return false;1344 1345 /* for dual link cases we consider TE from slave */1346 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)1347 port = PORT_B;1348 else1349 port = PORT_A;1350 1351 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT,1352 enable ? 0 : DSI_TE_EVENT);1353 1354 intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0);1355 1356 return true;1357}1358 1359int bdw_enable_vblank(struct drm_crtc *_crtc)1360{1361 struct intel_crtc *crtc = to_intel_crtc(_crtc);1362 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);1363 enum pipe pipe = crtc->pipe;1364 unsigned long irqflags;1365 1366 if (gen11_dsi_configure_te(crtc, true))1367 return 0;1368 1369 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1370 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);1371 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1372 1373 /* Even if there is no DMC, frame counter can get stuck when1374 * PSR is active as no frames are generated, so check only for PSR.1375 */1376 if (HAS_PSR(dev_priv))1377 drm_crtc_vblank_restore(&crtc->base);1378 1379 return 0;1380}1381 1382/* Called from drm generic code, passed 'crtc' which1383 * we use as a pipe index1384 */1385void i8xx_disable_vblank(struct drm_crtc *crtc)1386{1387 struct drm_i915_private *dev_priv = to_i915(crtc->dev);1388 enum pipe pipe = to_intel_crtc(crtc)->pipe;1389 unsigned long irqflags;1390 1391 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1392 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);1393 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1394}1395 1396void i915gm_disable_vblank(struct drm_crtc *crtc)1397{1398 struct drm_i915_private *i915 = to_i915(crtc->dev);1399 1400 i8xx_disable_vblank(crtc);1401 1402 if (--i915->display.irq.vblank_enabled == 0)1403 intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));1404}1405 1406void i965_disable_vblank(struct drm_crtc *crtc)1407{1408 struct drm_i915_private *dev_priv = to_i915(crtc->dev);1409 enum pipe pipe = to_intel_crtc(crtc)->pipe;1410 unsigned long irqflags;1411 1412 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1413 i915_disable_pipestat(dev_priv, pipe,1414 PIPE_START_VBLANK_INTERRUPT_STATUS);1415 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1416}1417 1418void ilk_disable_vblank(struct drm_crtc *crtc)1419{1420 struct drm_i915_private *dev_priv = to_i915(crtc->dev);1421 enum pipe pipe = to_intel_crtc(crtc)->pipe;1422 unsigned long irqflags;1423 u32 bit = DISPLAY_VER(dev_priv) >= 7 ?1424 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);1425 1426 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1427 ilk_disable_display_irq(dev_priv, bit);1428 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1429}1430 1431void bdw_disable_vblank(struct drm_crtc *_crtc)1432{1433 struct intel_crtc *crtc = to_intel_crtc(_crtc);1434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);1435 enum pipe pipe = crtc->pipe;1436 unsigned long irqflags;1437 1438 if (gen11_dsi_configure_te(crtc, false))1439 return;1440 1441 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);1442 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);1443 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);1444}1445 1446void vlv_display_irq_reset(struct drm_i915_private *dev_priv)1447{1448 struct intel_uncore *uncore = &dev_priv->uncore;1449 1450 if (IS_CHERRYVIEW(dev_priv))1451 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);1452 else1453 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);1454 1455 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);1456 intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0);1457 1458 i9xx_pipestat_irq_reset(dev_priv);1459 1460 GEN3_IRQ_RESET(uncore, VLV_);1461 dev_priv->irq_mask = ~0u;1462}1463 1464void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)1465{1466 struct intel_uncore *uncore = &dev_priv->uncore;1467 1468 u32 pipestat_mask;1469 u32 enable_mask;1470 enum pipe pipe;1471 1472 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;1473 1474 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);1475 for_each_pipe(dev_priv, pipe)1476 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);1477 1478 enable_mask = I915_DISPLAY_PORT_INTERRUPT |1479 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |1480 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |1481 I915_LPE_PIPE_A_INTERRUPT |1482 I915_LPE_PIPE_B_INTERRUPT;1483 1484 if (IS_CHERRYVIEW(dev_priv))1485 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |1486 I915_LPE_PIPE_C_INTERRUPT;1487 1488 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);1489 1490 dev_priv->irq_mask = ~enable_mask;1491 1492 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);1493}1494 1495void gen8_display_irq_reset(struct drm_i915_private *dev_priv)1496{1497 struct intel_uncore *uncore = &dev_priv->uncore;1498 enum pipe pipe;1499 1500 if (!HAS_DISPLAY(dev_priv))1501 return;1502 1503 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);1504 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);1505 1506 for_each_pipe(dev_priv, pipe)1507 if (intel_display_power_is_enabled(dev_priv,1508 POWER_DOMAIN_PIPE(pipe)))1509 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);1510 1511 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);1512 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);1513}1514 1515void gen11_display_irq_reset(struct drm_i915_private *dev_priv)1516{1517 struct intel_uncore *uncore = &dev_priv->uncore;1518 enum pipe pipe;1519 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |1520 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);1521 1522 if (!HAS_DISPLAY(dev_priv))1523 return;1524 1525 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);1526 1527 if (DISPLAY_VER(dev_priv) >= 12) {1528 enum transcoder trans;1529 1530 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {1531 enum intel_display_power_domain domain;1532 1533 domain = POWER_DOMAIN_TRANSCODER(trans);1534 if (!intel_display_power_is_enabled(dev_priv, domain))1535 continue;1536 1537 intel_uncore_write(uncore,1538 TRANS_PSR_IMR(dev_priv, trans),1539 0xffffffff);1540 intel_uncore_write(uncore,1541 TRANS_PSR_IIR(dev_priv, trans),1542 0xffffffff);1543 }1544 } else {1545 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);1546 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);1547 }1548 1549 for_each_pipe(dev_priv, pipe)1550 if (intel_display_power_is_enabled(dev_priv,1551 POWER_DOMAIN_PIPE(pipe)))1552 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);1553 1554 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);1555 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);1556 1557 if (DISPLAY_VER(dev_priv) >= 14)1558 GEN3_IRQ_RESET(uncore, PICAINTERRUPT_);1559 else1560 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);1561 1562 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)1563 GEN3_IRQ_RESET(uncore, SDE);1564}1565 1566void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,1567 u8 pipe_mask)1568{1569 struct intel_uncore *uncore = &dev_priv->uncore;1570 u32 extra_ier = GEN8_PIPE_VBLANK |1571 gen8_de_pipe_underrun_mask(dev_priv) |1572 gen8_de_pipe_flip_done_mask(dev_priv);1573 enum pipe pipe;1574 1575 spin_lock_irq(&dev_priv->irq_lock);1576 1577 if (!intel_irqs_enabled(dev_priv)) {1578 spin_unlock_irq(&dev_priv->irq_lock);1579 return;1580 }1581 1582 for_each_pipe_masked(dev_priv, pipe, pipe_mask)1583 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,1584 dev_priv->display.irq.de_irq_mask[pipe],1585 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier);1586 1587 spin_unlock_irq(&dev_priv->irq_lock);1588}1589 1590void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,1591 u8 pipe_mask)1592{1593 struct intel_uncore *uncore = &dev_priv->uncore;1594 enum pipe pipe;1595 1596 spin_lock_irq(&dev_priv->irq_lock);1597 1598 if (!intel_irqs_enabled(dev_priv)) {1599 spin_unlock_irq(&dev_priv->irq_lock);1600 return;1601 }1602 1603 for_each_pipe_masked(dev_priv, pipe, pipe_mask)1604 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);1605 1606 spin_unlock_irq(&dev_priv->irq_lock);1607 1608 /* make sure we're done processing display irqs */1609 intel_synchronize_irq(dev_priv);1610}1611 1612/*1613 * SDEIER is also touched by the interrupt handler to work around missed PCH1614 * interrupts. Hence we can't update it after the interrupt handler is enabled -1615 * instead we unconditionally enable all PCH interrupt sources here, but then1616 * only unmask them as needed with SDEIMR.1617 *1618 * Note that we currently do this after installing the interrupt handler,1619 * but before we enable the master interrupt. That should be sufficient1620 * to avoid races with the irq handler, assuming we have MSI. Shared legacy1621 * interrupts could still race.1622 */1623static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)1624{1625 struct intel_uncore *uncore = &dev_priv->uncore;1626 u32 mask;1627 1628 if (HAS_PCH_NOP(dev_priv))1629 return;1630 1631 if (HAS_PCH_IBX(dev_priv))1632 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;1633 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))1634 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;1635 else1636 mask = SDE_GMBUS_CPT;1637 1638 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);1639}1640 1641void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)1642{1643 lockdep_assert_held(&dev_priv->irq_lock);1644 1645 if (dev_priv->display.irq.display_irqs_enabled)1646 return;1647 1648 dev_priv->display.irq.display_irqs_enabled = true;1649 1650 if (intel_irqs_enabled(dev_priv)) {1651 vlv_display_irq_reset(dev_priv);1652 vlv_display_irq_postinstall(dev_priv);1653 }1654}1655 1656void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)1657{1658 lockdep_assert_held(&dev_priv->irq_lock);1659 1660 if (!dev_priv->display.irq.display_irqs_enabled)1661 return;1662 1663 dev_priv->display.irq.display_irqs_enabled = false;1664 1665 if (intel_irqs_enabled(dev_priv))1666 vlv_display_irq_reset(dev_priv);1667}1668 1669void ilk_de_irq_postinstall(struct drm_i915_private *i915)1670{1671 struct intel_uncore *uncore = &i915->uncore;1672 u32 display_mask, extra_mask;1673 1674 if (DISPLAY_VER(i915) >= 7) {1675 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |1676 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);1677 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |1678 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |1679 DE_PLANE_FLIP_DONE_IVB(PLANE_C) |1680 DE_PLANE_FLIP_DONE_IVB(PLANE_B) |1681 DE_PLANE_FLIP_DONE_IVB(PLANE_A) |1682 DE_DP_A_HOTPLUG_IVB);1683 } else {1684 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |1685 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |1686 DE_PIPEA_CRC_DONE | DE_POISON);1687 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |1688 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |1689 DE_PLANE_FLIP_DONE(PLANE_A) |1690 DE_PLANE_FLIP_DONE(PLANE_B) |1691 DE_DP_A_HOTPLUG);1692 }1693 1694 if (IS_HASWELL(i915)) {1695 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);1696 display_mask |= DE_EDP_PSR_INT_HSW;1697 }1698 1699 if (IS_IRONLAKE_M(i915))1700 extra_mask |= DE_PCU_EVENT;1701 1702 i915->irq_mask = ~display_mask;1703 1704 ibx_irq_postinstall(i915);1705 1706 GEN3_IRQ_INIT(uncore, DE, i915->irq_mask,1707 display_mask | extra_mask);1708}1709 1710static void mtp_irq_postinstall(struct drm_i915_private *i915);1711static void icp_irq_postinstall(struct drm_i915_private *i915);1712 1713void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)1714{1715 struct intel_display *display = &dev_priv->display;1716 struct intel_uncore *uncore = &dev_priv->uncore;1717 1718 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |1719 GEN8_PIPE_CDCLK_CRC_DONE;1720 u32 de_pipe_enables;1721 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);1722 u32 de_port_enables;1723 u32 de_misc_masked = GEN8_DE_EDP_PSR;1724 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |1725 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);1726 enum pipe pipe;1727 1728 if (!HAS_DISPLAY(dev_priv))1729 return;1730 1731 if (DISPLAY_VER(dev_priv) >= 14)1732 mtp_irq_postinstall(dev_priv);1733 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)1734 icp_irq_postinstall(dev_priv);1735 else if (HAS_PCH_SPLIT(dev_priv))1736 ibx_irq_postinstall(dev_priv);1737 1738 if (DISPLAY_VER(dev_priv) < 11)1739 de_misc_masked |= GEN8_DE_MISC_GSE;1740 1741 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))1742 de_port_masked |= BXT_DE_PORT_GMBUS;1743 1744 if (DISPLAY_VER(dev_priv) >= 14) {1745 de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |1746 XELPDP_PMDEMAND_RSP | XELPDP_RM_TIMEOUT;1747 } else if (DISPLAY_VER(dev_priv) >= 11) {1748 enum port port;1749 1750 if (intel_bios_is_dsi_present(display, &port))1751 de_port_masked |= DSI0_TE | DSI1_TE;1752 }1753 1754 if (HAS_DSB(dev_priv))1755 de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |1756 GEN12_DSB_INT(INTEL_DSB_1) |1757 GEN12_DSB_INT(INTEL_DSB_2);1758 1759 de_pipe_enables = de_pipe_masked |1760 GEN8_PIPE_VBLANK |1761 gen8_de_pipe_underrun_mask(dev_priv) |1762 gen8_de_pipe_flip_done_mask(dev_priv);1763 1764 de_port_enables = de_port_masked;1765 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))1766 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;1767 else if (IS_BROADWELL(dev_priv))1768 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;1769 1770 if (DISPLAY_VER(dev_priv) >= 12) {1771 enum transcoder trans;1772 1773 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {1774 enum intel_display_power_domain domain;1775 1776 domain = POWER_DOMAIN_TRANSCODER(trans);1777 if (!intel_display_power_is_enabled(dev_priv, domain))1778 continue;1779 1780 gen3_assert_iir_is_zero(uncore,1781 TRANS_PSR_IIR(dev_priv, trans));1782 }1783 } else {1784 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);1785 }1786 1787 for_each_pipe(dev_priv, pipe) {1788 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked;1789 1790 if (intel_display_power_is_enabled(dev_priv,1791 POWER_DOMAIN_PIPE(pipe)))1792 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,1793 dev_priv->display.irq.de_irq_mask[pipe],1794 de_pipe_enables);1795 }1796 1797 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);1798 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);1799 1800 if (IS_DISPLAY_VER(dev_priv, 11, 13)) {1801 u32 de_hpd_masked = 0;1802 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |1803 GEN11_DE_TBT_HOTPLUG_MASK;1804 1805 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,1806 de_hpd_enables);1807 }1808}1809 1810static void mtp_irq_postinstall(struct drm_i915_private *i915)1811{1812 struct intel_uncore *uncore = &i915->uncore;1813 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT;1814 u32 de_hpd_mask = XELPDP_AUX_TC_MASK;1815 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |1816 XELPDP_TBT_HOTPLUG_MASK;1817 1818 GEN3_IRQ_INIT(uncore, PICAINTERRUPT_, ~de_hpd_mask,1819 de_hpd_enables);1820 1821 GEN3_IRQ_INIT(uncore, SDE, ~sde_mask, 0xffffffff);1822}1823 1824static void icp_irq_postinstall(struct drm_i915_private *dev_priv)1825{1826 struct intel_uncore *uncore = &dev_priv->uncore;1827 u32 mask = SDE_GMBUS_ICP;1828 1829 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);1830}1831 1832void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)1833{1834 if (!HAS_DISPLAY(dev_priv))1835 return;1836 1837 gen8_de_irq_postinstall(dev_priv);1838 1839 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,1840 GEN11_DISPLAY_IRQ_ENABLE);1841}1842 1843void dg1_de_irq_postinstall(struct drm_i915_private *i915)1844{1845 if (!HAS_DISPLAY(i915))1846 return;1847 1848 gen8_de_irq_postinstall(i915);1849 intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL,1850 GEN11_DISPLAY_IRQ_ENABLE);1851}1852 1853void intel_display_irq_init(struct drm_i915_private *i915)1854{1855 i915->drm.vblank_disable_immediate = true;1856 1857 /*1858 * Most platforms treat the display irq block as an always-on power1859 * domain. vlv/chv can disable it at runtime and need special care to1860 * avoid writing any of the display block registers outside of the power1861 * domain. We defer setting up the display irqs in this case to the1862 * runtime pm.1863 */1864 i915->display.irq.display_irqs_enabled = true;1865 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))1866 i915->display.irq.display_irqs_enabled = false;1867 1868 intel_hotplug_irq_init(i915);1869}1870