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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef __INTEL_DISPLAY_IRQ_H__7#define __INTEL_DISPLAY_IRQ_H__8 9#include <linux/types.h>10 11#include "intel_display_limits.h"12 13enum pipe;14struct drm_i915_private;15struct drm_crtc;16 17void valleyview_enable_display_irqs(struct drm_i915_private *i915);18void valleyview_disable_display_irqs(struct drm_i915_private *i915);19 20void ilk_update_display_irq(struct drm_i915_private *i915,21 u32 interrupt_mask, u32 enabled_irq_mask);22void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);23void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);24 25void bdw_update_port_irq(struct drm_i915_private *i915, u32 interrupt_mask, u32 enabled_irq_mask);26void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);27void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);28 29void ibx_display_interrupt_update(struct drm_i915_private *i915,30 u32 interrupt_mask, u32 enabled_irq_mask);31void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);32void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);33 34void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask);35void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask);36u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *i915);37 38int i8xx_enable_vblank(struct drm_crtc *crtc);39int i915gm_enable_vblank(struct drm_crtc *crtc);40int i965_enable_vblank(struct drm_crtc *crtc);41int ilk_enable_vblank(struct drm_crtc *crtc);42int bdw_enable_vblank(struct drm_crtc *crtc);43void i8xx_disable_vblank(struct drm_crtc *crtc);44void i915gm_disable_vblank(struct drm_crtc *crtc);45void i965_disable_vblank(struct drm_crtc *crtc);46void ilk_disable_vblank(struct drm_crtc *crtc);47void bdw_disable_vblank(struct drm_crtc *crtc);48 49void ivb_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);50void ilk_display_irq_handler(struct drm_i915_private *i915, u32 de_iir);51void gen8_de_irq_handler(struct drm_i915_private *i915, u32 master_ctl);52void gen11_display_irq_handler(struct drm_i915_private *i915);53 54u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl);55void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir);56 57void vlv_display_irq_reset(struct drm_i915_private *i915);58void gen8_display_irq_reset(struct drm_i915_private *i915);59void gen11_display_irq_reset(struct drm_i915_private *i915);60 61void vlv_display_irq_postinstall(struct drm_i915_private *i915);62void ilk_de_irq_postinstall(struct drm_i915_private *i915);63void gen8_de_irq_postinstall(struct drm_i915_private *i915);64void gen11_de_irq_postinstall(struct drm_i915_private *i915);65void dg1_de_irq_postinstall(struct drm_i915_private *i915);66 67u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe);68void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);69void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask);70void i915_enable_asle_pipestat(struct drm_i915_private *i915);71void i9xx_pipestat_irq_reset(struct drm_i915_private *i915);72 73void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);74 75void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);76void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);77void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]);78void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPES]);79 80void intel_display_irq_init(struct drm_i915_private *i915);81 82#endif /* __INTEL_DISPLAY_IRQ_H__ */83