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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2019 Intel Corporation4 */5 6#ifndef __INTEL_DISPLAY_POWER_H__7#define __INTEL_DISPLAY_POWER_H__8 9#include <linux/mutex.h>10#include <linux/workqueue.h>11 12#include "intel_wakeref.h"13 14enum aux_ch;15enum port;16struct drm_i915_private;17struct i915_power_well;18struct intel_encoder;19struct seq_file;20 21/*22 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances23 * consecutive, so that the pipe,transcoder,port -> power domain macros24 * work correctly.25 */26enum intel_display_power_domain {27 POWER_DOMAIN_DISPLAY_CORE,28 POWER_DOMAIN_PIPE_A,29 POWER_DOMAIN_PIPE_B,30 POWER_DOMAIN_PIPE_C,31 POWER_DOMAIN_PIPE_D,32 POWER_DOMAIN_PIPE_PANEL_FITTER_A,33 POWER_DOMAIN_PIPE_PANEL_FITTER_B,34 POWER_DOMAIN_PIPE_PANEL_FITTER_C,35 POWER_DOMAIN_PIPE_PANEL_FITTER_D,36 POWER_DOMAIN_TRANSCODER_A,37 POWER_DOMAIN_TRANSCODER_B,38 POWER_DOMAIN_TRANSCODER_C,39 POWER_DOMAIN_TRANSCODER_D,40 POWER_DOMAIN_TRANSCODER_EDP,41 POWER_DOMAIN_TRANSCODER_DSI_A,42 POWER_DOMAIN_TRANSCODER_DSI_C,43 44 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */45 POWER_DOMAIN_TRANSCODER_VDSC_PW2,46 47 POWER_DOMAIN_PORT_DDI_LANES_A,48 POWER_DOMAIN_PORT_DDI_LANES_B,49 POWER_DOMAIN_PORT_DDI_LANES_C,50 POWER_DOMAIN_PORT_DDI_LANES_D,51 POWER_DOMAIN_PORT_DDI_LANES_E,52 POWER_DOMAIN_PORT_DDI_LANES_F,53 54 POWER_DOMAIN_PORT_DDI_LANES_TC1,55 POWER_DOMAIN_PORT_DDI_LANES_TC2,56 POWER_DOMAIN_PORT_DDI_LANES_TC3,57 POWER_DOMAIN_PORT_DDI_LANES_TC4,58 POWER_DOMAIN_PORT_DDI_LANES_TC5,59 POWER_DOMAIN_PORT_DDI_LANES_TC6,60 61 POWER_DOMAIN_PORT_DDI_IO_A,62 POWER_DOMAIN_PORT_DDI_IO_B,63 POWER_DOMAIN_PORT_DDI_IO_C,64 POWER_DOMAIN_PORT_DDI_IO_D,65 POWER_DOMAIN_PORT_DDI_IO_E,66 POWER_DOMAIN_PORT_DDI_IO_F,67 68 POWER_DOMAIN_PORT_DDI_IO_TC1,69 POWER_DOMAIN_PORT_DDI_IO_TC2,70 POWER_DOMAIN_PORT_DDI_IO_TC3,71 POWER_DOMAIN_PORT_DDI_IO_TC4,72 POWER_DOMAIN_PORT_DDI_IO_TC5,73 POWER_DOMAIN_PORT_DDI_IO_TC6,74 75 POWER_DOMAIN_PORT_DSI,76 POWER_DOMAIN_PORT_CRT,77 POWER_DOMAIN_PORT_OTHER,78 POWER_DOMAIN_VGA,79 POWER_DOMAIN_AUDIO_MMIO,80 POWER_DOMAIN_AUDIO_PLAYBACK,81 82 POWER_DOMAIN_AUX_IO_A,83 POWER_DOMAIN_AUX_IO_B,84 POWER_DOMAIN_AUX_IO_C,85 POWER_DOMAIN_AUX_IO_D,86 POWER_DOMAIN_AUX_IO_E,87 POWER_DOMAIN_AUX_IO_F,88 89 POWER_DOMAIN_AUX_A,90 POWER_DOMAIN_AUX_B,91 POWER_DOMAIN_AUX_C,92 POWER_DOMAIN_AUX_D,93 POWER_DOMAIN_AUX_E,94 POWER_DOMAIN_AUX_F,95 96 POWER_DOMAIN_AUX_USBC1,97 POWER_DOMAIN_AUX_USBC2,98 POWER_DOMAIN_AUX_USBC3,99 POWER_DOMAIN_AUX_USBC4,100 POWER_DOMAIN_AUX_USBC5,101 POWER_DOMAIN_AUX_USBC6,102 103 POWER_DOMAIN_AUX_TBT1,104 POWER_DOMAIN_AUX_TBT2,105 POWER_DOMAIN_AUX_TBT3,106 POWER_DOMAIN_AUX_TBT4,107 POWER_DOMAIN_AUX_TBT5,108 POWER_DOMAIN_AUX_TBT6,109 110 POWER_DOMAIN_GMBUS,111 POWER_DOMAIN_GT_IRQ,112 POWER_DOMAIN_DC_OFF,113 POWER_DOMAIN_TC_COLD_OFF,114 POWER_DOMAIN_INIT,115 116 POWER_DOMAIN_NUM,117 POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,118};119 120#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)121#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \122 ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)123#define POWER_DOMAIN_TRANSCODER(tran) \124 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \125 (tran) + POWER_DOMAIN_TRANSCODER_A)126 127struct intel_power_domain_mask {128 DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);129};130 131struct i915_power_domains {132 /*133 * Power wells needed for initialization at driver init and suspend134 * time are on. They are kept on until after the first modeset.135 */136 bool initializing;137 bool display_core_suspended;138 int power_well_count;139 140 u32 dc_state;141 u32 target_dc_state;142 u32 allowed_dc_mask;143 144 intel_wakeref_t init_wakeref;145 intel_wakeref_t disable_wakeref;146 147 struct mutex lock;148 int domain_use_count[POWER_DOMAIN_NUM];149 150 struct delayed_work async_put_work;151 intel_wakeref_t async_put_wakeref;152 struct intel_power_domain_mask async_put_domains[2];153 int async_put_next_delay;154 155 struct i915_power_well *power_wells;156};157 158struct intel_display_power_domain_set {159 struct intel_power_domain_mask mask;160#ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM161 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];162#endif163};164 165#define for_each_power_domain(__domain, __mask) \166 for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \167 for_each_if(test_bit((__domain), (__mask)->bits))168 169int intel_power_domains_init(struct drm_i915_private *dev_priv);170void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);171void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);172void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);173void intel_power_domains_enable(struct drm_i915_private *dev_priv);174void intel_power_domains_disable(struct drm_i915_private *dev_priv);175void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle);176void intel_power_domains_resume(struct drm_i915_private *dev_priv);177void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);178 179void intel_display_power_suspend_late(struct drm_i915_private *i915);180void intel_display_power_resume_early(struct drm_i915_private *i915);181void intel_display_power_suspend(struct drm_i915_private *i915);182void intel_display_power_resume(struct drm_i915_private *i915);183void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,184 u32 state);185 186bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,187 enum intel_display_power_domain domain);188intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,189 enum intel_display_power_domain domain);190intel_wakeref_t191intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,192 enum intel_display_power_domain domain);193void __intel_display_power_put_async(struct drm_i915_private *i915,194 enum intel_display_power_domain domain,195 intel_wakeref_t wakeref,196 int delay_ms);197void intel_display_power_flush_work(struct drm_i915_private *i915);198#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)199void intel_display_power_put(struct drm_i915_private *dev_priv,200 enum intel_display_power_domain domain,201 intel_wakeref_t wakeref);202static inline void203intel_display_power_put_async(struct drm_i915_private *i915,204 enum intel_display_power_domain domain,205 intel_wakeref_t wakeref)206{207 __intel_display_power_put_async(i915, domain, wakeref, -1);208}209 210static inline void211intel_display_power_put_async_delay(struct drm_i915_private *i915,212 enum intel_display_power_domain domain,213 intel_wakeref_t wakeref,214 int delay_ms)215{216 __intel_display_power_put_async(i915, domain, wakeref, delay_ms);217}218#else219void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,220 enum intel_display_power_domain domain);221 222static inline void223intel_display_power_put(struct drm_i915_private *i915,224 enum intel_display_power_domain domain,225 intel_wakeref_t wakeref)226{227 intel_display_power_put_unchecked(i915, domain);228}229 230static inline void231intel_display_power_put_async(struct drm_i915_private *i915,232 enum intel_display_power_domain domain,233 intel_wakeref_t wakeref)234{235 __intel_display_power_put_async(i915, domain, -1, -1);236}237 238static inline void239intel_display_power_put_async_delay(struct drm_i915_private *i915,240 enum intel_display_power_domain domain,241 intel_wakeref_t wakeref,242 int delay_ms)243{244 __intel_display_power_put_async(i915, domain, -1, delay_ms);245}246#endif247 248void249intel_display_power_get_in_set(struct drm_i915_private *i915,250 struct intel_display_power_domain_set *power_domain_set,251 enum intel_display_power_domain domain);252 253bool254intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,255 struct intel_display_power_domain_set *power_domain_set,256 enum intel_display_power_domain domain);257 258void259intel_display_power_put_mask_in_set(struct drm_i915_private *i915,260 struct intel_display_power_domain_set *power_domain_set,261 struct intel_power_domain_mask *mask);262 263static inline void264intel_display_power_put_all_in_set(struct drm_i915_private *i915,265 struct intel_display_power_domain_set *power_domain_set)266{267 intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);268}269 270void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);271 272enum intel_display_power_domain273intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);274enum intel_display_power_domain275intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);276enum intel_display_power_domain277intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);278enum intel_display_power_domain279intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);280enum intel_display_power_domain281intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);282 283/*284 * FIXME: We should probably switch this to a 0-based scheme to be consistent285 * with how we now name/number DBUF_CTL instances.286 */287enum dbuf_slice {288 DBUF_S1,289 DBUF_S2,290 DBUF_S3,291 DBUF_S4,292 I915_MAX_DBUF_SLICES293};294 295void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,296 u8 req_slices);297 298#define with_intel_display_power(i915, domain, wf) \299 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \300 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)301 302#define with_intel_display_power_if_enabled(i915, domain, wf) \303 for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \304 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)305 306#endif /* __INTEL_DISPLAY_POWER_H__ */307