107 lines · c
1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2022 Intel Corporation4 */5 6#ifndef __INTEL_DMC_REGS_H__7#define __INTEL_DMC_REGS_H__8 9#include "i915_reg_defs.h"10 11#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)12#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC013 14#define _PIPEDMC_CONTROL_A 0x4525015#define _PIPEDMC_CONTROL_B 0x4525416#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \17 _PIPEDMC_CONTROL_A, \18 _PIPEDMC_CONTROL_B)19#define PIPEDMC_ENABLE REG_BIT(0)20 21#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)22#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)23 24#define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f00025#define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x9200026 27#define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \28 ((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \29 _TGL_PIPEDMC_REG_MMIO_BASE_A) + \30 0x400 * ((dmc_id) - 1))31 32#define __DMC_REG_MMIO_BASE 0x8f00033 34#define _DMC_REG_MMIO_BASE(i915, dmc_id) \35 ((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \36 __PIPEDMC_REG_MMIO_BASE(i915, dmc_id))37 38#define _DMC_REG(i915, dmc_id, reg) \39 ((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))40 41#define DMC_EVENT_HANDLER_COUNT_GEN12 842 43#define _DMC_EVT_HTP_0 0x8f00444 45#define DMC_EVT_HTP(i915, dmc_id, handler) \46 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))47 48#define _DMC_EVT_CTL_0 0x8f03449 50#define DMC_EVT_CTL(i915, dmc_id, handler) \51 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))52 53#define DMC_EVT_CTL_ENABLE REG_BIT(31)54#define DMC_EVT_CTL_RECURRING REG_BIT(30)55#define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16)56#define DMC_EVT_CTL_TYPE_LEVEL_0 057#define DMC_EVT_CTL_TYPE_LEVEL_1 158#define DMC_EVT_CTL_TYPE_EDGE_1_0 259#define DMC_EVT_CTL_TYPE_EDGE_0_1 360 61#define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)62#define DMC_EVT_CTL_EVENT_ID_FALSE 0x0163#define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */64/* An event handler scheduled to run at a 1 kHz frequency. */65#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf66 67#define DMC_HTP_ADDR_SKL 0x0050003468#define DMC_SSP_BASE _MMIO(0x8F074)69#define DMC_HTP_SKL _MMIO(0x8F004)70#define DMC_LAST_WRITE _MMIO(0x8F034)71#define DMC_LAST_WRITE_VALUE 0xc003b40072#define DMC_MMIO_START_RANGE 0x8000073#define DMC_MMIO_END_RANGE 0x8FFFF74#define DMC_V1_MMIO_START_RANGE 0x8000075#define TGL_MAIN_MMIO_START 0x8F00076#define TGL_MAIN_MMIO_END 0x8FFFF77#define _TGL_PIPEA_MMIO_START 0x9200078#define _TGL_PIPEA_MMIO_END 0x93FFF79#define _TGL_PIPEB_MMIO_START 0x9600080#define _TGL_PIPEB_MMIO_END 0x97FFF81#define ADLP_PIPE_MMIO_START 0x5F00082#define ADLP_PIPE_MMIO_END 0x5FFFF83 84#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\85 _TGL_PIPEB_MMIO_START)86 87#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\88 _TGL_PIPEB_MMIO_END)89 90#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)91#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)92#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)93#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)94#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)95#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)96 97#define TGL_DMC_DEBUG3 _MMIO(0x101090)98#define DG1_DMC_DEBUG3 _MMIO(0x13415c)99 100#define DMC_WAKELOCK_CFG _MMIO(0x8F1B0)101#define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)102#define DMC_WAKELOCK1_CTL _MMIO(0x8F140)103#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)104#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)105 106#endif /* __INTEL_DMC_REGS_H__ */107