brintos / linux-shallow public Read only

1/*2 * Copyright © 2008 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS21 * IN THE SOFTWARE.22 *23 * Authors:24 *    Keith Packard <keithp@keithp.com>25 *26 */27 28#include <linux/export.h>29#include <linux/i2c.h>30#include <linux/notifier.h>31#include <linux/slab.h>32#include <linux/sort.h>33#include <linux/string_helpers.h>34#include <linux/timekeeping.h>35#include <linux/types.h>36 37#include <asm/byteorder.h>38 39#include <drm/display/drm_dp_helper.h>40#include <drm/display/drm_dp_tunnel.h>41#include <drm/display/drm_dsc_helper.h>42#include <drm/display/drm_hdmi_helper.h>43#include <drm/drm_atomic_helper.h>44#include <drm/drm_crtc.h>45#include <drm/drm_edid.h>46#include <drm/drm_fixed.h>47#include <drm/drm_probe_helper.h>48 49#include "g4x_dp.h"50#include "i915_drv.h"51#include "i915_irq.h"52#include "i915_reg.h"53#include "intel_alpm.h"54#include "intel_atomic.h"55#include "intel_audio.h"56#include "intel_backlight.h"57#include "intel_combo_phy_regs.h"58#include "intel_connector.h"59#include "intel_crtc.h"60#include "intel_cx0_phy.h"61#include "intel_ddi.h"62#include "intel_de.h"63#include "intel_display_driver.h"64#include "intel_display_types.h"65#include "intel_dp.h"66#include "intel_dp_aux.h"67#include "intel_dp_hdcp.h"68#include "intel_dp_link_training.h"69#include "intel_dp_mst.h"70#include "intel_dp_tunnel.h"71#include "intel_dpio_phy.h"72#include "intel_dpll.h"73#include "intel_drrs.h"74#include "intel_encoder.h"75#include "intel_fifo_underrun.h"76#include "intel_hdcp.h"77#include "intel_hdmi.h"78#include "intel_hotplug.h"79#include "intel_hotplug_irq.h"80#include "intel_lspcon.h"81#include "intel_lvds.h"82#include "intel_modeset_lock.h"83#include "intel_panel.h"84#include "intel_pch_display.h"85#include "intel_pps.h"86#include "intel_psr.h"87#include "intel_quirks.h"88#include "intel_tc.h"89#include "intel_vdsc.h"90#include "intel_vrr.h"91#include "intel_crtc_state_dump.h"92 93#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)94 95/* DP DSC throughput values used for slice count calculations KPixels/s */96#define DP_DSC_PEAK_PIXEL_RATE			272000097#define DP_DSC_MAX_ENC_THROUGHPUT_0		34000098#define DP_DSC_MAX_ENC_THROUGHPUT_1		40000099 100/* Max DSC line buffer depth supported by HW. */101#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH		13102 103/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */104#define DP_DSC_FEC_OVERHEAD_FACTOR		1028530105 106/* Compliance test status bits  */107#define INTEL_DP_RESOLUTION_SHIFT_MASK	0108#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)109#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)110#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)111 112 113/* Constants for DP DSC configurations */114static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};115 116/* With Single pipe configuration, HW is capable of supporting maximum117 * of 4 slices per line.118 */119static const u8 valid_dsc_slicecount[] = {1, 2, 4};120 121/**122 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)123 * @intel_dp: DP struct124 *125 * If a CPU or PCH DP output is attached to an eDP panel, this function126 * will return true, and false otherwise.127 *128 * This function is not safe to use prior to encoder type being set.129 */130bool intel_dp_is_edp(struct intel_dp *intel_dp)131{132	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);133 134	return dig_port->base.type == INTEL_OUTPUT_EDP;135}136 137static void intel_dp_unset_edid(struct intel_dp *intel_dp);138 139/* Is link rate UHBR and thus 128b/132b? */140bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)141{142	return drm_dp_is_uhbr_rate(crtc_state->port_clock);143}144 145/**146 * intel_dp_link_symbol_size - get the link symbol size for a given link rate147 * @rate: link rate in 10kbit/s units148 *149 * Returns the link symbol size in bits/symbol units depending on the link150 * rate -> channel coding.151 */152int intel_dp_link_symbol_size(int rate)153{154	return drm_dp_is_uhbr_rate(rate) ? 32 : 10;155}156 157/**158 * intel_dp_link_symbol_clock - convert link rate to link symbol clock159 * @rate: link rate in 10kbit/s units160 *161 * Returns the link symbol clock frequency in kHz units depending on the162 * link rate and channel coding.163 */164int intel_dp_link_symbol_clock(int rate)165{166	return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));167}168 169static int max_dprx_rate(struct intel_dp *intel_dp)170{171	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))172		return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);173 174	return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);175}176 177static int max_dprx_lane_count(struct intel_dp *intel_dp)178{179	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))180		return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);181 182	return drm_dp_max_lane_count(intel_dp->dpcd);183}184 185static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)186{187	intel_dp->sink_rates[0] = 162000;188	intel_dp->num_sink_rates = 1;189}190 191/* update sink rates from dpcd */192static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)193{194	static const int dp_rates[] = {195		162000, 270000, 540000, 810000196	};197	int i, max_rate;198	int max_lttpr_rate;199 200	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {201		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */202		static const int quirk_rates[] = { 162000, 270000, 324000 };203 204		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));205		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);206 207		return;208	}209 210	/*211	 * Sink rates for 8b/10b.212	 */213	max_rate = max_dprx_rate(intel_dp);214	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);215	if (max_lttpr_rate)216		max_rate = min(max_rate, max_lttpr_rate);217 218	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {219		if (dp_rates[i] > max_rate)220			break;221		intel_dp->sink_rates[i] = dp_rates[i];222	}223 224	/*225	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b226	 * rates and 10 Gbps.227	 */228	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {229		u8 uhbr_rates = 0;230 231		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);232 233		drm_dp_dpcd_readb(&intel_dp->aux,234				  DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);235 236		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {237			/* We have a repeater */238			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&239			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -240							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &241			    DP_PHY_REPEATER_128B132B_SUPPORTED) {242				/* Repeater supports 128b/132b, valid UHBR rates */243				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -244									  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];245			} else {246				/* Does not support 128b/132b */247				uhbr_rates = 0;248			}249		}250 251		if (uhbr_rates & DP_UHBR10)252			intel_dp->sink_rates[i++] = 1000000;253		if (uhbr_rates & DP_UHBR13_5)254			intel_dp->sink_rates[i++] = 1350000;255		if (uhbr_rates & DP_UHBR20)256			intel_dp->sink_rates[i++] = 2000000;257	}258 259	intel_dp->num_sink_rates = i;260}261 262static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)263{264	struct intel_connector *connector = intel_dp->attached_connector;265	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);266	struct intel_encoder *encoder = &intel_dig_port->base;267 268	intel_dp_set_dpcd_sink_rates(intel_dp);269 270	if (intel_dp->num_sink_rates)271		return;272 273	drm_err(&dp_to_i915(intel_dp)->drm,274		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",275		connector->base.base.id, connector->base.name,276		encoder->base.base.id, encoder->base.name);277 278	intel_dp_set_default_sink_rates(intel_dp);279}280 281static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)282{283	intel_dp->max_sink_lane_count = 1;284}285 286static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)287{288	struct intel_connector *connector = intel_dp->attached_connector;289	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);290	struct intel_encoder *encoder = &intel_dig_port->base;291 292	intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);293 294	switch (intel_dp->max_sink_lane_count) {295	case 1:296	case 2:297	case 4:298		return;299	}300 301	drm_err(&dp_to_i915(intel_dp)->drm,302		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",303		connector->base.base.id, connector->base.name,304		encoder->base.base.id, encoder->base.name,305		intel_dp->max_sink_lane_count);306 307	intel_dp_set_default_max_sink_lane_count(intel_dp);308}309 310/* Get length of rates array potentially limited by max_rate. */311static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)312{313	int i;314 315	/* Limit results by potentially reduced max rate */316	for (i = 0; i < len; i++) {317		if (rates[len - i - 1] <= max_rate)318			return len - i;319	}320 321	return 0;322}323 324/* Get length of common rates array potentially limited by max_rate. */325static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,326					  int max_rate)327{328	return intel_dp_rate_limit_len(intel_dp->common_rates,329				       intel_dp->num_common_rates, max_rate);330}331 332int intel_dp_common_rate(struct intel_dp *intel_dp, int index)333{334	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,335			index < 0 || index >= intel_dp->num_common_rates))336		return 162000;337 338	return intel_dp->common_rates[index];339}340 341/* Theoretical max between source and sink */342int intel_dp_max_common_rate(struct intel_dp *intel_dp)343{344	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);345}346 347int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)348{349	int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);350	int max_lanes = dig_port->max_lanes;351 352	if (vbt_max_lanes)353		max_lanes = min(max_lanes, vbt_max_lanes);354 355	return max_lanes;356}357 358/* Theoretical max between source and sink */359int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)360{361	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);362	int source_max = intel_dp_max_source_lane_count(dig_port);363	int sink_max = intel_dp->max_sink_lane_count;364	int lane_max = intel_tc_port_max_lane_count(dig_port);365	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);366 367	if (lttpr_max)368		sink_max = min(sink_max, lttpr_max);369 370	return min3(source_max, sink_max, lane_max);371}372 373static int forced_lane_count(struct intel_dp *intel_dp)374{375	return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));376}377 378int intel_dp_max_lane_count(struct intel_dp *intel_dp)379{380	int lane_count;381 382	if (intel_dp->link.force_lane_count)383		lane_count = forced_lane_count(intel_dp);384	else385		lane_count = intel_dp->link.max_lane_count;386 387	switch (lane_count) {388	case 1:389	case 2:390	case 4:391		return lane_count;392	default:393		MISSING_CASE(lane_count);394		return 1;395	}396}397 398static int intel_dp_min_lane_count(struct intel_dp *intel_dp)399{400	if (intel_dp->link.force_lane_count)401		return forced_lane_count(intel_dp);402 403	return 1;404}405 406/*407 * The required data bandwidth for a mode with given pixel clock and bpp. This408 * is the required net bandwidth independent of the data bandwidth efficiency.409 *410 * TODO: check if callers of this functions should use411 * intel_dp_effective_data_rate() instead.412 */413int414intel_dp_link_required(int pixel_clock, int bpp)415{416	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */417	return DIV_ROUND_UP(pixel_clock * bpp, 8);418}419 420/**421 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead422 * @pixel_clock: pixel clock in kHz423 * @bpp_x16: bits per pixel .4 fixed point format424 * @bw_overhead: BW allocation overhead in 1ppm units425 *426 * Return the effective pixel data rate in kB/sec units taking into account427 * the provided SSC, FEC, DSC BW allocation overhead.428 */429int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,430				 int bw_overhead)431{432	return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),433				1000000 * 16 * 8);434}435 436/**437 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params438 * @intel_dp: Intel DP object439 * @max_dprx_rate: Maximum data rate of the DPRX440 * @max_dprx_lanes: Maximum lane count of the DPRX441 *442 * Calculate the maximum data rate for the provided link parameters taking into443 * account any BW limitations by a DP tunnel attached to @intel_dp.444 *445 * Returns the maximum data rate in kBps units.446 */447int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,448				int max_dprx_rate, int max_dprx_lanes)449{450	int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);451 452	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))453		max_rate = min(max_rate,454			       drm_dp_tunnel_available_bw(intel_dp->tunnel));455 456	return max_rate;457}458 459bool intel_dp_has_joiner(struct intel_dp *intel_dp)460{461	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);462	struct intel_encoder *encoder = &intel_dig_port->base;463	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);464 465	/* eDP MSO is not compatible with joiner */466	if (intel_dp->mso_link_count)467		return false;468 469	return DISPLAY_VER(dev_priv) >= 12 ||470		(DISPLAY_VER(dev_priv) == 11 &&471		 encoder->port != PORT_A);472}473 474static int dg2_max_source_rate(struct intel_dp *intel_dp)475{476	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;477}478 479static int icl_max_source_rate(struct intel_dp *intel_dp)480{481	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;482 483	if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))484		return 540000;485 486	return 810000;487}488 489static int ehl_max_source_rate(struct intel_dp *intel_dp)490{491	if (intel_dp_is_edp(intel_dp))492		return 540000;493 494	return 810000;495}496 497static int mtl_max_source_rate(struct intel_dp *intel_dp)498{499	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;500 501	if (intel_encoder_is_c10phy(encoder))502		return 810000;503 504	if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1))505		return 1350000;506 507	return 2000000;508}509 510static int vbt_max_link_rate(struct intel_dp *intel_dp)511{512	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;513	int max_rate;514 515	max_rate = intel_bios_dp_max_link_rate(encoder->devdata);516 517	if (intel_dp_is_edp(intel_dp)) {518		struct intel_connector *connector = intel_dp->attached_connector;519		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;520 521		if (max_rate && edp_max_rate)522			max_rate = min(max_rate, edp_max_rate);523		else if (edp_max_rate)524			max_rate = edp_max_rate;525	}526 527	return max_rate;528}529 530static void531intel_dp_set_source_rates(struct intel_dp *intel_dp)532{533	/* The values must be in increasing order */534	static const int bmg_rates[] = {535		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,536		810000,	1000000, 1350000,537	};538	static const int mtl_rates[] = {539		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,540		810000,	1000000, 2000000,541	};542	static const int icl_rates[] = {543		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,544		1000000, 1350000,545	};546	static const int bxt_rates[] = {547		162000, 216000, 243000, 270000, 324000, 432000, 540000548	};549	static const int skl_rates[] = {550		162000, 216000, 270000, 324000, 432000, 540000551	};552	static const int hsw_rates[] = {553		162000, 270000, 540000554	};555	static const int g4x_rates[] = {556		162000, 270000557	};558	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);559	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);560	const int *source_rates;561	int size, max_rate = 0, vbt_max_rate;562 563	/* This should only be done once */564	drm_WARN_ON(&dev_priv->drm,565		    intel_dp->source_rates || intel_dp->num_source_rates);566 567	if (DISPLAY_VER(dev_priv) >= 14) {568		if (IS_BATTLEMAGE(dev_priv)) {569			source_rates = bmg_rates;570			size = ARRAY_SIZE(bmg_rates);571		} else {572			source_rates = mtl_rates;573			size = ARRAY_SIZE(mtl_rates);574		}575		max_rate = mtl_max_source_rate(intel_dp);576	} else if (DISPLAY_VER(dev_priv) >= 11) {577		source_rates = icl_rates;578		size = ARRAY_SIZE(icl_rates);579		if (IS_DG2(dev_priv))580			max_rate = dg2_max_source_rate(intel_dp);581		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||582			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))583			max_rate = 810000;584		else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))585			max_rate = ehl_max_source_rate(intel_dp);586		else587			max_rate = icl_max_source_rate(intel_dp);588	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {589		source_rates = bxt_rates;590		size = ARRAY_SIZE(bxt_rates);591	} else if (DISPLAY_VER(dev_priv) == 9) {592		source_rates = skl_rates;593		size = ARRAY_SIZE(skl_rates);594	} else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||595		   IS_BROADWELL(dev_priv)) {596		source_rates = hsw_rates;597		size = ARRAY_SIZE(hsw_rates);598	} else {599		source_rates = g4x_rates;600		size = ARRAY_SIZE(g4x_rates);601	}602 603	vbt_max_rate = vbt_max_link_rate(intel_dp);604	if (max_rate && vbt_max_rate)605		max_rate = min(max_rate, vbt_max_rate);606	else if (vbt_max_rate)607		max_rate = vbt_max_rate;608 609	if (max_rate)610		size = intel_dp_rate_limit_len(source_rates, size, max_rate);611 612	intel_dp->source_rates = source_rates;613	intel_dp->num_source_rates = size;614}615 616static int intersect_rates(const int *source_rates, int source_len,617			   const int *sink_rates, int sink_len,618			   int *common_rates)619{620	int i = 0, j = 0, k = 0;621 622	while (i < source_len && j < sink_len) {623		if (source_rates[i] == sink_rates[j]) {624			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))625				return k;626			common_rates[k] = source_rates[i];627			++k;628			++i;629			++j;630		} else if (source_rates[i] < sink_rates[j]) {631			++i;632		} else {633			++j;634		}635	}636	return k;637}638 639/* return index of rate in rates array, or -1 if not found */640int intel_dp_rate_index(const int *rates, int len, int rate)641{642	int i;643 644	for (i = 0; i < len; i++)645		if (rate == rates[i])646			return i;647 648	return -1;649}650 651static int intel_dp_link_config_rate(struct intel_dp *intel_dp,652				     const struct intel_dp_link_config *lc)653{654	return intel_dp_common_rate(intel_dp, lc->link_rate_idx);655}656 657static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)658{659	return 1 << lc->lane_count_exp;660}661 662static int intel_dp_link_config_bw(struct intel_dp *intel_dp,663				   const struct intel_dp_link_config *lc)664{665	return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),666					 intel_dp_link_config_lane_count(lc));667}668 669static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)670{671	struct intel_dp *intel_dp = (struct intel_dp *)p;	/* remove const */672	const struct intel_dp_link_config *lc_a = a;673	const struct intel_dp_link_config *lc_b = b;674	int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);675	int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);676 677	if (bw_a != bw_b)678		return bw_a - bw_b;679 680	return intel_dp_link_config_rate(intel_dp, lc_a) -681	       intel_dp_link_config_rate(intel_dp, lc_b);682}683 684static void intel_dp_link_config_init(struct intel_dp *intel_dp)685{686	struct drm_i915_private *i915 = dp_to_i915(intel_dp);687	struct intel_dp_link_config *lc;688	int num_common_lane_configs;689	int i;690	int j;691 692	if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))693		return;694 695	num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;696 697	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >698				    ARRAY_SIZE(intel_dp->link.configs)))699		return;700 701	intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;702 703	lc = &intel_dp->link.configs[0];704	for (i = 0; i < intel_dp->num_common_rates; i++) {705		for (j = 0; j < num_common_lane_configs; j++) {706			lc->lane_count_exp = j;707			lc->link_rate_idx = i;708 709			lc++;710		}711	}712 713	sort_r(intel_dp->link.configs, intel_dp->link.num_configs,714	       sizeof(intel_dp->link.configs[0]),715	       link_config_cmp_by_bw, NULL,716	       intel_dp);717}718 719void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)720{721	struct drm_i915_private *i915 = dp_to_i915(intel_dp);722	const struct intel_dp_link_config *lc;723 724	if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))725		idx = 0;726 727	lc = &intel_dp->link.configs[idx];728 729	*link_rate = intel_dp_link_config_rate(intel_dp, lc);730	*lane_count = intel_dp_link_config_lane_count(lc);731}732 733int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)734{735	int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,736						link_rate);737	int lane_count_exp = ilog2(lane_count);738	int i;739 740	for (i = 0; i < intel_dp->link.num_configs; i++) {741		const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];742 743		if (lc->lane_count_exp == lane_count_exp &&744		    lc->link_rate_idx == link_rate_idx)745			return i;746	}747 748	return -1;749}750 751static void intel_dp_set_common_rates(struct intel_dp *intel_dp)752{753	struct drm_i915_private *i915 = dp_to_i915(intel_dp);754 755	drm_WARN_ON(&i915->drm,756		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);757 758	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,759						     intel_dp->num_source_rates,760						     intel_dp->sink_rates,761						     intel_dp->num_sink_rates,762						     intel_dp->common_rates);763 764	/* Paranoia, there should always be something in common. */765	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {766		intel_dp->common_rates[0] = 162000;767		intel_dp->num_common_rates = 1;768	}769 770	intel_dp_link_config_init(intel_dp);771}772 773static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,774				       u8 lane_count)775{776	/*777	 * FIXME: we need to synchronize the current link parameters with778	 * hardware readout. Currently fast link training doesn't work on779	 * boot-up.780	 */781	if (link_rate == 0 ||782	    link_rate > intel_dp->link.max_rate)783		return false;784 785	if (lane_count == 0 ||786	    lane_count > intel_dp_max_lane_count(intel_dp))787		return false;788 789	return true;790}791 792u32 intel_dp_mode_to_fec_clock(u32 mode_clock)793{794	return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),795		       1000000U);796}797 798int intel_dp_bw_fec_overhead(bool fec_enabled)799{800	/*801	 * TODO: Calculate the actual overhead for a given mode.802	 * The hard-coded 1/0.972261=2.853% overhead factor803	 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +804	 * 0.453% DSC overhead. This is enough for a 3840 width mode,805	 * which has a DSC overhead of up to ~0.2%, but may not be806	 * enough for a 1024 width mode where this is ~0.8% (on a 4807	 * lane DP link, with 2 DSC slices and 8 bpp color depth).808	 */809	return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;810}811 812static int813small_joiner_ram_size_bits(struct drm_i915_private *i915)814{815	if (DISPLAY_VER(i915) >= 13)816		return 17280 * 8;817	else if (DISPLAY_VER(i915) >= 11)818		return 7680 * 8;819	else820		return 6144 * 8;821}822 823u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)824{825	u32 bits_per_pixel = bpp;826	int i;827 828	/* Error out if the max bpp is less than smallest allowed valid bpp */829	if (bits_per_pixel < valid_dsc_bpp[0]) {830		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",831			    bits_per_pixel, valid_dsc_bpp[0]);832		return 0;833	}834 835	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */836	if (DISPLAY_VER(i915) >= 13) {837		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);838 839		/*840		 * According to BSpec, 27 is the max DSC output bpp,841		 * 8 is the min DSC output bpp.842		 * While we can still clamp higher bpp values to 27, saving bandwidth,843		 * if it is required to oompress up to bpp < 8, means we can't do844		 * that and probably means we can't fit the required mode, even with845		 * DSC enabled.846		 */847		if (bits_per_pixel < 8) {848			drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",849				    bits_per_pixel);850			return 0;851		}852		bits_per_pixel = min_t(u32, bits_per_pixel, 27);853	} else {854		/* Find the nearest match in the array of known BPPs from VESA */855		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {856			if (bits_per_pixel < valid_dsc_bpp[i + 1])857				break;858		}859		drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",860			    bits_per_pixel, valid_dsc_bpp[i]);861 862		bits_per_pixel = valid_dsc_bpp[i];863	}864 865	return bits_per_pixel;866}867 868static869u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,870				       u32 mode_clock, u32 mode_hdisplay,871				       bool bigjoiner)872{873	u32 max_bpp_small_joiner_ram;874 875	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */876	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;877 878	if (bigjoiner) {879		int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;880		/* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */881		int ppc = 2;882		u32 max_bpp_bigjoiner =883			i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /884			intel_dp_mode_to_fec_clock(mode_clock);885 886		max_bpp_small_joiner_ram *= 2;887 888		return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);889	}890 891	return max_bpp_small_joiner_ram;892}893 894u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,895					u32 link_clock, u32 lane_count,896					u32 mode_clock, u32 mode_hdisplay,897					bool bigjoiner,898					enum intel_output_format output_format,899					u32 pipe_bpp,900					u32 timeslots)901{902	u32 bits_per_pixel, joiner_max_bpp;903 904	/*905	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*906	 * (LinkSymbolClock)* 8 * (TimeSlots / 64)907	 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)908	 * for MST -> TimeSlots has to be calculated, based on mode requirements909	 *910	 * Due to FEC overhead, the available bw is reduced to 97.2261%.911	 * To support the given mode:912	 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead913	 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead914	 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock915	 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /916	 *		       (ModeClock / FEC Overhead)917	 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /918	 *		       (ModeClock / FEC Overhead * 8)919	 */920	bits_per_pixel = ((link_clock * lane_count) * timeslots) /921			 (intel_dp_mode_to_fec_clock(mode_clock) * 8);922 923	/* Bandwidth required for 420 is half, that of 444 format */924	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)925		bits_per_pixel *= 2;926 927	/*928	 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum929	 * supported PPS value can be 63.9375 and with the further930	 * mention that for 420, 422 formats, bpp should be programmed double931	 * the target bpp restricting our target bpp to be 31.9375 at max.932	 */933	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)934		bits_per_pixel = min_t(u32, bits_per_pixel, 31);935 936	drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "937				"total bw %u pixel clock %u\n",938				bits_per_pixel, timeslots,939				(link_clock * lane_count * 8),940				intel_dp_mode_to_fec_clock(mode_clock));941 942	joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,943							    mode_hdisplay, bigjoiner);944	bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);945 946	bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);947 948	return bits_per_pixel;949}950 951u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,952				int mode_clock, int mode_hdisplay,953				bool bigjoiner)954{955	struct drm_i915_private *i915 = to_i915(connector->base.dev);956	u8 min_slice_count, i;957	int max_slice_width;958 959	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)960		min_slice_count = DIV_ROUND_UP(mode_clock,961					       DP_DSC_MAX_ENC_THROUGHPUT_0);962	else963		min_slice_count = DIV_ROUND_UP(mode_clock,964					       DP_DSC_MAX_ENC_THROUGHPUT_1);965 966	/*967	 * Due to some DSC engine BW limitations, we need to enable second968	 * slice and VDSC engine, whenever we approach close enough to max CDCLK969	 */970	if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))971		min_slice_count = max_t(u8, min_slice_count, 2);972 973	max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);974	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {975		drm_dbg_kms(&i915->drm,976			    "Unsupported slice width %d by DP DSC Sink device\n",977			    max_slice_width);978		return 0;979	}980	/* Also take into account max slice width */981	min_slice_count = max_t(u8, min_slice_count,982				DIV_ROUND_UP(mode_hdisplay,983					     max_slice_width));984 985	/* Find the closest match to the valid slice count values */986	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {987		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;988 989		if (test_slice_count >990		    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))991			break;992 993		/* big joiner needs small joiner to be enabled */994		if (bigjoiner && test_slice_count < 4)995			continue;996 997		if (min_slice_count <= test_slice_count)998			return test_slice_count;999	}1000 1001	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",1002		    min_slice_count);1003	return 0;1004}1005 1006static bool source_can_output(struct intel_dp *intel_dp,1007			      enum intel_output_format format)1008{1009	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1010 1011	switch (format) {1012	case INTEL_OUTPUT_FORMAT_RGB:1013		return true;1014 1015	case INTEL_OUTPUT_FORMAT_YCBCR444:1016		/*1017		 * No YCbCr output support on gmch platforms.1018		 * Also, ILK doesn't seem capable of DP YCbCr output.1019		 * The displayed image is severly corrupted. SNB+ is fine.1020		 */1021		return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);1022 1023	case INTEL_OUTPUT_FORMAT_YCBCR420:1024		/* Platform < Gen 11 cannot output YCbCr420 format */1025		return DISPLAY_VER(i915) >= 11;1026 1027	default:1028		MISSING_CASE(format);1029		return false;1030	}1031}1032 1033static bool1034dfp_can_convert_from_rgb(struct intel_dp *intel_dp,1035			 enum intel_output_format sink_format)1036{1037	if (!drm_dp_is_branch(intel_dp->dpcd))1038		return false;1039 1040	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)1041		return intel_dp->dfp.rgb_to_ycbcr;1042 1043	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)1044		return intel_dp->dfp.rgb_to_ycbcr &&1045			intel_dp->dfp.ycbcr_444_to_420;1046 1047	return false;1048}1049 1050static bool1051dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,1052			      enum intel_output_format sink_format)1053{1054	if (!drm_dp_is_branch(intel_dp->dpcd))1055		return false;1056 1057	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)1058		return intel_dp->dfp.ycbcr_444_to_420;1059 1060	return false;1061}1062 1063static bool1064dfp_can_convert(struct intel_dp *intel_dp,1065		enum intel_output_format output_format,1066		enum intel_output_format sink_format)1067{1068	switch (output_format) {1069	case INTEL_OUTPUT_FORMAT_RGB:1070		return dfp_can_convert_from_rgb(intel_dp, sink_format);1071	case INTEL_OUTPUT_FORMAT_YCBCR444:1072		return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);1073	default:1074		MISSING_CASE(output_format);1075		return false;1076	}1077 1078	return false;1079}1080 1081static enum intel_output_format1082intel_dp_output_format(struct intel_connector *connector,1083		       enum intel_output_format sink_format)1084{1085	struct intel_dp *intel_dp = intel_attached_dp(connector);1086	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1087	enum intel_output_format force_dsc_output_format =1088		intel_dp->force_dsc_output_format;1089	enum intel_output_format output_format;1090	if (force_dsc_output_format) {1091		if (source_can_output(intel_dp, force_dsc_output_format) &&1092		    (!drm_dp_is_branch(intel_dp->dpcd) ||1093		     sink_format != force_dsc_output_format ||1094		     dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))1095			return force_dsc_output_format;1096 1097		drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");1098	}1099 1100	if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||1101	    dfp_can_convert_from_rgb(intel_dp, sink_format))1102		output_format = INTEL_OUTPUT_FORMAT_RGB;1103 1104	else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||1105		 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))1106		output_format = INTEL_OUTPUT_FORMAT_YCBCR444;1107 1108	else1109		output_format = INTEL_OUTPUT_FORMAT_YCBCR420;1110 1111	drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));1112 1113	return output_format;1114}1115 1116int intel_dp_min_bpp(enum intel_output_format output_format)1117{1118	if (output_format == INTEL_OUTPUT_FORMAT_RGB)1119		return 6 * 3;1120	else1121		return 8 * 3;1122}1123 1124int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)1125{1126	/*1127	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output1128	 * format of the number of bytes per pixel will be half the number1129	 * of bytes of RGB pixel.1130	 */1131	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)1132		bpp /= 2;1133 1134	return bpp;1135}1136 1137static enum intel_output_format1138intel_dp_sink_format(struct intel_connector *connector,1139		     const struct drm_display_mode *mode)1140{1141	const struct drm_display_info *info = &connector->base.display_info;1142 1143	if (drm_mode_is_420_only(info, mode))1144		return INTEL_OUTPUT_FORMAT_YCBCR420;1145 1146	return INTEL_OUTPUT_FORMAT_RGB;1147}1148 1149static int1150intel_dp_mode_min_output_bpp(struct intel_connector *connector,1151			     const struct drm_display_mode *mode)1152{1153	enum intel_output_format output_format, sink_format;1154 1155	sink_format = intel_dp_sink_format(connector, mode);1156 1157	output_format = intel_dp_output_format(connector, sink_format);1158 1159	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));1160}1161 1162static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,1163				  int hdisplay)1164{1165	/*1166	 * Older platforms don't like hdisplay==4096 with DP.1167	 *1168	 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline1169	 * and frame counter increment), but we don't get vblank interrupts,1170	 * and the pipe underruns immediately. The link also doesn't seem1171	 * to get trained properly.1172	 *1173	 * On CHV the vblank interrupts don't seem to disappear but1174	 * otherwise the symptoms are similar.1175	 *1176	 * TODO: confirm the behaviour on HSW+1177	 */1178	return hdisplay == 4096 && !HAS_DDI(dev_priv);1179}1180 1181static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)1182{1183	struct intel_connector *connector = intel_dp->attached_connector;1184	const struct drm_display_info *info = &connector->base.display_info;1185	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;1186 1187	/* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */1188	if (max_tmds_clock && info->max_tmds_clock)1189		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);1190 1191	return max_tmds_clock;1192}1193 1194static enum drm_mode_status1195intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,1196			  int clock, int bpc,1197			  enum intel_output_format sink_format,1198			  bool respect_downstream_limits)1199{1200	int tmds_clock, min_tmds_clock, max_tmds_clock;1201 1202	if (!respect_downstream_limits)1203		return MODE_OK;1204 1205	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);1206 1207	min_tmds_clock = intel_dp->dfp.min_tmds_clock;1208	max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);1209 1210	if (min_tmds_clock && tmds_clock < min_tmds_clock)1211		return MODE_CLOCK_LOW;1212 1213	if (max_tmds_clock && tmds_clock > max_tmds_clock)1214		return MODE_CLOCK_HIGH;1215 1216	return MODE_OK;1217}1218 1219static enum drm_mode_status1220intel_dp_mode_valid_downstream(struct intel_connector *connector,1221			       const struct drm_display_mode *mode,1222			       int target_clock)1223{1224	struct intel_dp *intel_dp = intel_attached_dp(connector);1225	const struct drm_display_info *info = &connector->base.display_info;1226	enum drm_mode_status status;1227	enum intel_output_format sink_format;1228 1229	/* If PCON supports FRL MODE, check FRL bandwidth constraints */1230	if (intel_dp->dfp.pcon_max_frl_bw) {1231		int target_bw;1232		int max_frl_bw;1233		int bpp = intel_dp_mode_min_output_bpp(connector, mode);1234 1235		target_bw = bpp * target_clock;1236 1237		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;1238 1239		/* converting bw from Gbps to Kbps*/1240		max_frl_bw = max_frl_bw * 1000000;1241 1242		if (target_bw > max_frl_bw)1243			return MODE_CLOCK_HIGH;1244 1245		return MODE_OK;1246	}1247 1248	if (intel_dp->dfp.max_dotclock &&1249	    target_clock > intel_dp->dfp.max_dotclock)1250		return MODE_CLOCK_HIGH;1251 1252	sink_format = intel_dp_sink_format(connector, mode);1253 1254	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */1255	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,1256					   8, sink_format, true);1257 1258	if (status != MODE_OK) {1259		if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||1260		    !connector->base.ycbcr_420_allowed ||1261		    !drm_mode_is_420_also(info, mode))1262			return status;1263		sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;1264		status = intel_dp_tmds_clock_valid(intel_dp, target_clock,1265						   8, sink_format, true);1266		if (status != MODE_OK)1267			return status;1268	}1269 1270	return MODE_OK;1271}1272 1273bool intel_dp_need_joiner(struct intel_dp *intel_dp,1274			  struct intel_connector *connector,1275			  int hdisplay, int clock)1276{1277	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1278 1279	if (!intel_dp_has_joiner(intel_dp))1280		return false;1281 1282	return clock > i915->display.cdclk.max_dotclk_freq || hdisplay > 5120 ||1283	       connector->force_bigjoiner_enable;1284}1285 1286bool intel_dp_has_dsc(const struct intel_connector *connector)1287{1288	struct drm_i915_private *i915 = to_i915(connector->base.dev);1289 1290	if (!HAS_DSC(i915))1291		return false;1292 1293	if (connector->mst_port && !HAS_DSC_MST(i915))1294		return false;1295 1296	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&1297	    connector->panel.vbt.edp.dsc_disable)1298		return false;1299 1300	if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))1301		return false;1302 1303	return true;1304}1305 1306static enum drm_mode_status1307intel_dp_mode_valid(struct drm_connector *_connector,1308		    struct drm_display_mode *mode)1309{1310	struct intel_connector *connector = to_intel_connector(_connector);1311	struct intel_dp *intel_dp = intel_attached_dp(connector);1312	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);1313	const struct drm_display_mode *fixed_mode;1314	int target_clock = mode->clock;1315	int max_rate, mode_rate, max_lanes, max_link_clock;1316	int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;1317	u16 dsc_max_compressed_bpp = 0;1318	u8 dsc_slice_count = 0;1319	enum drm_mode_status status;1320	bool dsc = false, joiner = false;1321 1322	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);1323	if (status != MODE_OK)1324		return status;1325 1326	if (mode->flags & DRM_MODE_FLAG_DBLCLK)1327		return MODE_H_ILLEGAL;1328 1329	if (mode->clock < 10000)1330		return MODE_CLOCK_LOW;1331 1332	fixed_mode = intel_panel_fixed_mode(connector, mode);1333	if (intel_dp_is_edp(intel_dp) && fixed_mode) {1334		status = intel_panel_mode_valid(connector, mode);1335		if (status != MODE_OK)1336			return status;1337 1338		target_clock = fixed_mode->clock;1339	}1340 1341	if (intel_dp_need_joiner(intel_dp, connector,1342				 mode->hdisplay, target_clock)) {1343		joiner = true;1344		max_dotclk *= 2;1345	}1346	if (target_clock > max_dotclk)1347		return MODE_CLOCK_HIGH;1348 1349	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))1350		return MODE_H_ILLEGAL;1351 1352	max_link_clock = intel_dp_max_link_rate(intel_dp);1353	max_lanes = intel_dp_max_lane_count(intel_dp);1354 1355	max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);1356 1357	mode_rate = intel_dp_link_required(target_clock,1358					   intel_dp_mode_min_output_bpp(connector, mode));1359 1360	if (intel_dp_has_dsc(connector)) {1361		enum intel_output_format sink_format, output_format;1362		int pipe_bpp;1363 1364		sink_format = intel_dp_sink_format(connector, mode);1365		output_format = intel_dp_output_format(connector, sink_format);1366		/*1367		 * TBD pass the connector BPC,1368		 * for now U8_MAX so that max BPC on that platform would be picked1369		 */1370		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);1371 1372		/*1373		 * Output bpp is stored in 6.4 format so right shift by 4 to get the1374		 * integer value since we support only integer values of bpp.1375		 */1376		if (intel_dp_is_edp(intel_dp)) {1377			dsc_max_compressed_bpp =1378				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;1379			dsc_slice_count =1380				drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,1381								true);1382		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {1383			dsc_max_compressed_bpp =1384				intel_dp_dsc_get_max_compressed_bpp(dev_priv,1385								    max_link_clock,1386								    max_lanes,1387								    target_clock,1388								    mode->hdisplay,1389								    joiner,1390								    output_format,1391								    pipe_bpp, 64);1392			dsc_slice_count =1393				intel_dp_dsc_get_slice_count(connector,1394							     target_clock,1395							     mode->hdisplay,1396							     joiner);1397		}1398 1399		dsc = dsc_max_compressed_bpp && dsc_slice_count;1400	}1401 1402	if (intel_dp_joiner_needs_dsc(dev_priv, joiner) && !dsc)1403		return MODE_CLOCK_HIGH;1404 1405	if (mode_rate > max_rate && !dsc)1406		return MODE_CLOCK_HIGH;1407 1408	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);1409	if (status != MODE_OK)1410		return status;1411 1412	return intel_mode_valid_max_plane_size(dev_priv, mode, joiner);1413}1414 1415bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)1416{1417	return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);1418}1419 1420bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)1421{1422	return DISPLAY_VER(i915) >= 10;1423}1424 1425static void snprintf_int_array(char *str, size_t len,1426			       const int *array, int nelem)1427{1428	int i;1429 1430	str[0] = '\0';1431 1432	for (i = 0; i < nelem; i++) {1433		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);1434		if (r >= len)1435			return;1436		str += r;1437		len -= r;1438	}1439}1440 1441static void intel_dp_print_rates(struct intel_dp *intel_dp)1442{1443	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1444	char str[128]; /* FIXME: too big for stack? */1445 1446	if (!drm_debug_enabled(DRM_UT_KMS))1447		return;1448 1449	snprintf_int_array(str, sizeof(str),1450			   intel_dp->source_rates, intel_dp->num_source_rates);1451	drm_dbg_kms(&i915->drm, "source rates: %s\n", str);1452 1453	snprintf_int_array(str, sizeof(str),1454			   intel_dp->sink_rates, intel_dp->num_sink_rates);1455	drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);1456 1457	snprintf_int_array(str, sizeof(str),1458			   intel_dp->common_rates, intel_dp->num_common_rates);1459	drm_dbg_kms(&i915->drm, "common rates: %s\n", str);1460}1461 1462static int forced_link_rate(struct intel_dp *intel_dp)1463{1464	int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);1465 1466	if (len == 0)1467		return intel_dp_common_rate(intel_dp, 0);1468 1469	return intel_dp_common_rate(intel_dp, len - 1);1470}1471 1472int1473intel_dp_max_link_rate(struct intel_dp *intel_dp)1474{1475	int len;1476 1477	if (intel_dp->link.force_rate)1478		return forced_link_rate(intel_dp);1479 1480	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);1481 1482	return intel_dp_common_rate(intel_dp, len - 1);1483}1484 1485static int1486intel_dp_min_link_rate(struct intel_dp *intel_dp)1487{1488	if (intel_dp->link.force_rate)1489		return forced_link_rate(intel_dp);1490 1491	return intel_dp_common_rate(intel_dp, 0);1492}1493 1494int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)1495{1496	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1497	int i = intel_dp_rate_index(intel_dp->sink_rates,1498				    intel_dp->num_sink_rates, rate);1499 1500	if (drm_WARN_ON(&i915->drm, i < 0))1501		i = 0;1502 1503	return i;1504}1505 1506void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,1507			   u8 *link_bw, u8 *rate_select)1508{1509	/* eDP 1.4 rate select method. */1510	if (intel_dp->use_rate_select) {1511		*link_bw = 0;1512		*rate_select =1513			intel_dp_rate_select(intel_dp, port_clock);1514	} else {1515		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);1516		*rate_select = 0;1517	}1518}1519 1520bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)1521{1522	struct intel_connector *connector = intel_dp->attached_connector;1523 1524	return connector->base.display_info.is_hdmi;1525}1526 1527static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,1528					 const struct intel_crtc_state *pipe_config)1529{1530	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;1531	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);1532 1533	if (DISPLAY_VER(dev_priv) >= 12)1534		return true;1535 1536	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&1537	    !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))1538		return true;1539 1540	return false;1541}1542 1543bool intel_dp_supports_fec(struct intel_dp *intel_dp,1544			   const struct intel_connector *connector,1545			   const struct intel_crtc_state *pipe_config)1546{1547	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&1548		drm_dp_sink_supports_fec(connector->dp.fec_capability);1549}1550 1551bool intel_dp_supports_dsc(const struct intel_connector *connector,1552			   const struct intel_crtc_state *crtc_state)1553{1554	if (!intel_dp_has_dsc(connector))1555		return false;1556 1557	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)1558		return false;1559 1560	return intel_dsc_source_support(crtc_state);1561}1562 1563static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,1564				     const struct intel_crtc_state *crtc_state,1565				     int bpc, bool respect_downstream_limits)1566{1567	int clock = crtc_state->hw.adjusted_mode.crtc_clock;1568 1569	/*1570	 * Current bpc could already be below 8bpc due to1571	 * FDI bandwidth constraints or other limits.1572	 * HDMI minimum is 8bpc however.1573	 */1574	bpc = max(bpc, 8);1575 1576	/*1577	 * We will never exceed downstream TMDS clock limits while1578	 * attempting deep color. If the user insists on forcing an1579	 * out of spec mode they will have to be satisfied with 8bpc.1580	 */1581	if (!respect_downstream_limits)1582		bpc = 8;1583 1584	for (; bpc >= 8; bpc -= 2) {1585		if (intel_hdmi_bpc_possible(crtc_state, bpc,1586					    intel_dp_has_hdmi_sink(intel_dp)) &&1587		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,1588					      respect_downstream_limits) == MODE_OK)1589			return bpc;1590	}1591 1592	return -EINVAL;1593}1594 1595static int intel_dp_max_bpp(struct intel_dp *intel_dp,1596			    const struct intel_crtc_state *crtc_state,1597			    bool respect_downstream_limits)1598{1599	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);1600	struct intel_connector *intel_connector = intel_dp->attached_connector;1601	int bpp, bpc;1602 1603	bpc = crtc_state->pipe_bpp / 3;1604 1605	if (intel_dp->dfp.max_bpc)1606		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);1607 1608	if (intel_dp->dfp.min_tmds_clock) {1609		int max_hdmi_bpc;1610 1611		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,1612							 respect_downstream_limits);1613		if (max_hdmi_bpc < 0)1614			return 0;1615 1616		bpc = min(bpc, max_hdmi_bpc);1617	}1618 1619	bpp = bpc * 3;1620	if (intel_dp_is_edp(intel_dp)) {1621		/* Get bpp from vbt only for panels that dont have bpp in edid */1622		if (intel_connector->base.display_info.bpc == 0 &&1623		    intel_connector->panel.vbt.edp.bpp &&1624		    intel_connector->panel.vbt.edp.bpp < bpp) {1625			drm_dbg_kms(&dev_priv->drm,1626				    "clamping bpp for eDP panel to BIOS-provided %i\n",1627				    intel_connector->panel.vbt.edp.bpp);1628			bpp = intel_connector->panel.vbt.edp.bpp;1629		}1630	}1631 1632	return bpp;1633}1634 1635/* Adjust link config limits based on compliance test requests. */1636void1637intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,1638				  struct intel_crtc_state *pipe_config,1639				  struct link_config_limits *limits)1640{1641	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1642 1643	/* For DP Compliance we override the computed bpp for the pipe */1644	if (intel_dp->compliance.test_data.bpc != 0) {1645		int bpp = 3 * intel_dp->compliance.test_data.bpc;1646 1647		limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;1648		pipe_config->dither_force_disable = bpp == 6 * 3;1649 1650		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);1651	}1652 1653	/* Use values requested by Compliance Test Request */1654	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {1655		int index;1656 1657		/* Validate the compliance test data since max values1658		 * might have changed due to link train fallback.1659		 */1660		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,1661					       intel_dp->compliance.test_lane_count)) {1662			index = intel_dp_rate_index(intel_dp->common_rates,1663						    intel_dp->num_common_rates,1664						    intel_dp->compliance.test_link_rate);1665			if (index >= 0)1666				limits->min_rate = limits->max_rate =1667					intel_dp->compliance.test_link_rate;1668			limits->min_lane_count = limits->max_lane_count =1669				intel_dp->compliance.test_lane_count;1670		}1671	}1672}1673 1674static bool has_seamless_m_n(struct intel_connector *connector)1675{1676	struct drm_i915_private *i915 = to_i915(connector->base.dev);1677 1678	/*1679	 * Seamless M/N reprogramming only implemented1680	 * for BDW+ double buffered M/N registers so far.1681	 */1682	return HAS_DOUBLE_BUFFERED_M_N(i915) &&1683		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;1684}1685 1686static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,1687			       const struct drm_connector_state *conn_state)1688{1689	struct intel_connector *connector = to_intel_connector(conn_state->connector);1690	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;1691 1692	/* FIXME a bit of a mess wrt clock vs. crtc_clock */1693	if (has_seamless_m_n(connector))1694		return intel_panel_highest_mode(connector, adjusted_mode)->clock;1695	else1696		return adjusted_mode->crtc_clock;1697}1698 1699/* Optimize link config in order: max bpp, min clock, min lanes */1700static int1701intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,1702				  struct intel_crtc_state *pipe_config,1703				  const struct drm_connector_state *conn_state,1704				  const struct link_config_limits *limits)1705{1706	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);1707	int mode_rate, link_rate, link_avail;1708 1709	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);1710	     bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);1711	     bpp -= 2 * 3) {1712		int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);1713 1714		mode_rate = intel_dp_link_required(clock, link_bpp);1715 1716		for (i = 0; i < intel_dp->num_common_rates; i++) {1717			link_rate = intel_dp_common_rate(intel_dp, i);1718			if (link_rate < limits->min_rate ||1719			    link_rate > limits->max_rate)1720				continue;1721 1722			for (lane_count = limits->min_lane_count;1723			     lane_count <= limits->max_lane_count;1724			     lane_count <<= 1) {1725				link_avail = intel_dp_max_link_data_rate(intel_dp,1726									 link_rate,1727									 lane_count);1728 1729 1730				if (mode_rate <= link_avail) {1731					pipe_config->lane_count = lane_count;1732					pipe_config->pipe_bpp = bpp;1733					pipe_config->port_clock = link_rate;1734 1735					return 0;1736				}1737			}1738		}1739	}1740 1741	return -EINVAL;1742}1743 1744static1745u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)1746{1747	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */1748	if (DISPLAY_VER(i915) >= 12)1749		return 12;1750	if (DISPLAY_VER(i915) == 11)1751		return 10;1752 1753	return 0;1754}1755 1756int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,1757				 u8 max_req_bpc)1758{1759	struct drm_i915_private *i915 = to_i915(connector->base.dev);1760	int i, num_bpc;1761	u8 dsc_bpc[3] = {};1762	u8 dsc_max_bpc;1763 1764	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);1765 1766	if (!dsc_max_bpc)1767		return dsc_max_bpc;1768 1769	dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);1770 1771	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,1772						       dsc_bpc);1773	for (i = 0; i < num_bpc; i++) {1774		if (dsc_max_bpc >= dsc_bpc[i])1775			return dsc_bpc[i] * 3;1776	}1777 1778	return 0;1779}1780 1781static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)1782{1783	return DISPLAY_VER(i915) >= 14 ? 2 : 1;1784}1785 1786static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1787{1788	return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>1789		DP_DSC_MINOR_SHIFT;1790}1791 1792static int intel_dp_get_slice_height(int vactive)1793{1794	int slice_height;1795 1796	/*1797	 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 1081798	 * lines is an optimal slice height, but any size can be used as long as1799	 * vertical active integer multiple and maximum vertical slice count1800	 * requirements are met.1801	 */1802	for (slice_height = 108; slice_height <= vactive; slice_height += 2)1803		if (vactive % slice_height == 0)1804			return slice_height;1805 1806	/*1807	 * Highly unlikely we reach here as most of the resolutions will end up1808	 * finding appropriate slice_height in above loop but returning1809	 * slice_height as 2 here as it should work with all resolutions.1810	 */1811	return 2;1812}1813 1814static int intel_dp_dsc_compute_params(const struct intel_connector *connector,1815				       struct intel_crtc_state *crtc_state)1816{1817	struct drm_i915_private *i915 = to_i915(connector->base.dev);1818	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;1819	int ret;1820 1821	/*1822	 * RC_MODEL_SIZE is currently a constant across all configurations.1823	 *1824	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and1825	 * DP_DSC_RC_BUF_SIZE for this.1826	 */1827	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;1828	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;1829 1830	vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);1831 1832	ret = intel_dsc_compute_params(crtc_state);1833	if (ret)1834		return ret;1835 1836	vdsc_cfg->dsc_version_major =1837		(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &1838		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;1839	vdsc_cfg->dsc_version_minor =1840		min(intel_dp_source_dsc_version_minor(i915),1841		    intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));1842	if (vdsc_cfg->convert_rgb)1843		vdsc_cfg->convert_rgb =1844			connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &1845			DP_DSC_RGB;1846 1847	vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,1848				       drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));1849	if (!vdsc_cfg->line_buf_depth) {1850		drm_dbg_kms(&i915->drm,1851			    "DSC Sink Line Buffer Depth invalid\n");1852		return -EINVAL;1853	}1854 1855	vdsc_cfg->block_pred_enable =1856		connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &1857		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;1858 1859	return drm_dsc_compute_rc_parameters(vdsc_cfg);1860}1861 1862static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,1863					 enum intel_output_format output_format)1864{1865	struct drm_i915_private *i915 = to_i915(connector->base.dev);1866	u8 sink_dsc_format;1867 1868	switch (output_format) {1869	case INTEL_OUTPUT_FORMAT_RGB:1870		sink_dsc_format = DP_DSC_RGB;1871		break;1872	case INTEL_OUTPUT_FORMAT_YCBCR444:1873		sink_dsc_format = DP_DSC_YCbCr444;1874		break;1875	case INTEL_OUTPUT_FORMAT_YCBCR420:1876		if (min(intel_dp_source_dsc_version_minor(i915),1877			intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)1878			return false;1879		sink_dsc_format = DP_DSC_YCbCr420_Native;1880		break;1881	default:1882		return false;1883	}1884 1885	return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);1886}1887 1888static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,1889					    u32 lane_count, u32 mode_clock,1890					    enum intel_output_format output_format,1891					    int timeslots)1892{1893	u32 available_bw, required_bw;1894 1895	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;1896	required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));1897 1898	return available_bw > required_bw;1899}1900 1901static int dsc_compute_link_config(struct intel_dp *intel_dp,1902				   struct intel_crtc_state *pipe_config,1903				   struct link_config_limits *limits,1904				   u16 compressed_bppx16,1905				   int timeslots)1906{1907	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;1908	int link_rate, lane_count;1909	int i;1910 1911	for (i = 0; i < intel_dp->num_common_rates; i++) {1912		link_rate = intel_dp_common_rate(intel_dp, i);1913		if (link_rate < limits->min_rate || link_rate > limits->max_rate)1914			continue;1915 1916		for (lane_count = limits->min_lane_count;1917		     lane_count <= limits->max_lane_count;1918		     lane_count <<= 1) {1919			if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,1920							     lane_count, adjusted_mode->clock,1921							     pipe_config->output_format,1922							     timeslots))1923				continue;1924 1925			pipe_config->lane_count = lane_count;1926			pipe_config->port_clock = link_rate;1927 1928			return 0;1929		}1930	}1931 1932	return -EINVAL;1933}1934 1935static1936u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,1937					    struct intel_crtc_state *pipe_config,1938					    int bpc)1939{1940	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);1941 1942	if (max_bppx16)1943		return max_bppx16;1944	/*1945	 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate1946	 * values as given in spec Table 2-157 DP v2.01947	 */1948	switch (pipe_config->output_format) {1949	case INTEL_OUTPUT_FORMAT_RGB:1950	case INTEL_OUTPUT_FORMAT_YCBCR444:1951		return (3 * bpc) << 4;1952	case INTEL_OUTPUT_FORMAT_YCBCR420:1953		return (3 * (bpc / 2)) << 4;1954	default:1955		MISSING_CASE(pipe_config->output_format);1956		break;1957	}1958 1959	return 0;1960}1961 1962int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)1963{1964	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */1965	switch (pipe_config->output_format) {1966	case INTEL_OUTPUT_FORMAT_RGB:1967	case INTEL_OUTPUT_FORMAT_YCBCR444:1968		return 8;1969	case INTEL_OUTPUT_FORMAT_YCBCR420:1970		return 6;1971	default:1972		MISSING_CASE(pipe_config->output_format);1973		break;1974	}1975 1976	return 0;1977}1978 1979int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,1980					 struct intel_crtc_state *pipe_config,1981					 int bpc)1982{1983	return intel_dp_dsc_max_sink_compressed_bppx16(connector,1984						       pipe_config, bpc) >> 4;1985}1986 1987static int dsc_src_min_compressed_bpp(void)1988{1989	/* Min Compressed bpp supported by source is 8 */1990	return 8;1991}1992 1993static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)1994{1995	struct drm_i915_private *i915 = dp_to_i915(intel_dp);1996 1997	/*1998	 * Max Compressed bpp for Gen 13+ is 27bpp.1999	 * For earlier platform is 23bpp. (Bspec:49259).2000	 */2001	if (DISPLAY_VER(i915) < 13)2002		return 23;2003	else2004		return 27;2005}2006 2007/*2008 * From a list of valid compressed bpps try different compressed bpp and find a2009 * suitable link configuration that can support it.2010 */2011static int2012icl_dsc_compute_link_config(struct intel_dp *intel_dp,2013			    struct intel_crtc_state *pipe_config,2014			    struct link_config_limits *limits,2015			    int dsc_max_bpp,2016			    int dsc_min_bpp,2017			    int pipe_bpp,2018			    int timeslots)2019{2020	int i, ret;2021 2022	/* Compressed BPP should be less than the Input DSC bpp */2023	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);2024 2025	for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {2026		if (valid_dsc_bpp[i] < dsc_min_bpp)2027			continue;2028		if (valid_dsc_bpp[i] > dsc_max_bpp)2029			break;2030 2031		ret = dsc_compute_link_config(intel_dp,2032					      pipe_config,2033					      limits,2034					      valid_dsc_bpp[i] << 4,2035					      timeslots);2036		if (ret == 0) {2037			pipe_config->dsc.compressed_bpp_x16 =2038				fxp_q4_from_int(valid_dsc_bpp[i]);2039			return 0;2040		}2041	}2042 2043	return -EINVAL;2044}2045 2046/*2047 * From XE_LPD onwards we supports compression bpps in steps of 1 up to2048 * uncompressed bpp-1. So we start from max compressed bpp and see if any2049 * link configuration is able to support that compressed bpp, if not we2050 * step down and check for lower compressed bpp.2051 */2052static int2053xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,2054			      const struct intel_connector *connector,2055			      struct intel_crtc_state *pipe_config,2056			      struct link_config_limits *limits,2057			      int dsc_max_bpp,2058			      int dsc_min_bpp,2059			      int pipe_bpp,2060			      int timeslots)2061{2062	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);2063	struct drm_i915_private *i915 = dp_to_i915(intel_dp);2064	u16 compressed_bppx16;2065	u8 bppx16_step;2066	int ret;2067 2068	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)2069		bppx16_step = 16;2070	else2071		bppx16_step = 16 / bppx16_incr;2072 2073	/* Compressed BPP should be less than the Input DSC bpp */2074	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);2075	dsc_min_bpp = dsc_min_bpp << 4;2076 2077	for (compressed_bppx16 = dsc_max_bpp;2078	     compressed_bppx16 >= dsc_min_bpp;2079	     compressed_bppx16 -= bppx16_step) {2080		if (intel_dp->force_dsc_fractional_bpp_en &&2081		    !fxp_q4_to_frac(compressed_bppx16))2082			continue;2083		ret = dsc_compute_link_config(intel_dp,2084					      pipe_config,2085					      limits,2086					      compressed_bppx16,2087					      timeslots);2088		if (ret == 0) {2089			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;2090			if (intel_dp->force_dsc_fractional_bpp_en &&2091			    fxp_q4_to_frac(compressed_bppx16))2092				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");2093 2094			return 0;2095		}2096	}2097	return -EINVAL;2098}2099 2100static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,2101				      const struct intel_connector *connector,2102				      struct intel_crtc_state *pipe_config,2103				      struct link_config_limits *limits,2104				      int pipe_bpp,2105				      int timeslots)2106{2107	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;2108	struct drm_i915_private *i915 = dp_to_i915(intel_dp);2109	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;2110	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;2111	int dsc_joiner_max_bpp;2112 2113	dsc_src_min_bpp = dsc_src_min_compressed_bpp();2114	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);2115	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);2116	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));2117 2118	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);2119	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,2120								pipe_config,2121								pipe_bpp / 3);2122	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;2123 2124	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,2125								adjusted_mode->hdisplay,2126								pipe_config->joiner_pipes);2127	dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);2128	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));2129 2130	if (DISPLAY_VER(i915) >= 13)2131		return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,2132						     dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);2133	return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,2134					   dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);2135}2136 2137static2138u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)2139{2140	/* Min DSC Input BPC for ICL+ is 8 */2141	return HAS_DSC(i915) ? 8 : 0;2142}2143 2144static2145bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,2146				struct drm_connector_state *conn_state,2147				struct link_config_limits *limits,2148				int pipe_bpp)2149{2150	u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;2151 2152	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);2153	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);2154 2155	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);2156	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);2157 2158	return pipe_bpp >= dsc_min_pipe_bpp &&2159	       pipe_bpp <= dsc_max_pipe_bpp;2160}2161 2162static2163int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,2164				struct drm_connector_state *conn_state,2165				struct link_config_limits *limits)2166{2167	struct drm_i915_private *i915 = dp_to_i915(intel_dp);2168	int forced_bpp;2169 2170	if (!intel_dp->force_dsc_bpc)2171		return 0;2172 2173	forced_bpp = intel_dp->force_dsc_bpc * 3;2174 2175	if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {2176		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);2177		return forced_bpp;2178	}2179 2180	drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",2181		    intel_dp->force_dsc_bpc);2182 2183	return 0;2184}2185 2186static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,2187					 struct intel_crtc_state *pipe_config,2188					 struct drm_connector_state *conn_state,2189					 struct link_config_limits *limits,2190					 int timeslots)2191{2192	struct drm_i915_private *i915 = dp_to_i915(intel_dp);2193	const struct intel_connector *connector =2194		to_intel_connector(conn_state->connector);2195	u8 max_req_bpc = conn_state->max_requested_bpc;2196	u8 dsc_max_bpc, dsc_max_bpp;2197	u8 dsc_min_bpc, dsc_min_bpp;2198	u8 dsc_bpc[3] = {};2199	int forced_bpp, pipe_bpp;2200	int num_bpc, i, ret;2201 2202	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);2203 2204	if (forced_bpp) {2205		ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,2206						 limits, forced_bpp, timeslots);2207		if (ret == 0) {2208			pipe_config->pipe_bpp = forced_bpp;2209			return 0;2210		}2211	}2212 2213	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);2214	if (!dsc_max_bpc)2215		return -EINVAL;2216 2217	dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);2218	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);2219 2220	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);2221	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);2222 2223	/*2224	 * Get the maximum DSC bpc that will be supported by any valid2225	 * link configuration and compressed bpp.2226	 */2227	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);2228	for (i = 0; i < num_bpc; i++) {2229		pipe_bpp = dsc_bpc[i] * 3;2230		if (pipe_bpp < dsc_min_bpp)2231			break;2232		if (pipe_bpp > dsc_max_bpp)2233			continue;2234		ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,2235						 limits, pipe_bpp, timeslots);2236		if (ret == 0) {2237			pipe_config->pipe_bpp = pipe_bpp;2238			return 0;2239		}2240	}2241 2242	return -EINVAL;2243}2244 2245static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,2246					  struct intel_crtc_state *pipe_config,2247					  struct drm_connector_state *conn_state,2248					  struct link_config_limits *limits)2249{2250	struct drm_i915_private *i915 = dp_to_i915(intel_dp);2251	struct intel_connector *connector =2252		to_intel_connector(conn_state->connector);2253	int pipe_bpp, forced_bpp;2254	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;2255	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;2256 2257	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);2258 2259	if (forced_bpp) {2260		pipe_bpp = forced_bpp;2261	} else {2262		int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);2263 2264		/* For eDP use max bpp that can be supported with DSC. */2265		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);2266		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {2267			drm_dbg_kms(&i915->drm,2268				    "Computed BPC is not in DSC BPC limits\n");2269			return -EINVAL;2270		}2271	}2272	pipe_config->port_clock = limits->max_rate;2273	pipe_config->lane_count = limits->max_lane_count;2274 2275	dsc_src_min_bpp = dsc_src_min_compressed_bpp();2276	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);2277	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);2278	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));2279 2280	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);2281	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,2282								pipe_config,2283								pipe_bpp / 3);2284	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;2285	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));2286 2287	/* Compressed BPP should be less than the Input DSC bpp */2288	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);2289 2290	pipe_config->dsc.compressed_bpp_x16 =2291		fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));2292 2293	pipe_config->pipe_bpp = pipe_bpp;2294 2295	return 0;2296}2297 2298int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,2299				struct intel_crtc_state *pipe_config,2300				struct drm_connector_state *conn_state,2301				struct link_config_limits *limits,2302				int timeslots,2303				bool compute_pipe_bpp)2304{2305	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);2306	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);2307	const struct intel_connector *connector =2308		to_intel_connector(conn_state->connector);2309	const struct drm_display_mode *adjusted_mode =2310		&pipe_config->hw.adjusted_mode;2311	int ret;2312 2313	pipe_config->fec_enable = pipe_config->fec_enable ||2314		(!intel_dp_is_edp(intel_dp) &&2315		 intel_dp_supports_fec(intel_dp, connector, pipe_config));2316 2317	if (!intel_dp_supports_dsc(connector, pipe_config))2318		return -EINVAL;2319 2320	if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))2321		return -EINVAL;2322 2323	/*2324	 * compute pipe bpp is set to false for DP MST DSC case2325	 * and compressed_bpp is calculated same time once2326	 * vpci timeslots are allocated, because overall bpp2327	 * calculation procedure is bit different for MST case.2328	 */2329	if (compute_pipe_bpp) {2330		if (intel_dp_is_edp(intel_dp))2331			ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,2332							     conn_state, limits);2333		else2334			ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,2335							    conn_state, limits, timeslots);2336		if (ret) {2337			drm_dbg_kms(&dev_priv->drm,2338				    "No Valid pipe bpp for given mode ret = %d\n", ret);2339			return ret;2340		}2341	}2342 2343	/* Calculate Slice count */2344	if (intel_dp_is_edp(intel_dp)) {2345		pipe_config->dsc.slice_count =2346			drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,2347							true);2348		if (!pipe_config->dsc.slice_count) {2349			drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",2350				    pipe_config->dsc.slice_count);2351			return -EINVAL;2352		}2353	} else {2354		u8 dsc_dp_slice_count;2355 2356		dsc_dp_slice_count =2357			intel_dp_dsc_get_slice_count(connector,2358						     adjusted_mode->crtc_clock,2359						     adjusted_mode->crtc_hdisplay,2360						     pipe_config->joiner_pipes);2361		if (!dsc_dp_slice_count) {2362			drm_dbg_kms(&dev_priv->drm,2363				    "Compressed Slice Count not supported\n");2364			return -EINVAL;2365		}2366 2367		pipe_config->dsc.slice_count = dsc_dp_slice_count;2368	}2369	/*2370	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate2371	 * is greater than the maximum Cdclock and if slice count is even2372	 * then we need to use 2 VDSC instances.2373	 */2374	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)2375		pipe_config->dsc.dsc_split = true;2376 2377	ret = intel_dp_dsc_compute_params(connector, pipe_config);2378	if (ret < 0) {2379		drm_dbg_kms(&dev_priv->drm,2380			    "Cannot compute valid DSC parameters for Input Bpp = %d"2381			    "Compressed BPP = " FXP_Q4_FMT "\n",2382			    pipe_config->pipe_bpp,2383			    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));2384		return ret;2385	}2386 2387	pipe_config->dsc.compression_enable = true;2388	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "2389		    "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",2390		    pipe_config->pipe_bpp,2391		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),2392		    pipe_config->dsc.slice_count);2393 2394	return 0;2395}2396 2397/**2398 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits2399 * @intel_dp: intel DP2400 * @crtc_state: crtc state2401 * @dsc: DSC compression mode2402 * @limits: link configuration limits2403 *2404 * Calculates the output link min, max bpp values in @limits based on the2405 * pipe bpp range, @crtc_state and @dsc mode.2406 *2407 * Returns %true in case of success.2408 */2409bool2410intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,2411					const struct intel_crtc_state *crtc_state,2412					bool dsc,2413					struct link_config_limits *limits)2414{2415	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);2416	const struct drm_display_mode *adjusted_mode =2417		&crtc_state->hw.adjusted_mode;2418	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);2419	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;2420	int max_link_bpp_x16;2421 2422	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,2423			       fxp_q4_from_int(limits->pipe.max_bpp));2424 2425	if (!dsc) {2426		max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));2427 2428		if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))2429			return false;2430 2431		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);2432	} else {2433		/*2434		 * TODO: set the DSC link limits already here, atm these are2435		 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /2436		 * intel_dp_dsc_compute_pipe_bpp()2437		 */2438		limits->link.min_bpp_x16 = 0;2439	}2440 2441	limits->link.max_bpp_x16 = max_link_bpp_x16;2442 2443	drm_dbg_kms(&i915->drm,2444		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",2445		    encoder->base.base.id, encoder->base.name,2446		    crtc->base.base.id, crtc->base.name,2447		    adjusted_mode->crtc_clock,2448		    dsc ? "on" : "off",2449		    limits->max_lane_count,2450		    limits->max_rate,2451		    limits->pipe.max_bpp,2452		    FXP_Q4_ARGS(limits->link.max_bpp_x16));2453 2454	return true;2455}2456 2457static bool2458intel_dp_compute_config_limits(struct intel_dp *intel_dp,2459			       struct intel_crtc_state *crtc_state,2460			       bool respect_downstream_limits,2461			       bool dsc,2462			       struct link_config_limits *limits)2463{2464	limits->min_rate = intel_dp_min_link_rate(intel_dp);2465	limits->max_rate = intel_dp_max_link_rate(intel_dp);2466 2467	/* FIXME 128b/132b SST support missing */2468	limits->max_rate = min(limits->max_rate, 810000);2469	limits->min_rate = min(limits->min_rate, limits->max_rate);2470 2471	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);2472	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);2473 2474	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);2475	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,2476						     respect_downstream_limits);2477 2478	if (intel_dp->use_max_params) {2479		/*2480		 * Use the maximum clock and number of lanes the eDP panel2481		 * advertizes being capable of in case the initial fast2482		 * optimal params failed us. The panels are generally2483		 * designed to support only a single clock and lane2484		 * configuration, and typically on older panels these2485		 * values correspond to the native resolution of the panel.2486		 */2487		limits->min_lane_count = limits->max_lane_count;2488		limits->min_rate = limits->max_rate;2489	}2490 2491	intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);2492 2493	return intel_dp_compute_config_link_bpp_limits(intel_dp,2494						       crtc_state,2495						       dsc,2496						       limits);2497}2498 2499int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)2500{2501	const struct drm_display_mode *adjusted_mode =2502		&crtc_state->hw.adjusted_mode;2503	int bpp = crtc_state->dsc.compression_enable ?2504		fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :2505		crtc_state->pipe_bpp;2506 2507	return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);2508}2509 2510bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915, bool use_joiner)2511{2512	/*2513	 * Pipe joiner needs compression up to display 12 due to bandwidth2514	 * limitation. DG2 onwards pipe joiner can be enabled without2515	 * compression.2516	 */2517	return DISPLAY_VER(i915) < 13 && use_joiner;2518}2519 2520static int2521intel_dp_compute_link_config(struct intel_encoder *encoder,2522			     struct intel_crtc_state *pipe_config,2523			     struct drm_connector_state *conn_state,2524			     bool respect_downstream_limits)2525{2526	struct drm_i915_private *i915 = to_i915(encoder->base.dev);2527	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);2528	struct intel_connector *connector =2529		to_intel_connector(conn_state->connector);2530	const struct drm_display_mode *adjusted_mode =2531		&pipe_config->hw.adjusted_mode;2532	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);2533	struct link_config_limits limits;2534	bool dsc_needed, joiner_needs_dsc;2535	int ret = 0;2536 2537	if (pipe_config->fec_enable &&2538	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))2539		return -EINVAL;2540 2541	if (intel_dp_need_joiner(intel_dp, connector,2542				 adjusted_mode->crtc_hdisplay,2543				 adjusted_mode->crtc_clock))2544		pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);2545 2546	joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, pipe_config->joiner_pipes);2547 2548	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||2549		     !intel_dp_compute_config_limits(intel_dp, pipe_config,2550						     respect_downstream_limits,2551						     false,2552						     &limits);2553 2554	if (!dsc_needed) {2555		/*2556		 * Optimize for slow and wide for everything, because there are some2557		 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.2558		 */2559		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,2560							conn_state, &limits);2561		if (ret)2562			dsc_needed = true;2563	}2564 2565	if (dsc_needed) {2566		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",2567			    str_yes_no(ret), str_yes_no(joiner_needs_dsc),2568			    str_yes_no(intel_dp->force_dsc_en));2569 2570		if (!intel_dp_compute_config_limits(intel_dp, pipe_config,2571						    respect_downstream_limits,2572						    true,2573						    &limits))2574			return -EINVAL;2575 2576		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,2577						  conn_state, &limits, 64, true);2578		if (ret < 0)2579			return ret;2580	}2581 2582	drm_dbg_kms(&i915->drm,2583		    "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",2584		    pipe_config->lane_count, pipe_config->port_clock,2585		    pipe_config->pipe_bpp,2586		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),2587		    intel_dp_config_required_rate(pipe_config),2588		    intel_dp_max_link_data_rate(intel_dp,2589						pipe_config->port_clock,2590						pipe_config->lane_count));2591 2592	return 0;2593}2594 2595bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,2596				  const struct drm_connector_state *conn_state)2597{2598	const struct intel_digital_connector_state *intel_conn_state =2599		to_intel_digital_connector_state(conn_state);2600	const struct drm_display_mode *adjusted_mode =2601		&crtc_state->hw.adjusted_mode;2602 2603	/*2604	 * Our YCbCr output is always limited range.2605	 * crtc_state->limited_color_range only applies to RGB,2606	 * and it must never be set for YCbCr or we risk setting2607	 * some conflicting bits in TRANSCONF which will mess up2608	 * the colors on the monitor.2609	 */2610	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)2611		return false;2612 2613	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {2614		/*2615		 * See:2616		 * CEA-861-E - 5.1 Default Encoding Parameters2617		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry2618		 */2619		return crtc_state->pipe_bpp != 18 &&2620			drm_default_rgb_quant_range(adjusted_mode) ==2621			HDMI_QUANTIZATION_RANGE_LIMITED;2622	} else {2623		return intel_conn_state->broadcast_rgb ==2624			INTEL_BROADCAST_RGB_LIMITED;2625	}2626}2627 2628static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,2629				    enum port port)2630{2631	if (IS_G4X(dev_priv))2632		return false;2633	if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)2634		return false;2635 2636	return true;2637}2638 2639static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,2640					     const struct drm_connector_state *conn_state,2641					     struct drm_dp_vsc_sdp *vsc)2642{2643	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);2644	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);2645 2646	if (crtc_state->has_panel_replay) {2647		/*2648		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-2232649		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel2650		 * Encoding/Colorimetry Format indication.2651		 */2652		vsc->revision = 0x7;2653	} else {2654		/*2655		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-1182656		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/2657		 * Colorimetry Format indication.2658		 */2659		vsc->revision = 0x5;2660	}2661 2662	vsc->length = 0x13;2663 2664	/* DP 1.4a spec, Table 2-120 */2665	switch (crtc_state->output_format) {2666	case INTEL_OUTPUT_FORMAT_YCBCR444:2667		vsc->pixelformat = DP_PIXELFORMAT_YUV444;2668		break;2669	case INTEL_OUTPUT_FORMAT_YCBCR420:2670		vsc->pixelformat = DP_PIXELFORMAT_YUV420;2671		break;2672	case INTEL_OUTPUT_FORMAT_RGB:2673	default:2674		vsc->pixelformat = DP_PIXELFORMAT_RGB;2675	}2676 2677	switch (conn_state->colorspace) {2678	case DRM_MODE_COLORIMETRY_BT709_YCC:2679		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;2680		break;2681	case DRM_MODE_COLORIMETRY_XVYCC_601:2682		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;2683		break;2684	case DRM_MODE_COLORIMETRY_XVYCC_709:2685		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;2686		break;2687	case DRM_MODE_COLORIMETRY_SYCC_601:2688		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;2689		break;2690	case DRM_MODE_COLORIMETRY_OPYCC_601:2691		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;2692		break;2693	case DRM_MODE_COLORIMETRY_BT2020_CYCC:2694		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;2695		break;2696	case DRM_MODE_COLORIMETRY_BT2020_RGB:2697		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;2698		break;2699	case DRM_MODE_COLORIMETRY_BT2020_YCC:2700		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;2701		break;2702	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:2703	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:2704		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;2705		break;2706	default:2707		/*2708		 * RGB->YCBCR color conversion uses the BT.7092709		 * color space.2710		 */2711		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)2712			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;2713		else2714			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;2715		break;2716	}2717 2718	vsc->bpc = crtc_state->pipe_bpp / 3;2719 2720	/* only RGB pixelformat supports 6 bpc */2721	drm_WARN_ON(&dev_priv->drm,2722		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);2723 2724	/* all YCbCr are always limited range */2725	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;2726	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;2727}2728 2729static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,2730				    struct intel_crtc_state *crtc_state)2731{2732	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;2733	const struct drm_display_mode *adjusted_mode =2734		&crtc_state->hw.adjusted_mode;2735 2736	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)2737		return;2738 2739	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);2740 2741	/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */2742	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;2743	as_sdp->length = 0x9;2744	as_sdp->duration_incr_ms = 0;2745	as_sdp->duration_incr_ms = 0;2746 2747	if (crtc_state->cmrr.enable) {2748		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;2749		as_sdp->vtotal = adjusted_mode->vtotal;2750		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);2751		as_sdp->target_rr_divider = true;2752	} else {2753		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;2754		as_sdp->vtotal = adjusted_mode->vtotal;2755		as_sdp->target_rr = 0;2756	}2757}2758 2759static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,2760				     struct intel_crtc_state *crtc_state,2761				     const struct drm_connector_state *conn_state)2762{2763	struct drm_dp_vsc_sdp *vsc;2764 2765	if ((!intel_dp->colorimetry_support ||2766	     !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&2767	    !crtc_state->has_psr)2768		return;2769 2770	vsc = &crtc_state->infoframes.vsc;2771 2772	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);2773	vsc->sdp_type = DP_SDP_VSC;2774 2775	/* Needs colorimetry */2776	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {2777		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,2778						 vsc);2779	} else if (crtc_state->has_panel_replay) {2780		/*2781		 * [Panel Replay without colorimetry info]2782		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-2232783		 * VSC SDP supporting 3D stereo + Panel Replay.2784		 */2785		vsc->revision = 0x6;2786		vsc->length = 0x10;2787	} else if (crtc_state->has_sel_update) {2788		/*2789		 * [PSR2 without colorimetry]2790		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-112791		 * 3D stereo + PSR/PSR2 + Y-coordinate.2792		 */2793		vsc->revision = 0x4;2794		vsc->length = 0xe;2795	} else {2796		/*2797		 * [PSR1]2798		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-1182799		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or2800		 * higher).2801		 */2802		vsc->revision = 0x2;2803		vsc->length = 0x8;2804	}2805}2806 2807static void2808intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,2809					    struct intel_crtc_state *crtc_state,2810					    const struct drm_connector_state *conn_state)2811{2812	int ret;2813	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);2814	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;2815 2816	if (!conn_state->hdr_output_metadata)2817		return;2818 2819	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);2820 2821	if (ret) {2822		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");2823		return;2824	}2825 2826	crtc_state->infoframes.enable |=2827		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);2828}2829 2830static bool can_enable_drrs(struct intel_connector *connector,2831			    const struct intel_crtc_state *pipe_config,2832			    const struct drm_display_mode *downclock_mode)2833{2834	struct drm_i915_private *i915 = to_i915(connector->base.dev);2835 2836	if (pipe_config->vrr.enable)2837		return false;2838 2839	/*2840	 * DRRS and PSR can't be enable together, so giving preference to PSR2841	 * as it allows more power-savings by complete shutting down display,2842	 * so to guarantee this, intel_drrs_compute_config() must be called2843	 * after intel_psr_compute_config().2844	 */2845	if (pipe_config->has_psr)2846		return false;2847 2848	/* FIXME missing FDI M2/N2 etc. */2849	if (pipe_config->has_pch_encoder)2850		return false;2851 2852	if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))2853		return false;2854 2855	return downclock_mode &&2856		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;2857}2858 2859static void2860intel_dp_drrs_compute_config(struct intel_connector *connector,2861			     struct intel_crtc_state *pipe_config,2862			     int link_bpp_x16)2863{2864	struct drm_i915_private *i915 = to_i915(connector->base.dev);2865	const struct drm_display_mode *downclock_mode =2866		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);2867	int pixel_clock;2868 2869	/*2870	 * FIXME all joined pipes share the same transcoder.2871	 * Need to account for that when updating M/N live.2872	 */2873	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)2874		pipe_config->update_m_n = true;2875 2876	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {2877		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))2878			intel_zero_m_n(&pipe_config->dp_m2_n2);2879		return;2880	}2881 2882	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))2883		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;2884 2885	pipe_config->has_drrs = true;2886 2887	pixel_clock = downclock_mode->clock;2888	if (pipe_config->splitter.enable)2889		pixel_clock /= pipe_config->splitter.link_count;2890 2891	intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,2892			       pipe_config->port_clock,2893			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),2894			       &pipe_config->dp_m2_n2);2895 2896	/* FIXME: abstract this better */2897	if (pipe_config->splitter.enable)2898		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;2899}2900 2901static bool intel_dp_has_audio(struct intel_encoder *encoder,2902			       const struct drm_connector_state *conn_state)2903{2904	struct drm_i915_private *i915 = to_i915(encoder->base.dev);2905	const struct intel_digital_connector_state *intel_conn_state =2906		to_intel_digital_connector_state(conn_state);2907	struct intel_connector *connector =2908		to_intel_connector(conn_state->connector);2909 2910	if (!intel_dp_port_has_audio(i915, encoder->port))2911		return false;2912 2913	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)2914		return connector->base.display_info.has_audio;2915	else2916		return intel_conn_state->force_audio == HDMI_AUDIO_ON;2917}2918 2919static int2920intel_dp_compute_output_format(struct intel_encoder *encoder,2921			       struct intel_crtc_state *crtc_state,2922			       struct drm_connector_state *conn_state,2923			       bool respect_downstream_limits)2924{2925	struct drm_i915_private *i915 = to_i915(encoder->base.dev);2926	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);2927	struct intel_connector *connector = intel_dp->attached_connector;2928	const struct drm_display_info *info = &connector->base.display_info;2929	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;2930	bool ycbcr_420_only;2931	int ret;2932 2933	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);2934 2935	if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {2936		drm_dbg_kms(&i915->drm,2937			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");2938		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;2939	} else {2940		crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);2941	}2942 2943	crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);2944 2945	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,2946					   respect_downstream_limits);2947	if (ret) {2948		if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||2949		    !connector->base.ycbcr_420_allowed ||2950		    !drm_mode_is_420_also(info, adjusted_mode))2951			return ret;2952 2953		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;2954		crtc_state->output_format = intel_dp_output_format(connector,2955								   crtc_state->sink_format);2956		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,2957						   respect_downstream_limits);2958	}2959 2960	return ret;2961}2962 2963void2964intel_dp_audio_compute_config(struct intel_encoder *encoder,2965			      struct intel_crtc_state *pipe_config,2966			      struct drm_connector_state *conn_state)2967{2968	pipe_config->has_audio =2969		intel_dp_has_audio(encoder, conn_state) &&2970		intel_audio_compute_config(encoder, pipe_config, conn_state);2971 2972	pipe_config->sdp_split_enable = pipe_config->has_audio &&2973					intel_dp_is_uhbr(pipe_config);2974}2975 2976static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)2977{2978	struct drm_i915_private *i915 = to_i915(connector->base.dev);2979 2980	drm_connector_get(&connector->base);2981	if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))2982		drm_connector_put(&connector->base);2983}2984 2985void2986intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,2987				      struct intel_encoder *encoder,2988				      const struct intel_crtc_state *crtc_state)2989{2990	struct intel_connector *connector;2991	struct intel_digital_connector_state *conn_state;2992	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);2993	int i;2994 2995	if (intel_dp->needs_modeset_retry)2996		return;2997 2998	intel_dp->needs_modeset_retry = true;2999 3000	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {3001		intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);3002 3003		return;3004	}3005 3006	for_each_new_intel_connector_in_state(state, connector, conn_state, i) {3007		if (!conn_state->base.crtc)3008			continue;3009 3010		if (connector->mst_port == intel_dp)3011			intel_dp_queue_modeset_retry_work(connector);3012	}3013}3014 3015int3016intel_dp_compute_config(struct intel_encoder *encoder,3017			struct intel_crtc_state *pipe_config,3018			struct drm_connector_state *conn_state)3019{3020	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);3021	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);3022	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;3023	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);3024	const struct drm_display_mode *fixed_mode;3025	struct intel_connector *connector = intel_dp->attached_connector;3026	int ret = 0, link_bpp_x16;3027 3028	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)3029		pipe_config->has_pch_encoder = true;3030 3031	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);3032	if (intel_dp_is_edp(intel_dp) && fixed_mode) {3033		ret = intel_panel_compute_config(connector, adjusted_mode);3034		if (ret)3035			return ret;3036	}3037 3038	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)3039		return -EINVAL;3040 3041	if (!connector->base.interlace_allowed &&3042	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)3043		return -EINVAL;3044 3045	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)3046		return -EINVAL;3047 3048	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))3049		return -EINVAL;3050 3051	/*3052	 * Try to respect downstream TMDS clock limits first, if3053	 * that fails assume the user might know something we don't.3054	 */3055	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);3056	if (ret)3057		ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);3058	if (ret)3059		return ret;3060 3061	if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||3062	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {3063		ret = intel_panel_fitting(pipe_config, conn_state);3064		if (ret)3065			return ret;3066	}3067 3068	pipe_config->limited_color_range =3069		intel_dp_limited_color_range(pipe_config, conn_state);3070 3071	pipe_config->enhanced_framing =3072		drm_dp_enhanced_frame_cap(intel_dp->dpcd);3073 3074	if (pipe_config->dsc.compression_enable)3075		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;3076	else3077		link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,3078								   pipe_config->pipe_bpp));3079 3080	if (intel_dp->mso_link_count) {3081		int n = intel_dp->mso_link_count;3082		int overlap = intel_dp->mso_pixel_overlap;3083 3084		pipe_config->splitter.enable = true;3085		pipe_config->splitter.link_count = n;3086		pipe_config->splitter.pixel_overlap = overlap;3087 3088		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",3089			    n, overlap);3090 3091		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;3092		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;3093		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;3094		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;3095		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;3096		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;3097		adjusted_mode->crtc_clock /= n;3098	}3099 3100	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);3101 3102	intel_link_compute_m_n(link_bpp_x16,3103			       pipe_config->lane_count,3104			       adjusted_mode->crtc_clock,3105			       pipe_config->port_clock,3106			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),3107			       &pipe_config->dp_m_n);3108 3109	/* FIXME: abstract this better */3110	if (pipe_config->splitter.enable)3111		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;3112 3113	if (!HAS_DDI(dev_priv))3114		g4x_dp_set_clock(encoder, pipe_config);3115 3116	intel_vrr_compute_config(pipe_config, conn_state);3117	intel_dp_compute_as_sdp(intel_dp, pipe_config);3118	intel_psr_compute_config(intel_dp, pipe_config, conn_state);3119	intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);3120	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);3121	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);3122	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);3123 3124	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,3125							pipe_config);3126}3127 3128void intel_dp_set_link_params(struct intel_dp *intel_dp,3129			      int link_rate, int lane_count)3130{3131	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));3132	intel_dp->link_trained = false;3133	intel_dp->needs_modeset_retry = false;3134	intel_dp->link_rate = link_rate;3135	intel_dp->lane_count = lane_count;3136}3137 3138void intel_dp_reset_link_params(struct intel_dp *intel_dp)3139{3140	intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);3141	intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);3142	intel_dp->link.mst_probed_lane_count = 0;3143	intel_dp->link.mst_probed_rate = 0;3144	intel_dp->link.retrain_disabled = false;3145	intel_dp->link.seq_train_failures = 0;3146}3147 3148/* Enable backlight PWM and backlight PP control. */3149void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,3150			    const struct drm_connector_state *conn_state)3151{3152	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));3153	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3154 3155	if (!intel_dp_is_edp(intel_dp))3156		return;3157 3158	drm_dbg_kms(&i915->drm, "\n");3159 3160	intel_backlight_enable(crtc_state, conn_state);3161	intel_pps_backlight_on(intel_dp);3162}3163 3164/* Disable backlight PP control and backlight PWM. */3165void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)3166{3167	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));3168	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3169 3170	if (!intel_dp_is_edp(intel_dp))3171		return;3172 3173	drm_dbg_kms(&i915->drm, "\n");3174 3175	intel_pps_backlight_off(intel_dp);3176	intel_backlight_disable(old_conn_state);3177}3178 3179static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)3180{3181	/*3182	 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus3183	 * be capable of signalling downstream hpd with a long pulse.3184	 * Whether or not that means D3 is safe to use is not clear,3185	 * but let's assume so until proven otherwise.3186	 *3187	 * FIXME should really check all downstream ports...3188	 */3189	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&3190		drm_dp_is_branch(intel_dp->dpcd) &&3191		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;3192}3193 3194static int3195write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)3196{3197	int err;3198	u8 val;3199 3200	err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);3201	if (err < 0)3202		return err;3203 3204	if (set)3205		val |= flag;3206	else3207		val &= ~flag;3208 3209	return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);3210}3211 3212static void3213intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,3214				    bool enable)3215{3216	struct drm_i915_private *i915 = to_i915(connector->base.dev);3217 3218	if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,3219					 DP_DECOMPRESSION_EN, enable) < 0)3220		drm_dbg_kms(&i915->drm,3221			    "Failed to %s sink decompression state\n",3222			    str_enable_disable(enable));3223}3224 3225static void3226intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,3227				  bool enable)3228{3229	struct drm_i915_private *i915 = to_i915(connector->base.dev);3230	struct drm_dp_aux *aux = connector->port ?3231				 connector->port->passthrough_aux : NULL;3232 3233	if (!aux)3234		return;3235 3236	if (write_dsc_decompression_flag(aux,3237					 DP_DSC_PASSTHROUGH_EN, enable) < 0)3238		drm_dbg_kms(&i915->drm,3239			    "Failed to %s sink compression passthrough state\n",3240			    str_enable_disable(enable));3241}3242 3243static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,3244				      const struct intel_connector *connector,3245				      bool for_get_ref)3246{3247	struct drm_i915_private *i915 = to_i915(state->base.dev);3248	struct drm_connector *_connector_iter;3249	struct drm_connector_state *old_conn_state;3250	struct drm_connector_state *new_conn_state;3251	int ref_count = 0;3252	int i;3253 3254	/*3255	 * On SST the decompression AUX device won't be shared, each connector3256	 * uses for this its own AUX targeting the sink device.3257	 */3258	if (!connector->mst_port)3259		return connector->dp.dsc_decompression_enabled ? 1 : 0;3260 3261	for_each_oldnew_connector_in_state(&state->base, _connector_iter,3262					   old_conn_state, new_conn_state, i) {3263		const struct intel_connector *3264			connector_iter = to_intel_connector(_connector_iter);3265 3266		if (connector_iter->mst_port != connector->mst_port)3267			continue;3268 3269		if (!connector_iter->dp.dsc_decompression_enabled)3270			continue;3271 3272		drm_WARN_ON(&i915->drm,3273			    (for_get_ref && !new_conn_state->crtc) ||3274			    (!for_get_ref && !old_conn_state->crtc));3275 3276		if (connector_iter->dp.dsc_decompression_aux ==3277		    connector->dp.dsc_decompression_aux)3278			ref_count++;3279	}3280 3281	return ref_count;3282}3283 3284static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,3285				     struct intel_connector *connector)3286{3287	bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;3288 3289	connector->dp.dsc_decompression_enabled = true;3290 3291	return ret;3292}3293 3294static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,3295				     struct intel_connector *connector)3296{3297	connector->dp.dsc_decompression_enabled = false;3298 3299	return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;3300}3301 3302/**3303 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device3304 * @state: atomic state3305 * @connector: connector to enable the decompression for3306 * @new_crtc_state: new state for the CRTC driving @connector3307 *3308 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD3309 * register of the appropriate sink/branch device. On SST this is always the3310 * sink device, whereas on MST based on each device's DSC capabilities it's3311 * either the last branch device (enabling decompression in it) or both the3312 * last branch device (enabling passthrough in it) and the sink device3313 * (enabling decompression in it).3314 */3315void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,3316					struct intel_connector *connector,3317					const struct intel_crtc_state *new_crtc_state)3318{3319	struct drm_i915_private *i915 = to_i915(state->base.dev);3320 3321	if (!new_crtc_state->dsc.compression_enable)3322		return;3323 3324	if (drm_WARN_ON(&i915->drm,3325			!connector->dp.dsc_decompression_aux ||3326			connector->dp.dsc_decompression_enabled))3327		return;3328 3329	if (!intel_dp_dsc_aux_get_ref(state, connector))3330		return;3331 3332	intel_dp_sink_set_dsc_passthrough(connector, true);3333	intel_dp_sink_set_dsc_decompression(connector, true);3334}3335 3336/**3337 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device3338 * @state: atomic state3339 * @connector: connector to disable the decompression for3340 * @old_crtc_state: old state for the CRTC driving @connector3341 *3342 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD3343 * register of the appropriate sink/branch device, corresponding to the3344 * sequence in intel_dp_sink_enable_decompression().3345 */3346void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,3347					 struct intel_connector *connector,3348					 const struct intel_crtc_state *old_crtc_state)3349{3350	struct drm_i915_private *i915 = to_i915(state->base.dev);3351 3352	if (!old_crtc_state->dsc.compression_enable)3353		return;3354 3355	if (drm_WARN_ON(&i915->drm,3356			!connector->dp.dsc_decompression_aux ||3357			!connector->dp.dsc_decompression_enabled))3358		return;3359 3360	if (!intel_dp_dsc_aux_put_ref(state, connector))3361		return;3362 3363	intel_dp_sink_set_dsc_decompression(connector, false);3364	intel_dp_sink_set_dsc_passthrough(connector, false);3365}3366 3367static void3368intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)3369{3370	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3371	u8 oui[] = { 0x00, 0xaa, 0x01 };3372	u8 buf[3] = {};3373 3374	/*3375	 * During driver init, we want to be careful and avoid changing the source OUI if it's3376	 * already set to what we want, so as to avoid clearing any state by accident3377	 */3378	if (careful) {3379		if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)3380			drm_err(&i915->drm, "Failed to read source OUI\n");3381 3382		if (memcmp(oui, buf, sizeof(oui)) == 0)3383			return;3384	}3385 3386	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)3387		drm_err(&i915->drm, "Failed to write source OUI\n");3388 3389	intel_dp->last_oui_write = jiffies;3390}3391 3392void intel_dp_wait_source_oui(struct intel_dp *intel_dp)3393{3394	struct intel_connector *connector = intel_dp->attached_connector;3395	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3396 3397	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",3398		    connector->base.base.id, connector->base.name,3399		    connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);3400 3401	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,3402				       connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);3403}3404 3405/* If the device supports it, try to set the power state appropriately */3406void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)3407{3408	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;3409	struct drm_i915_private *i915 = to_i915(encoder->base.dev);3410	int ret, i;3411 3412	/* Should have a valid DPCD by this point */3413	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)3414		return;3415 3416	if (mode != DP_SET_POWER_D0) {3417		if (downstream_hpd_needs_d0(intel_dp))3418			return;3419 3420		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);3421	} else {3422		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);3423 3424		lspcon_resume(dp_to_dig_port(intel_dp));3425 3426		/* Write the source OUI as early as possible */3427		if (intel_dp_is_edp(intel_dp))3428			intel_edp_init_source_oui(intel_dp, false);3429 3430		/*3431		 * When turning on, we need to retry for 1ms to give the sink3432		 * time to wake up.3433		 */3434		for (i = 0; i < 3; i++) {3435			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);3436			if (ret == 1)3437				break;3438			msleep(1);3439		}3440 3441		if (ret == 1 && lspcon->active)3442			lspcon_wait_pcon_mode(lspcon);3443	}3444 3445	if (ret != 1)3446		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",3447			    encoder->base.base.id, encoder->base.name,3448			    mode == DP_SET_POWER_D0 ? "D0" : "D3");3449}3450 3451static bool3452intel_dp_get_dpcd(struct intel_dp *intel_dp);3453 3454/**3455 * intel_dp_sync_state - sync the encoder state during init/resume3456 * @encoder: intel encoder to sync3457 * @crtc_state: state for the CRTC connected to the encoder3458 *3459 * Sync any state stored in the encoder wrt. HW state during driver init3460 * and system resume.3461 */3462void intel_dp_sync_state(struct intel_encoder *encoder,3463			 const struct intel_crtc_state *crtc_state)3464{3465	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);3466	bool dpcd_updated = false;3467 3468	/*3469	 * Don't clobber DPCD if it's been already read out during output3470	 * setup (eDP) or detect.3471	 */3472	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {3473		intel_dp_get_dpcd(intel_dp);3474		dpcd_updated = true;3475	}3476 3477	intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);3478 3479	if (crtc_state) {3480		intel_dp_reset_link_params(intel_dp);3481		intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);3482		intel_dp->link_trained = true;3483	}3484}3485 3486bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,3487				    struct intel_crtc_state *crtc_state)3488{3489	struct drm_i915_private *i915 = to_i915(encoder->base.dev);3490	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);3491	bool fastset = true;3492 3493	/*3494	 * If BIOS has set an unsupported or non-standard link rate for some3495	 * reason force an encoder recompute and full modeset.3496	 */3497	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,3498				crtc_state->port_clock) < 0) {3499		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",3500			    encoder->base.base.id, encoder->base.name);3501		crtc_state->uapi.connectors_changed = true;3502		fastset = false;3503	}3504 3505	/*3506	 * FIXME hack to force full modeset when DSC is being used.3507	 *3508	 * As long as we do not have full state readout and config comparison3509	 * of crtc_state->dsc, we have no way to ensure reliable fastset.3510	 * Remove once we have readout for DSC.3511	 */3512	if (crtc_state->dsc.compression_enable) {3513		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",3514			    encoder->base.base.id, encoder->base.name);3515		crtc_state->uapi.mode_changed = true;3516		fastset = false;3517	}3518 3519	if (CAN_PANEL_REPLAY(intel_dp)) {3520		drm_dbg_kms(&i915->drm,3521			    "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",3522			    encoder->base.base.id, encoder->base.name);3523		crtc_state->uapi.mode_changed = true;3524		fastset = false;3525	}3526 3527	return fastset;3528}3529 3530static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)3531{3532	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3533 3534	/* Clear the cached register set to avoid using stale values */3535 3536	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));3537 3538	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,3539			     intel_dp->pcon_dsc_dpcd,3540			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)3541		drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",3542			DP_PCON_DSC_ENCODER);3543 3544	drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",3545		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);3546}3547 3548static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)3549{3550	static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};3551	int i;3552 3553	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {3554		if (frl_bw_mask & (1 << i))3555			return bw_gbps[i];3556	}3557	return 0;3558}3559 3560static int intel_dp_pcon_set_frl_mask(int max_frl)3561{3562	switch (max_frl) {3563	case 48:3564		return DP_PCON_FRL_BW_MASK_48GBPS;3565	case 40:3566		return DP_PCON_FRL_BW_MASK_40GBPS;3567	case 32:3568		return DP_PCON_FRL_BW_MASK_32GBPS;3569	case 24:3570		return DP_PCON_FRL_BW_MASK_24GBPS;3571	case 18:3572		return DP_PCON_FRL_BW_MASK_18GBPS;3573	case 9:3574		return DP_PCON_FRL_BW_MASK_9GBPS;3575	}3576 3577	return 0;3578}3579 3580static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)3581{3582	struct intel_connector *intel_connector = intel_dp->attached_connector;3583	struct drm_connector *connector = &intel_connector->base;3584	int max_frl_rate;3585	int max_lanes, rate_per_lane;3586	int max_dsc_lanes, dsc_rate_per_lane;3587 3588	max_lanes = connector->display_info.hdmi.max_lanes;3589	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;3590	max_frl_rate = max_lanes * rate_per_lane;3591 3592	if (connector->display_info.hdmi.dsc_cap.v_1p2) {3593		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;3594		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;3595		if (max_dsc_lanes && dsc_rate_per_lane)3596			max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);3597	}3598 3599	return max_frl_rate;3600}3601 3602static bool3603intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,3604			     u8 max_frl_bw_mask, u8 *frl_trained_mask)3605{3606	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&3607	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&3608	    *frl_trained_mask >= max_frl_bw_mask)3609		return true;3610 3611	return false;3612}3613 3614static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)3615{3616#define TIMEOUT_FRL_READY_MS 5003617#define TIMEOUT_HDMI_LINK_ACTIVE_MS 10003618 3619	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3620	int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;3621	u8 max_frl_bw_mask = 0, frl_trained_mask;3622	bool is_active;3623 3624	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;3625	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);3626 3627	max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);3628	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);3629 3630	max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);3631 3632	if (max_frl_bw <= 0)3633		return -EINVAL;3634 3635	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);3636	drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);3637 3638	if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))3639		goto frl_trained;3640 3641	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);3642	if (ret < 0)3643		return ret;3644	/* Wait for PCON to be FRL Ready */3645	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);3646 3647	if (!is_active)3648		return -ETIMEDOUT;3649 3650	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,3651					  DP_PCON_ENABLE_SEQUENTIAL_LINK);3652	if (ret < 0)3653		return ret;3654	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,3655					  DP_PCON_FRL_LINK_TRAIN_NORMAL);3656	if (ret < 0)3657		return ret;3658	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);3659	if (ret < 0)3660		return ret;3661	/*3662	 * Wait for FRL to be completed3663	 * Check if the HDMI Link is up and active.3664	 */3665	wait_for(is_active =3666		 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),3667		 TIMEOUT_HDMI_LINK_ACTIVE_MS);3668 3669	if (!is_active)3670		return -ETIMEDOUT;3671 3672frl_trained:3673	drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);3674	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);3675	intel_dp->frl.is_trained = true;3676	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);3677 3678	return 0;3679}3680 3681static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)3682{3683	if (drm_dp_is_branch(intel_dp->dpcd) &&3684	    intel_dp_has_hdmi_sink(intel_dp) &&3685	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)3686		return true;3687 3688	return false;3689}3690 3691static3692int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)3693{3694	int ret;3695	u8 buf = 0;3696 3697	/* Set PCON source control mode */3698	buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;3699 3700	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);3701	if (ret < 0)3702		return ret;3703 3704	/* Set HDMI LINK ENABLE */3705	buf |= DP_PCON_ENABLE_HDMI_LINK;3706	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);3707	if (ret < 0)3708		return ret;3709 3710	return 0;3711}3712 3713void intel_dp_check_frl_training(struct intel_dp *intel_dp)3714{3715	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);3716 3717	/*3718	 * Always go for FRL training if:3719	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)3720	 * -sink is HDMI2.13721	 */3722	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||3723	    !intel_dp_is_hdmi_2_1_sink(intel_dp) ||3724	    intel_dp->frl.is_trained)3725		return;3726 3727	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {3728		int ret, mode;3729 3730		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");3731		ret = intel_dp_pcon_set_tmds_mode(intel_dp);3732		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);3733 3734		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)3735			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");3736	} else {3737		drm_dbg(&dev_priv->drm, "FRL training Completed\n");3738	}3739}3740 3741static int3742intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)3743{3744	int vactive = crtc_state->hw.adjusted_mode.vdisplay;3745 3746	return intel_hdmi_dsc_get_slice_height(vactive);3747}3748 3749static int3750intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,3751			     const struct intel_crtc_state *crtc_state)3752{3753	struct intel_connector *intel_connector = intel_dp->attached_connector;3754	struct drm_connector *connector = &intel_connector->base;3755	int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;3756	int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;3757	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);3758	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);3759 3760	return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,3761					     pcon_max_slice_width,3762					     hdmi_max_slices, hdmi_throughput);3763}3764 3765static int3766intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,3767			  const struct intel_crtc_state *crtc_state,3768			  int num_slices, int slice_width)3769{3770	struct intel_connector *intel_connector = intel_dp->attached_connector;3771	struct drm_connector *connector = &intel_connector->base;3772	int output_format = crtc_state->output_format;3773	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;3774	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);3775	int hdmi_max_chunk_bytes =3776		connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;3777 3778	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,3779				      num_slices, output_format, hdmi_all_bpp,3780				      hdmi_max_chunk_bytes);3781}3782 3783void3784intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,3785			    const struct intel_crtc_state *crtc_state)3786{3787	u8 pps_param[6];3788	int slice_height;3789	int slice_width;3790	int num_slices;3791	int bits_per_pixel;3792	int ret;3793	struct intel_connector *intel_connector = intel_dp->attached_connector;3794	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3795	struct drm_connector *connector;3796	bool hdmi_is_dsc_1_2;3797 3798	if (!intel_dp_is_hdmi_2_1_sink(intel_dp))3799		return;3800 3801	if (!intel_connector)3802		return;3803	connector = &intel_connector->base;3804	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;3805 3806	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||3807	    !hdmi_is_dsc_1_2)3808		return;3809 3810	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);3811	if (!slice_height)3812		return;3813 3814	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);3815	if (!num_slices)3816		return;3817 3818	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,3819				   num_slices);3820 3821	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,3822						   num_slices, slice_width);3823	if (!bits_per_pixel)3824		return;3825 3826	pps_param[0] = slice_height & 0xFF;3827	pps_param[1] = slice_height >> 8;3828	pps_param[2] = slice_width & 0xFF;3829	pps_param[3] = slice_width >> 8;3830	pps_param[4] = bits_per_pixel & 0xFF;3831	pps_param[5] = (bits_per_pixel >> 8) & 0x3;3832 3833	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);3834	if (ret < 0)3835		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");3836}3837 3838void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,3839					   const struct intel_crtc_state *crtc_state)3840{3841	struct drm_i915_private *i915 = dp_to_i915(intel_dp);3842	bool ycbcr444_to_420 = false;3843	bool rgb_to_ycbcr = false;3844	u8 tmp;3845 3846	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)3847		return;3848 3849	if (!drm_dp_is_branch(intel_dp->dpcd))3850		return;3851 3852	tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;3853 3854	if (drm_dp_dpcd_writeb(&intel_dp->aux,3855			       DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)3856		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",3857			    str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));3858 3859	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {3860		switch (crtc_state->output_format) {3861		case INTEL_OUTPUT_FORMAT_YCBCR420:3862			break;3863		case INTEL_OUTPUT_FORMAT_YCBCR444:3864			ycbcr444_to_420 = true;3865			break;3866		case INTEL_OUTPUT_FORMAT_RGB:3867			rgb_to_ycbcr = true;3868			ycbcr444_to_420 = true;3869			break;3870		default:3871			MISSING_CASE(crtc_state->output_format);3872			break;3873		}3874	} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {3875		switch (crtc_state->output_format) {3876		case INTEL_OUTPUT_FORMAT_YCBCR444:3877			break;3878		case INTEL_OUTPUT_FORMAT_RGB:3879			rgb_to_ycbcr = true;3880			break;3881		default:3882			MISSING_CASE(crtc_state->output_format);3883			break;3884		}3885	}3886 3887	tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;3888 3889	if (drm_dp_dpcd_writeb(&intel_dp->aux,3890			       DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)3891		drm_dbg_kms(&i915->drm,3892			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",3893			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));3894 3895	tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;3896 3897	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)3898		drm_dbg_kms(&i915->drm,3899			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",3900			    str_enable_disable(tmp));3901}3902 3903bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)3904{3905	u8 dprx = 0;3906 3907	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,3908			      &dprx) != 1)3909		return false;3910	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;3911}3912 3913static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,3914				   u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])3915{3916	if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,3917			     DP_DSC_RECEIVER_CAP_SIZE) < 0) {3918		drm_err(aux->drm_dev,3919			"Failed to read DPCD register 0x%x\n",3920			DP_DSC_SUPPORT);3921		return;3922	}3923 3924	drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",3925		    DP_DSC_RECEIVER_CAP_SIZE,3926		    dsc_dpcd);3927}3928 3929void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)3930{3931	struct drm_i915_private *i915 = to_i915(connector->base.dev);3932 3933	/*3934	 * Clear the cached register set to avoid using stale values3935	 * for the sinks that do not support DSC.3936	 */3937	memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));3938 3939	/* Clear fec_capable to avoid using stale values */3940	connector->dp.fec_capability = 0;3941 3942	if (dpcd_rev < DP_DPCD_REV_14)3943		return;3944 3945	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,3946			       connector->dp.dsc_dpcd);3947 3948	if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,3949			      &connector->dp.fec_capability) < 0) {3950		drm_err(&i915->drm, "Failed to read FEC DPCD register\n");3951		return;3952	}3953 3954	drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",3955		    connector->dp.fec_capability);3956}3957 3958static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)3959{3960	if (edp_dpcd_rev < DP_EDP_14)3961		return;3962 3963	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);3964}3965 3966static void intel_edp_mso_mode_fixup(struct intel_connector *connector,3967				     struct drm_display_mode *mode)3968{3969	struct intel_dp *intel_dp = intel_attached_dp(connector);3970	struct drm_i915_private *i915 = to_i915(connector->base.dev);3971	int n = intel_dp->mso_link_count;3972	int overlap = intel_dp->mso_pixel_overlap;3973 3974	if (!mode || !n)3975		return;3976 3977	mode->hdisplay = (mode->hdisplay - overlap) * n;3978	mode->hsync_start = (mode->hsync_start - overlap) * n;3979	mode->hsync_end = (mode->hsync_end - overlap) * n;3980	mode->htotal = (mode->htotal - overlap) * n;3981	mode->clock *= n;3982 3983	drm_mode_set_name(mode);3984 3985	drm_dbg_kms(&i915->drm,3986		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",3987		    connector->base.base.id, connector->base.name,3988		    DRM_MODE_ARG(mode));3989}3990 3991void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)3992{3993	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);3994	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);3995	struct intel_connector *connector = intel_dp->attached_connector;3996 3997	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {3998		/*3999		 * This is a big fat ugly hack.4000		 *4001		 * Some machines in UEFI boot mode provide us a VBT that has 184002		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons4003		 * unknown we fail to light up. Yet the same BIOS boots up with4004		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as4005		 * max, not what it tells us to use.4006		 *4007		 * Note: This will still be broken if the eDP panel is not lit4008		 * up by the BIOS, and thus we can't get the mode at module4009		 * load.4010		 */4011		drm_dbg_kms(&dev_priv->drm,4012			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",4013			    pipe_bpp, connector->panel.vbt.edp.bpp);4014		connector->panel.vbt.edp.bpp = pipe_bpp;4015	}4016}4017 4018static void intel_edp_mso_init(struct intel_dp *intel_dp)4019{4020	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4021	struct intel_connector *connector = intel_dp->attached_connector;4022	struct drm_display_info *info = &connector->base.display_info;4023	u8 mso;4024 4025	if (intel_dp->edp_dpcd[0] < DP_EDP_14)4026		return;4027 4028	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {4029		drm_err(&i915->drm, "Failed to read MSO cap\n");4030		return;4031	}4032 4033	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */4034	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;4035	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {4036		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);4037		mso = 0;4038	}4039 4040	if (mso) {4041		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",4042			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,4043			    info->mso_pixel_overlap);4044		if (!HAS_MSO(i915)) {4045			drm_err(&i915->drm, "No source MSO support, disabling\n");4046			mso = 0;4047		}4048	}4049 4050	intel_dp->mso_link_count = mso;4051	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;4052}4053 4054static bool4055intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)4056{4057	struct drm_i915_private *dev_priv =4058		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);4059 4060	/* this function is meant to be called only once */4061	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);4062 4063	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)4064		return false;4065 4066	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,4067			 drm_dp_is_branch(intel_dp->dpcd));4068	intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);4069 4070	intel_dp->colorimetry_support =4071		intel_dp_get_colorimetry_status(intel_dp);4072 4073	/*4074	 * Read the eDP display control registers.4075	 *4076	 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in4077	 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it4078	 * set, but require eDP 1.4+ detection (e.g. for supported link rates4079	 * method). The display control registers should read zero if they're4080	 * not supported anyway.4081	 */4082	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,4083			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==4084			     sizeof(intel_dp->edp_dpcd)) {4085		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",4086			    (int)sizeof(intel_dp->edp_dpcd),4087			    intel_dp->edp_dpcd);4088 4089		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;4090	}4091 4092	/*4093	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks4094	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]4095	 */4096	intel_psr_init_dpcd(intel_dp);4097 4098	/* Clear the default sink rates */4099	intel_dp->num_sink_rates = 0;4100 4101	/* Read the eDP 1.4+ supported link rates. */4102	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {4103		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];4104		int i;4105 4106		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,4107				sink_rates, sizeof(sink_rates));4108 4109		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {4110			int val = le16_to_cpu(sink_rates[i]);4111 4112			if (val == 0)4113				break;4114 4115			/* Value read multiplied by 200kHz gives the per-lane4116			 * link rate in kHz. The source rates are, however,4117			 * stored in terms of LS_Clk kHz. The full conversion4118			 * back to symbols is4119			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)4120			 */4121			intel_dp->sink_rates[i] = (val * 200) / 10;4122		}4123		intel_dp->num_sink_rates = i;4124	}4125 4126	/*4127	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,4128	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.4129	 */4130	if (intel_dp->num_sink_rates)4131		intel_dp->use_rate_select = true;4132	else4133		intel_dp_set_sink_rates(intel_dp);4134	intel_dp_set_max_sink_lane_count(intel_dp);4135 4136	/* Read the eDP DSC DPCD registers */4137	if (HAS_DSC(dev_priv))4138		intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],4139					   connector);4140 4141	/*4142	 * If needed, program our source OUI so we can make various Intel-specific AUX services4143	 * available (such as HDR backlight controls)4144	 */4145	intel_edp_init_source_oui(intel_dp, true);4146 4147	return true;4148}4149 4150static bool4151intel_dp_has_sink_count(struct intel_dp *intel_dp)4152{4153	if (!intel_dp->attached_connector)4154		return false;4155 4156	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,4157					  intel_dp->dpcd,4158					  &intel_dp->desc);4159}4160 4161void intel_dp_update_sink_caps(struct intel_dp *intel_dp)4162{4163	intel_dp_set_sink_rates(intel_dp);4164	intel_dp_set_max_sink_lane_count(intel_dp);4165	intel_dp_set_common_rates(intel_dp);4166}4167 4168static bool4169intel_dp_get_dpcd(struct intel_dp *intel_dp)4170{4171	int ret;4172 4173	if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)4174		return false;4175 4176	/*4177	 * Don't clobber cached eDP rates. Also skip re-reading4178	 * the OUI/ID since we know it won't change.4179	 */4180	if (!intel_dp_is_edp(intel_dp)) {4181		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,4182				 drm_dp_is_branch(intel_dp->dpcd));4183 4184		intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);4185 4186		intel_dp->colorimetry_support =4187			intel_dp_get_colorimetry_status(intel_dp);4188 4189		intel_dp_update_sink_caps(intel_dp);4190	}4191 4192	if (intel_dp_has_sink_count(intel_dp)) {4193		ret = drm_dp_read_sink_count(&intel_dp->aux);4194		if (ret < 0)4195			return false;4196 4197		/*4198		 * Sink count can change between short pulse hpd hence4199		 * a member variable in intel_dp will track any changes4200		 * between short pulse interrupts.4201		 */4202		intel_dp->sink_count = ret;4203 4204		/*4205		 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that4206		 * a dongle is present but no display. Unless we require to know4207		 * if a dongle is present or not, we don't need to update4208		 * downstream port information. So, an early return here saves4209		 * time from performing other operations which are not required.4210		 */4211		if (!intel_dp->sink_count)4212			return false;4213	}4214 4215	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,4216					   intel_dp->downstream_ports) == 0;4217}4218 4219static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)4220{4221	if (mst_mode == DRM_DP_MST)4222		return "MST";4223	else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)4224		return "SST w/ sideband messaging";4225	else4226		return "SST";4227}4228 4229static enum drm_dp_mst_mode4230intel_dp_mst_mode_choose(struct intel_dp *intel_dp,4231			 enum drm_dp_mst_mode sink_mst_mode)4232{4233	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4234 4235	if (!i915->display.params.enable_dp_mst)4236		return DRM_DP_SST;4237 4238	if (!intel_dp_mst_source_support(intel_dp))4239		return DRM_DP_SST;4240 4241	if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&4242	    !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))4243		return DRM_DP_SST;4244 4245	return sink_mst_mode;4246}4247 4248static enum drm_dp_mst_mode4249intel_dp_mst_detect(struct intel_dp *intel_dp)4250{4251	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4252	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;4253	enum drm_dp_mst_mode sink_mst_mode;4254	enum drm_dp_mst_mode mst_detect;4255 4256	sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);4257 4258	mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);4259 4260	drm_dbg_kms(&i915->drm,4261		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",4262		    encoder->base.base.id, encoder->base.name,4263		    str_yes_no(intel_dp_mst_source_support(intel_dp)),4264		    intel_dp_mst_mode_str(sink_mst_mode),4265		    str_yes_no(i915->display.params.enable_dp_mst),4266		    intel_dp_mst_mode_str(mst_detect));4267 4268	return mst_detect;4269}4270 4271static void4272intel_dp_mst_configure(struct intel_dp *intel_dp)4273{4274	if (!intel_dp_mst_source_support(intel_dp))4275		return;4276 4277	intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;4278 4279	if (intel_dp->is_mst)4280		intel_dp_mst_prepare_probe(intel_dp);4281 4282	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);4283 4284	/* Avoid stale info on the next detect cycle. */4285	intel_dp->mst_detect = DRM_DP_SST;4286}4287 4288static void4289intel_dp_mst_disconnect(struct intel_dp *intel_dp)4290{4291	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4292 4293	if (!intel_dp->is_mst)4294		return;4295 4296	drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",4297		    intel_dp->is_mst, intel_dp->mst_mgr.mst_state);4298	intel_dp->is_mst = false;4299	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);4300}4301 4302static bool4303intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)4304{4305	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;4306}4307 4308static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])4309{4310	int retry;4311 4312	for (retry = 0; retry < 3; retry++) {4313		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,4314				      &esi[1], 3) == 3)4315			return true;4316	}4317 4318	return false;4319}4320 4321bool4322intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,4323		       const struct drm_connector_state *conn_state)4324{4325	/*4326	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication4327	 * of Color Encoding Format and Content Color Gamut], in order to4328	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.4329	 */4330	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)4331		return true;4332 4333	switch (conn_state->colorspace) {4334	case DRM_MODE_COLORIMETRY_SYCC_601:4335	case DRM_MODE_COLORIMETRY_OPYCC_601:4336	case DRM_MODE_COLORIMETRY_BT2020_YCC:4337	case DRM_MODE_COLORIMETRY_BT2020_RGB:4338	case DRM_MODE_COLORIMETRY_BT2020_CYCC:4339		return true;4340	default:4341		break;4342	}4343 4344	return false;4345}4346 4347static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,4348				    struct dp_sdp *sdp, size_t size)4349{4350	size_t length = sizeof(struct dp_sdp);4351 4352	if (size < length)4353		return -ENOSPC;4354 4355	memset(sdp, 0, size);4356 4357	/* Prepare AS (Adaptive Sync) SDP Header */4358	sdp->sdp_header.HB0 = 0;4359	sdp->sdp_header.HB1 = as_sdp->sdp_type;4360	sdp->sdp_header.HB2 = 0x02;4361	sdp->sdp_header.HB3 = as_sdp->length;4362 4363	/* Fill AS (Adaptive Sync) SDP Payload */4364	sdp->db[0] = as_sdp->mode;4365	sdp->db[1] = as_sdp->vtotal & 0xFF;4366	sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;4367	sdp->db[3] = as_sdp->target_rr & 0xFF;4368	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;4369 4370	if (as_sdp->target_rr_divider)4371		sdp->db[4] |= 0x20;4372 4373	return length;4374}4375 4376static ssize_t4377intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,4378					 const struct hdmi_drm_infoframe *drm_infoframe,4379					 struct dp_sdp *sdp,4380					 size_t size)4381{4382	size_t length = sizeof(struct dp_sdp);4383	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;4384	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];4385	ssize_t len;4386 4387	if (size < length)4388		return -ENOSPC;4389 4390	memset(sdp, 0, size);4391 4392	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));4393	if (len < 0) {4394		drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");4395		return -ENOSPC;4396	}4397 4398	if (len != infoframe_size) {4399		drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");4400		return -ENOSPC;4401	}4402 4403	/*4404	 * Set up the infoframe sdp packet for HDR static metadata.4405	 * Prepare VSC Header for SU as per DP 1.4a spec,4406	 * Table 2-100 and Table 2-1014407	 */4408 4409	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */4410	sdp->sdp_header.HB0 = 0;4411	/*4412	 * Packet Type 80h + Non-audio INFOFRAME Type value4413	 * HDMI_INFOFRAME_TYPE_DRM: 0x874414	 * - 80h + Non-audio INFOFRAME Type value4415	 * - InfoFrame Type: 0x074416	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]4417	 */4418	sdp->sdp_header.HB1 = drm_infoframe->type;4419	/*4420	 * Least Significant Eight Bits of (Data Byte Count – 1)4421	 * infoframe_size - 14422	 */4423	sdp->sdp_header.HB2 = 0x1D;4424	/* INFOFRAME SDP Version Number */4425	sdp->sdp_header.HB3 = (0x13 << 2);4426	/* CTA Header Byte 2 (INFOFRAME Version Number) */4427	sdp->db[0] = drm_infoframe->version;4428	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */4429	sdp->db[1] = drm_infoframe->length;4430	/*4431	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after4432	 * HDMI_INFOFRAME_HEADER_SIZE4433	 */4434	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);4435	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],4436	       HDMI_DRM_INFOFRAME_SIZE);4437 4438	/*4439	 * Size of DP infoframe sdp packet for HDR static metadata consists of4440	 * - DP SDP Header(struct dp_sdp_header): 4 bytes4441	 * - Two Data Blocks: 2 bytes4442	 *    CTA Header Byte2 (INFOFRAME Version Number)4443	 *    CTA Header Byte3 (Length of INFOFRAME)4444	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes4445	 *4446	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata4447	 * infoframe size. But GEN11+ has larger than that size, write_infoframe4448	 * will pad rest of the size.4449	 */4450	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;4451}4452 4453static void intel_write_dp_sdp(struct intel_encoder *encoder,4454			       const struct intel_crtc_state *crtc_state,4455			       unsigned int type)4456{4457	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);4458	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);4459	struct dp_sdp sdp = {};4460	ssize_t len;4461 4462	if ((crtc_state->infoframes.enable &4463	     intel_hdmi_infoframe_enable(type)) == 0)4464		return;4465 4466	switch (type) {4467	case DP_SDP_VSC:4468		len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);4469		break;4470	case HDMI_PACKET_TYPE_GAMUT_METADATA:4471		len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,4472							       &crtc_state->infoframes.drm.drm,4473							       &sdp, sizeof(sdp));4474		break;4475	case DP_SDP_ADAPTIVE_SYNC:4476		len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,4477					   sizeof(sdp));4478		break;4479	default:4480		MISSING_CASE(type);4481		return;4482	}4483 4484	if (drm_WARN_ON(&dev_priv->drm, len < 0))4485		return;4486 4487	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);4488}4489 4490void intel_dp_set_infoframes(struct intel_encoder *encoder,4491			     bool enable,4492			     const struct intel_crtc_state *crtc_state,4493			     const struct drm_connector_state *conn_state)4494{4495	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);4496	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv,4497					    crtc_state->cpu_transcoder);4498	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |4499			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |4500			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;4501 4502	if (HAS_AS_SDP(dev_priv))4503		dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;4504 4505	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;4506 4507	/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */4508	if (!enable && HAS_DSC(dev_priv))4509		val &= ~VDIP_ENABLE_PPS;4510 4511	/*4512	 * This routine disables VSC DIP if the function is called4513	 * to disable SDP or if it does not have PSR4514	 */4515	if (!enable || !crtc_state->has_psr)4516		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;4517 4518	intel_de_write(dev_priv, reg, val);4519	intel_de_posting_read(dev_priv, reg);4520 4521	if (!enable)4522		return;4523 4524	intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);4525	intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);4526 4527	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);4528}4529 4530static4531int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,4532			   const void *buffer, size_t size)4533{4534	const struct dp_sdp *sdp = buffer;4535 4536	if (size < sizeof(struct dp_sdp))4537		return -EINVAL;4538 4539	memset(as_sdp, 0, sizeof(*as_sdp));4540 4541	if (sdp->sdp_header.HB0 != 0)4542		return -EINVAL;4543 4544	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)4545		return -EINVAL;4546 4547	if (sdp->sdp_header.HB2 != 0x02)4548		return -EINVAL;4549 4550	if ((sdp->sdp_header.HB3 & 0x3F) != 9)4551		return -EINVAL;4552 4553	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;4554	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;4555	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];4556	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);4557	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;4558 4559	return 0;4560}4561 4562static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,4563				   const void *buffer, size_t size)4564{4565	const struct dp_sdp *sdp = buffer;4566 4567	if (size < sizeof(struct dp_sdp))4568		return -EINVAL;4569 4570	memset(vsc, 0, sizeof(*vsc));4571 4572	if (sdp->sdp_header.HB0 != 0)4573		return -EINVAL;4574 4575	if (sdp->sdp_header.HB1 != DP_SDP_VSC)4576		return -EINVAL;4577 4578	vsc->sdp_type = sdp->sdp_header.HB1;4579	vsc->revision = sdp->sdp_header.HB2;4580	vsc->length = sdp->sdp_header.HB3;4581 4582	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||4583	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||4584	    (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {4585		/*4586		 * - HB2 = 0x2, HB3 = 0x84587		 *   VSC SDP supporting 3D stereo + PSR4588		 * - HB2 = 0x4, HB3 = 0xe4589		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of4590		 *   first scan line of the SU region (applies to eDP v1.4b4591		 *   and higher).4592		 * - HB2 = 0x6, HB3 = 0x104593		 *   VSC SDP supporting 3D stereo + Panel Replay.4594		 */4595		return 0;4596	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {4597		/*4598		 * - HB2 = 0x5, HB3 = 0x134599		 *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry4600		 *   Format.4601		 */4602		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;4603		vsc->colorimetry = sdp->db[16] & 0xf;4604		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;4605 4606		switch (sdp->db[17] & 0x7) {4607		case 0x0:4608			vsc->bpc = 6;4609			break;4610		case 0x1:4611			vsc->bpc = 8;4612			break;4613		case 0x2:4614			vsc->bpc = 10;4615			break;4616		case 0x3:4617			vsc->bpc = 12;4618			break;4619		case 0x4:4620			vsc->bpc = 16;4621			break;4622		default:4623			MISSING_CASE(sdp->db[17] & 0x7);4624			return -EINVAL;4625		}4626 4627		vsc->content_type = sdp->db[18] & 0x7;4628	} else {4629		return -EINVAL;4630	}4631 4632	return 0;4633}4634 4635static void4636intel_read_dp_as_sdp(struct intel_encoder *encoder,4637		     struct intel_crtc_state *crtc_state,4638		     struct drm_dp_as_sdp *as_sdp)4639{4640	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);4641	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);4642	unsigned int type = DP_SDP_ADAPTIVE_SYNC;4643	struct dp_sdp sdp = {};4644	int ret;4645 4646	if ((crtc_state->infoframes.enable &4647	     intel_hdmi_infoframe_enable(type)) == 0)4648		return;4649 4650	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,4651				 sizeof(sdp));4652 4653	ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));4654	if (ret)4655		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");4656}4657 4658static int4659intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,4660					   const void *buffer, size_t size)4661{4662	int ret;4663 4664	const struct dp_sdp *sdp = buffer;4665 4666	if (size < sizeof(struct dp_sdp))4667		return -EINVAL;4668 4669	if (sdp->sdp_header.HB0 != 0)4670		return -EINVAL;4671 4672	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)4673		return -EINVAL;4674 4675	/*4676	 * Least Significant Eight Bits of (Data Byte Count – 1)4677	 * 1Dh (i.e., Data Byte Count = 30 bytes).4678	 */4679	if (sdp->sdp_header.HB2 != 0x1D)4680		return -EINVAL;4681 4682	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */4683	if ((sdp->sdp_header.HB3 & 0x3) != 0)4684		return -EINVAL;4685 4686	/* INFOFRAME SDP Version Number */4687	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)4688		return -EINVAL;4689 4690	/* CTA Header Byte 2 (INFOFRAME Version Number) */4691	if (sdp->db[0] != 1)4692		return -EINVAL;4693 4694	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */4695	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)4696		return -EINVAL;4697 4698	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],4699					     HDMI_DRM_INFOFRAME_SIZE);4700 4701	return ret;4702}4703 4704static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,4705				  struct intel_crtc_state *crtc_state,4706				  struct drm_dp_vsc_sdp *vsc)4707{4708	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);4709	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);4710	unsigned int type = DP_SDP_VSC;4711	struct dp_sdp sdp = {};4712	int ret;4713 4714	if ((crtc_state->infoframes.enable &4715	     intel_hdmi_infoframe_enable(type)) == 0)4716		return;4717 4718	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));4719 4720	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));4721 4722	if (ret)4723		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");4724}4725 4726static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,4727						     struct intel_crtc_state *crtc_state,4728						     struct hdmi_drm_infoframe *drm_infoframe)4729{4730	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);4731	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);4732	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;4733	struct dp_sdp sdp = {};4734	int ret;4735 4736	if ((crtc_state->infoframes.enable &4737	    intel_hdmi_infoframe_enable(type)) == 0)4738		return;4739 4740	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,4741				 sizeof(sdp));4742 4743	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,4744							 sizeof(sdp));4745 4746	if (ret)4747		drm_dbg_kms(&dev_priv->drm,4748			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");4749}4750 4751void intel_read_dp_sdp(struct intel_encoder *encoder,4752		       struct intel_crtc_state *crtc_state,4753		       unsigned int type)4754{4755	switch (type) {4756	case DP_SDP_VSC:4757		intel_read_dp_vsc_sdp(encoder, crtc_state,4758				      &crtc_state->infoframes.vsc);4759		break;4760	case HDMI_PACKET_TYPE_GAMUT_METADATA:4761		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,4762							 &crtc_state->infoframes.drm.drm);4763		break;4764	case DP_SDP_ADAPTIVE_SYNC:4765		intel_read_dp_as_sdp(encoder, crtc_state,4766				     &crtc_state->infoframes.as_sdp);4767		break;4768	default:4769		MISSING_CASE(type);4770		break;4771	}4772}4773 4774static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)4775{4776	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4777	int status = 0;4778	int test_link_rate;4779	u8 test_lane_count, test_link_bw;4780	/* (DP CTS 1.2)4781	 * 4.3.1.114782	 */4783	/* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */4784	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,4785				   &test_lane_count);4786 4787	if (status <= 0) {4788		drm_dbg_kms(&i915->drm, "Lane count read failed\n");4789		return DP_TEST_NAK;4790	}4791	test_lane_count &= DP_MAX_LANE_COUNT_MASK;4792 4793	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,4794				   &test_link_bw);4795	if (status <= 0) {4796		drm_dbg_kms(&i915->drm, "Link Rate read failed\n");4797		return DP_TEST_NAK;4798	}4799	test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);4800 4801	/* Validate the requested link rate and lane count */4802	if (!intel_dp_link_params_valid(intel_dp, test_link_rate,4803					test_lane_count))4804		return DP_TEST_NAK;4805 4806	intel_dp->compliance.test_lane_count = test_lane_count;4807	intel_dp->compliance.test_link_rate = test_link_rate;4808 4809	return DP_TEST_ACK;4810}4811 4812static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)4813{4814	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4815	u8 test_pattern;4816	u8 test_misc;4817	__be16 h_width, v_height;4818	int status = 0;4819 4820	/* Read the TEST_PATTERN (DP CTS 3.1.5) */4821	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,4822				   &test_pattern);4823	if (status <= 0) {4824		drm_dbg_kms(&i915->drm, "Test pattern read failed\n");4825		return DP_TEST_NAK;4826	}4827	if (test_pattern != DP_COLOR_RAMP)4828		return DP_TEST_NAK;4829 4830	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,4831				  &h_width, 2);4832	if (status <= 0) {4833		drm_dbg_kms(&i915->drm, "H Width read failed\n");4834		return DP_TEST_NAK;4835	}4836 4837	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,4838				  &v_height, 2);4839	if (status <= 0) {4840		drm_dbg_kms(&i915->drm, "V Height read failed\n");4841		return DP_TEST_NAK;4842	}4843 4844	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,4845				   &test_misc);4846	if (status <= 0) {4847		drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");4848		return DP_TEST_NAK;4849	}4850	if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)4851		return DP_TEST_NAK;4852	if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)4853		return DP_TEST_NAK;4854	switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {4855	case DP_TEST_BIT_DEPTH_6:4856		intel_dp->compliance.test_data.bpc = 6;4857		break;4858	case DP_TEST_BIT_DEPTH_8:4859		intel_dp->compliance.test_data.bpc = 8;4860		break;4861	default:4862		return DP_TEST_NAK;4863	}4864 4865	intel_dp->compliance.test_data.video_pattern = test_pattern;4866	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);4867	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);4868	/* Set test active flag here so userspace doesn't interrupt things */4869	intel_dp->compliance.test_active = true;4870 4871	return DP_TEST_ACK;4872}4873 4874static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)4875{4876	struct drm_i915_private *i915 = dp_to_i915(intel_dp);4877	u8 test_result = DP_TEST_ACK;4878	struct intel_connector *intel_connector = intel_dp->attached_connector;4879	struct drm_connector *connector = &intel_connector->base;4880 4881	if (intel_connector->detect_edid == NULL ||4882	    connector->edid_corrupt ||4883	    intel_dp->aux.i2c_defer_count > 6) {4884		/* Check EDID read for NACKs, DEFERs and corruption4885		 * (DP CTS 1.2 Core r1.1)4886		 *    4.2.2.4 : Failed EDID read, I2C_NAK4887		 *    4.2.2.5 : Failed EDID read, I2C_DEFER4888		 *    4.2.2.6 : EDID corruption detected4889		 * Use failsafe mode for all cases4890		 */4891		if (intel_dp->aux.i2c_nack_count > 0 ||4892			intel_dp->aux.i2c_defer_count > 0)4893			drm_dbg_kms(&i915->drm,4894				    "EDID read had %d NACKs, %d DEFERs\n",4895				    intel_dp->aux.i2c_nack_count,4896				    intel_dp->aux.i2c_defer_count);4897		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;4898	} else {4899		/* FIXME: Get rid of drm_edid_raw() */4900		const struct edid *block = drm_edid_raw(intel_connector->detect_edid);4901 4902		/* We have to write the checksum of the last block read */4903		block += block->extensions;4904 4905		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,4906				       block->checksum) <= 0)4907			drm_dbg_kms(&i915->drm,4908				    "Failed to write EDID checksum\n");4909 4910		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;4911		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;4912	}4913 4914	/* Set test active flag here so userspace doesn't interrupt things */4915	intel_dp->compliance.test_active = true;4916 4917	return test_result;4918}4919 4920static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,4921					const struct intel_crtc_state *crtc_state)4922{4923	struct drm_i915_private *dev_priv =4924			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);4925	struct drm_dp_phy_test_params *data =4926			&intel_dp->compliance.test_data.phytest;4927	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);4928	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;4929	enum pipe pipe = crtc->pipe;4930	u32 pattern_val;4931 4932	switch (data->phy_pattern) {4933	case DP_LINK_QUAL_PATTERN_DISABLE:4934		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");4935		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);4936		if (DISPLAY_VER(dev_priv) >= 10)4937			intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),4938				     DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,4939				     DP_TP_CTL_LINK_TRAIN_NORMAL);4940		break;4941	case DP_LINK_QUAL_PATTERN_D10_2:4942		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");4943		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),4944			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);4945		break;4946	case DP_LINK_QUAL_PATTERN_ERROR_RATE:4947		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");4948		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),4949			       DDI_DP_COMP_CTL_ENABLE |4950			       DDI_DP_COMP_CTL_SCRAMBLED_0);4951		break;4952	case DP_LINK_QUAL_PATTERN_PRBS7:4953		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");4954		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),4955			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);4956		break;4957	case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:4958		/*4959		 * FIXME: Ideally pattern should come from DPCD 0x250. As4960		 * current firmware of DPR-100 could not set it, so hardcoding4961		 * now for complaince test.4962		 */4963		drm_dbg_kms(&dev_priv->drm,4964			    "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");4965		pattern_val = 0x3e0f83e0;4966		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);4967		pattern_val = 0x0f83e0f8;4968		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);4969		pattern_val = 0x0000f83e;4970		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);4971		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),4972			       DDI_DP_COMP_CTL_ENABLE |4973			       DDI_DP_COMP_CTL_CUSTOM80);4974		break;4975	case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:4976		/*4977		 * FIXME: Ideally pattern should come from DPCD 0x24A. As4978		 * current firmware of DPR-100 could not set it, so hardcoding4979		 * now for complaince test.4980		 */4981		drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");4982		pattern_val = 0xFB;4983		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),4984			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |4985			       pattern_val);4986		break;4987	case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:4988		if (DISPLAY_VER(dev_priv) < 10)  {4989			drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");4990			break;4991		}4992		drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");4993		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);4994		intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),4995			     DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,4996			     DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);4997		break;4998	default:4999		drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");5000	}5001}5002 5003static void intel_dp_process_phy_request(struct intel_dp *intel_dp,5004					 const struct intel_crtc_state *crtc_state)5005{5006	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5007	struct drm_dp_phy_test_params *data =5008		&intel_dp->compliance.test_data.phytest;5009	u8 link_status[DP_LINK_STATUS_SIZE];5010 5011	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,5012					     link_status) < 0) {5013		drm_dbg_kms(&i915->drm, "failed to get link status\n");5014		return;5015	}5016 5017	/* retrieve vswing & pre-emphasis setting */5018	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,5019				  link_status);5020 5021	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);5022 5023	intel_dp_phy_pattern_update(intel_dp, crtc_state);5024 5025	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,5026			  intel_dp->train_set, crtc_state->lane_count);5027 5028	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,5029				    intel_dp->dpcd[DP_DPCD_REV]);5030}5031 5032static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)5033{5034	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5035	struct drm_dp_phy_test_params *data =5036		&intel_dp->compliance.test_data.phytest;5037 5038	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {5039		drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");5040		return DP_TEST_NAK;5041	}5042 5043	/* Set test active flag here so userspace doesn't interrupt things */5044	intel_dp->compliance.test_active = true;5045 5046	return DP_TEST_ACK;5047}5048 5049static void intel_dp_handle_test_request(struct intel_dp *intel_dp)5050{5051	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5052	u8 response = DP_TEST_NAK;5053	u8 request = 0;5054	int status;5055 5056	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);5057	if (status <= 0) {5058		drm_dbg_kms(&i915->drm,5059			    "Could not read test request from sink\n");5060		goto update_status;5061	}5062 5063	switch (request) {5064	case DP_TEST_LINK_TRAINING:5065		drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");5066		response = intel_dp_autotest_link_training(intel_dp);5067		break;5068	case DP_TEST_LINK_VIDEO_PATTERN:5069		drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");5070		response = intel_dp_autotest_video_pattern(intel_dp);5071		break;5072	case DP_TEST_LINK_EDID_READ:5073		drm_dbg_kms(&i915->drm, "EDID test requested\n");5074		response = intel_dp_autotest_edid(intel_dp);5075		break;5076	case DP_TEST_LINK_PHY_TEST_PATTERN:5077		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");5078		response = intel_dp_autotest_phy_pattern(intel_dp);5079		break;5080	default:5081		drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",5082			    request);5083		break;5084	}5085 5086	if (response & DP_TEST_ACK)5087		intel_dp->compliance.test_type = request;5088 5089update_status:5090	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);5091	if (status <= 0)5092		drm_dbg_kms(&i915->drm,5093			    "Could not write test response to sink\n");5094}5095 5096static bool intel_dp_link_ok(struct intel_dp *intel_dp,5097			     u8 link_status[DP_LINK_STATUS_SIZE])5098{5099	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;5100	struct drm_i915_private *i915 = to_i915(encoder->base.dev);5101	bool uhbr = intel_dp->link_rate >= 1000000;5102	bool ok;5103 5104	if (uhbr)5105		ok = drm_dp_128b132b_lane_channel_eq_done(link_status,5106							  intel_dp->lane_count);5107	else5108		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);5109 5110	if (ok)5111		return true;5112 5113	intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);5114	drm_dbg_kms(&i915->drm,5115		    "[ENCODER:%d:%s] %s link not ok, retraining\n",5116		    encoder->base.base.id, encoder->base.name,5117		    uhbr ? "128b/132b" : "8b/10b");5118 5119	return false;5120}5121 5122static void5123intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)5124{5125	bool handled = false;5126 5127	drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);5128 5129	if (esi[1] & DP_CP_IRQ) {5130		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);5131		ack[1] |= DP_CP_IRQ;5132	}5133}5134 5135static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)5136{5137	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;5138	struct drm_i915_private *i915 = to_i915(encoder->base.dev);5139	u8 link_status[DP_LINK_STATUS_SIZE] = {};5140	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;5141 5142	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,5143			     esi_link_status_size) != esi_link_status_size) {5144		drm_err(&i915->drm,5145			"[ENCODER:%d:%s] Failed to read link status\n",5146			encoder->base.base.id, encoder->base.name);5147		return false;5148	}5149 5150	return intel_dp_link_ok(intel_dp, link_status);5151}5152 5153/**5154 * intel_dp_check_mst_status - service any pending MST interrupts, check link status5155 * @intel_dp: Intel DP struct5156 *5157 * Read any pending MST interrupts, call MST core to handle these and ack the5158 * interrupts. Check if the main and AUX link state is ok.5159 *5160 * Returns:5161 * - %true if pending interrupts were serviced (or no interrupts were5162 *   pending) w/o detecting an error condition.5163 * - %false if an error condition - like AUX failure or a loss of link - is5164 *   detected, or another condition - like a DP tunnel BW state change - needs5165 *   servicing from the hotplug work.5166 */5167static bool5168intel_dp_check_mst_status(struct intel_dp *intel_dp)5169{5170	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5171	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);5172	struct intel_encoder *encoder = &dig_port->base;5173	bool link_ok = true;5174	bool reprobe_needed = false;5175 5176	drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);5177 5178	for (;;) {5179		u8 esi[4] = {};5180		u8 ack[4] = {};5181 5182		if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {5183			drm_dbg_kms(&i915->drm,5184				    "failed to get ESI - device may have failed\n");5185			link_ok = false;5186 5187			break;5188		}5189 5190		drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);5191 5192		if (intel_dp->active_mst_links > 0 && link_ok &&5193		    esi[3] & LINK_STATUS_CHANGED) {5194			if (!intel_dp_mst_link_status(intel_dp))5195				link_ok = false;5196			ack[3] |= LINK_STATUS_CHANGED;5197		}5198 5199		intel_dp_mst_hpd_irq(intel_dp, esi, ack);5200 5201		if (esi[3] & DP_TUNNELING_IRQ) {5202			if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,5203						     &intel_dp->aux))5204				reprobe_needed = true;5205			ack[3] |= DP_TUNNELING_IRQ;5206		}5207 5208		if (mem_is_zero(ack, sizeof(ack)))5209			break;5210 5211		if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))5212			drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");5213 5214		if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))5215			drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);5216	}5217 5218	if (!link_ok || intel_dp->link.force_retrain)5219		intel_encoder_link_check_queue_work(encoder, 0);5220 5221	return !reprobe_needed;5222}5223 5224static void5225intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)5226{5227	bool is_active;5228	u8 buf = 0;5229 5230	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);5231	if (intel_dp->frl.is_trained && !is_active) {5232		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)5233			return;5234 5235		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;5236		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)5237			return;5238 5239		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);5240 5241		intel_dp->frl.is_trained = false;5242 5243		/* Restart FRL training or fall back to TMDS mode */5244		intel_dp_check_frl_training(intel_dp);5245	}5246}5247 5248static bool5249intel_dp_needs_link_retrain(struct intel_dp *intel_dp)5250{5251	u8 link_status[DP_LINK_STATUS_SIZE];5252 5253	if (!intel_dp->link_trained)5254		return false;5255 5256	/*5257	 * While PSR source HW is enabled, it will control main-link sending5258	 * frames, enabling and disabling it so trying to do a retrain will fail5259	 * as the link would or not be on or it could mix training patterns5260	 * and frame data at the same time causing retrain to fail.5261	 * Also when exiting PSR, HW will retrain the link anyways fixing5262	 * any link status error.5263	 */5264	if (intel_psr_enabled(intel_dp))5265		return false;5266 5267	if (intel_dp->link.force_retrain)5268		return true;5269 5270	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,5271					     link_status) < 0)5272		return false;5273 5274	/*5275	 * Validate the cached values of intel_dp->link_rate and5276	 * intel_dp->lane_count before attempting to retrain.5277	 *5278	 * FIXME would be nice to user the crtc state here, but since5279	 * we need to call this from the short HPD handler that seems5280	 * a bit hard.5281	 */5282	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,5283					intel_dp->lane_count))5284		return false;5285 5286	if (intel_dp->link.retrain_disabled)5287		return false;5288 5289	if (intel_dp->link.seq_train_failures)5290		return true;5291 5292	/* Retrain if link not ok */5293	return !intel_dp_link_ok(intel_dp, link_status);5294}5295 5296static bool intel_dp_has_connector(struct intel_dp *intel_dp,5297				   const struct drm_connector_state *conn_state)5298{5299	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5300	struct intel_encoder *encoder;5301	enum pipe pipe;5302 5303	if (!conn_state->best_encoder)5304		return false;5305 5306	/* SST */5307	encoder = &dp_to_dig_port(intel_dp)->base;5308	if (conn_state->best_encoder == &encoder->base)5309		return true;5310 5311	/* MST */5312	for_each_pipe(i915, pipe) {5313		encoder = &intel_dp->mst_encoders[pipe]->base;5314		if (conn_state->best_encoder == &encoder->base)5315			return true;5316	}5317 5318	return false;5319}5320 5321int intel_dp_get_active_pipes(struct intel_dp *intel_dp,5322			      struct drm_modeset_acquire_ctx *ctx,5323			      u8 *pipe_mask)5324{5325	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5326	struct drm_connector_list_iter conn_iter;5327	struct intel_connector *connector;5328	int ret = 0;5329 5330	*pipe_mask = 0;5331 5332	drm_connector_list_iter_begin(&i915->drm, &conn_iter);5333	for_each_intel_connector_iter(connector, &conn_iter) {5334		struct drm_connector_state *conn_state =5335			connector->base.state;5336		struct intel_crtc_state *crtc_state;5337		struct intel_crtc *crtc;5338 5339		if (!intel_dp_has_connector(intel_dp, conn_state))5340			continue;5341 5342		crtc = to_intel_crtc(conn_state->crtc);5343		if (!crtc)5344			continue;5345 5346		ret = drm_modeset_lock(&crtc->base.mutex, ctx);5347		if (ret)5348			break;5349 5350		crtc_state = to_intel_crtc_state(crtc->base.state);5351 5352		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));5353 5354		if (!crtc_state->hw.active)5355			continue;5356 5357		if (conn_state->commit)5358			drm_WARN_ON(&i915->drm,5359				    !wait_for_completion_timeout(&conn_state->commit->hw_done,5360								 msecs_to_jiffies(5000)));5361 5362		*pipe_mask |= BIT(crtc->pipe);5363	}5364	drm_connector_list_iter_end(&conn_iter);5365 5366	return ret;5367}5368 5369static bool intel_dp_is_connected(struct intel_dp *intel_dp)5370{5371	struct intel_connector *connector = intel_dp->attached_connector;5372 5373	return connector->base.status == connector_status_connected ||5374		intel_dp->is_mst;5375}5376 5377static int intel_dp_retrain_link(struct intel_encoder *encoder,5378				 struct drm_modeset_acquire_ctx *ctx)5379{5380	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);5381	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);5382	u8 pipe_mask;5383	int ret;5384 5385	if (!intel_dp_is_connected(intel_dp))5386		return 0;5387 5388	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,5389			       ctx);5390	if (ret)5391		return ret;5392 5393	if (!intel_dp_needs_link_retrain(intel_dp))5394		return 0;5395 5396	ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);5397	if (ret)5398		return ret;5399 5400	if (pipe_mask == 0)5401		return 0;5402 5403	if (!intel_dp_needs_link_retrain(intel_dp))5404		return 0;5405 5406	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n",5407		    encoder->base.base.id, encoder->base.name,5408		    str_yes_no(intel_dp->link.force_retrain));5409 5410	ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);5411	if (ret == -EDEADLK)5412		return ret;5413 5414	intel_dp->link.force_retrain = false;5415 5416	if (ret)5417		drm_dbg_kms(&dev_priv->drm,5418			    "[ENCODER:%d:%s] link retraining failed: %pe\n",5419			    encoder->base.base.id, encoder->base.name,5420			    ERR_PTR(ret));5421 5422	return ret;5423}5424 5425void intel_dp_link_check(struct intel_encoder *encoder)5426{5427	struct drm_modeset_acquire_ctx ctx;5428	int ret;5429 5430	intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)5431		ret = intel_dp_retrain_link(encoder, &ctx);5432}5433 5434void intel_dp_check_link_state(struct intel_dp *intel_dp)5435{5436	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);5437	struct intel_encoder *encoder = &dig_port->base;5438 5439	if (!intel_dp_is_connected(intel_dp))5440		return;5441 5442	if (!intel_dp_needs_link_retrain(intel_dp))5443		return;5444 5445	intel_encoder_link_check_queue_work(encoder, 0);5446}5447 5448static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,5449				  struct drm_modeset_acquire_ctx *ctx,5450				  u8 *pipe_mask)5451{5452	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5453	struct drm_connector_list_iter conn_iter;5454	struct intel_connector *connector;5455	int ret = 0;5456 5457	*pipe_mask = 0;5458 5459	drm_connector_list_iter_begin(&i915->drm, &conn_iter);5460	for_each_intel_connector_iter(connector, &conn_iter) {5461		struct drm_connector_state *conn_state =5462			connector->base.state;5463		struct intel_crtc_state *crtc_state;5464		struct intel_crtc *crtc;5465 5466		if (!intel_dp_has_connector(intel_dp, conn_state))5467			continue;5468 5469		crtc = to_intel_crtc(conn_state->crtc);5470		if (!crtc)5471			continue;5472 5473		ret = drm_modeset_lock(&crtc->base.mutex, ctx);5474		if (ret)5475			break;5476 5477		crtc_state = to_intel_crtc_state(crtc->base.state);5478 5479		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));5480 5481		if (!crtc_state->hw.active)5482			continue;5483 5484		if (conn_state->commit &&5485		    !try_wait_for_completion(&conn_state->commit->hw_done))5486			continue;5487 5488		*pipe_mask |= BIT(crtc->pipe);5489	}5490	drm_connector_list_iter_end(&conn_iter);5491 5492	return ret;5493}5494 5495static int intel_dp_do_phy_test(struct intel_encoder *encoder,5496				struct drm_modeset_acquire_ctx *ctx)5497{5498	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);5499	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);5500	struct intel_crtc *crtc;5501	u8 pipe_mask;5502	int ret;5503 5504	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,5505			       ctx);5506	if (ret)5507		return ret;5508 5509	ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);5510	if (ret)5511		return ret;5512 5513	if (pipe_mask == 0)5514		return 0;5515 5516	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",5517		    encoder->base.base.id, encoder->base.name);5518 5519	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {5520		const struct intel_crtc_state *crtc_state =5521			to_intel_crtc_state(crtc->base.state);5522 5523		/* test on the MST master transcoder */5524		if (DISPLAY_VER(dev_priv) >= 12 &&5525		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&5526		    !intel_dp_mst_is_master_trans(crtc_state))5527			continue;5528 5529		intel_dp_process_phy_request(intel_dp, crtc_state);5530		break;5531	}5532 5533	return 0;5534}5535 5536void intel_dp_phy_test(struct intel_encoder *encoder)5537{5538	struct drm_modeset_acquire_ctx ctx;5539	int ret;5540 5541	drm_modeset_acquire_init(&ctx, 0);5542 5543	for (;;) {5544		ret = intel_dp_do_phy_test(encoder, &ctx);5545 5546		if (ret == -EDEADLK) {5547			drm_modeset_backoff(&ctx);5548			continue;5549		}5550 5551		break;5552	}5553 5554	drm_modeset_drop_locks(&ctx);5555	drm_modeset_acquire_fini(&ctx);5556	drm_WARN(encoder->base.dev, ret,5557		 "Acquiring modeset locks failed with %i\n", ret);5558}5559 5560static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)5561{5562	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5563	u8 val;5564 5565	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)5566		return;5567 5568	if (drm_dp_dpcd_readb(&intel_dp->aux,5569			      DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)5570		return;5571 5572	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);5573 5574	if (val & DP_AUTOMATED_TEST_REQUEST)5575		intel_dp_handle_test_request(intel_dp);5576 5577	if (val & DP_CP_IRQ)5578		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);5579 5580	if (val & DP_SINK_SPECIFIC_IRQ)5581		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");5582}5583 5584static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)5585{5586	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5587	bool reprobe_needed = false;5588	u8 val;5589 5590	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)5591		return false;5592 5593	if (drm_dp_dpcd_readb(&intel_dp->aux,5594			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)5595		return false;5596 5597	if ((val & DP_TUNNELING_IRQ) &&5598	    drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,5599				     &intel_dp->aux))5600		reprobe_needed = true;5601 5602	if (drm_dp_dpcd_writeb(&intel_dp->aux,5603			       DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)5604		return reprobe_needed;5605 5606	if (val & HDMI_LINK_STATUS_CHANGED)5607		intel_dp_handle_hdmi_link_status_change(intel_dp);5608 5609	return reprobe_needed;5610}5611 5612/*5613 * According to DP spec5614 * 5.1.2:5615 *  1. Read DPCD5616 *  2. Configure link according to Receiver Capabilities5617 *  3. Use Link Training from 2.5.3.3 and 3.5.1.35618 *  4. Check link status on receipt of hot-plug interrupt5619 *5620 * intel_dp_short_pulse -  handles short pulse interrupts5621 * when full detection is not required.5622 * Returns %true if short pulse is handled and full detection5623 * is NOT required and %false otherwise.5624 */5625static bool5626intel_dp_short_pulse(struct intel_dp *intel_dp)5627{5628	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);5629	u8 old_sink_count = intel_dp->sink_count;5630	bool reprobe_needed = false;5631	bool ret;5632 5633	/*5634	 * Clearing compliance test variables to allow capturing5635	 * of values for next automated test request.5636	 */5637	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));5638 5639	/*5640	 * Now read the DPCD to see if it's actually running5641	 * If the current value of sink count doesn't match with5642	 * the value that was stored earlier or dpcd read failed5643	 * we need to do full detection5644	 */5645	ret = intel_dp_get_dpcd(intel_dp);5646 5647	if ((old_sink_count != intel_dp->sink_count) || !ret) {5648		/* No need to proceed if we are going to do full detect */5649		return false;5650	}5651 5652	intel_dp_check_device_service_irq(intel_dp);5653	reprobe_needed = intel_dp_check_link_service_irq(intel_dp);5654 5655	/* Handle CEC interrupts, if any */5656	drm_dp_cec_irq(&intel_dp->aux);5657 5658	intel_dp_check_link_state(intel_dp);5659 5660	intel_psr_short_pulse(intel_dp);5661 5662	switch (intel_dp->compliance.test_type) {5663	case DP_TEST_LINK_TRAINING:5664		drm_dbg_kms(&dev_priv->drm,5665			    "Link Training Compliance Test requested\n");5666		/* Send a Hotplug Uevent to userspace to start modeset */5667		drm_kms_helper_hotplug_event(&dev_priv->drm);5668		break;5669	case DP_TEST_LINK_PHY_TEST_PATTERN:5670		drm_dbg_kms(&dev_priv->drm,5671			    "PHY test pattern Compliance Test requested\n");5672		/*5673		 * Schedule long hpd to do the test5674		 *5675		 * FIXME get rid of the ad-hoc phy test modeset code5676		 * and properly incorporate it into the normal modeset.5677		 */5678		reprobe_needed = true;5679	}5680 5681	return !reprobe_needed;5682}5683 5684/* XXX this is probably wrong for multiple downstream ports */5685static enum drm_connector_status5686intel_dp_detect_dpcd(struct intel_dp *intel_dp)5687{5688	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5689	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);5690	u8 *dpcd = intel_dp->dpcd;5691	u8 type;5692 5693	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))5694		return connector_status_connected;5695 5696	lspcon_resume(dig_port);5697 5698	if (!intel_dp_get_dpcd(intel_dp))5699		return connector_status_disconnected;5700 5701	intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);5702 5703	/* if there's no downstream port, we're done */5704	if (!drm_dp_is_branch(dpcd))5705		return connector_status_connected;5706 5707	/* If we're HPD-aware, SINK_COUNT changes dynamically */5708	if (intel_dp_has_sink_count(intel_dp) &&5709	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {5710		return intel_dp->sink_count ?5711		connector_status_connected : connector_status_disconnected;5712	}5713 5714	if (intel_dp->mst_detect == DRM_DP_MST)5715		return connector_status_connected;5716 5717	/* If no HPD, poke DDC gently */5718	if (drm_probe_ddc(&intel_dp->aux.ddc))5719		return connector_status_connected;5720 5721	/* Well we tried, say unknown for unreliable port types */5722	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {5723		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;5724		if (type == DP_DS_PORT_TYPE_VGA ||5725		    type == DP_DS_PORT_TYPE_NON_EDID)5726			return connector_status_unknown;5727	} else {5728		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &5729			DP_DWN_STRM_PORT_TYPE_MASK;5730		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||5731		    type == DP_DWN_STRM_PORT_TYPE_OTHER)5732			return connector_status_unknown;5733	}5734 5735	/* Anything else is out of spec, warn and ignore */5736	drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");5737	return connector_status_disconnected;5738}5739 5740static enum drm_connector_status5741edp_detect(struct intel_dp *intel_dp)5742{5743	return connector_status_connected;5744}5745 5746void intel_digital_port_lock(struct intel_encoder *encoder)5747{5748	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);5749 5750	if (dig_port->lock)5751		dig_port->lock(dig_port);5752}5753 5754void intel_digital_port_unlock(struct intel_encoder *encoder)5755{5756	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);5757 5758	if (dig_port->unlock)5759		dig_port->unlock(dig_port);5760}5761 5762/*5763 * intel_digital_port_connected_locked - is the specified port connected?5764 * @encoder: intel_encoder5765 *5766 * In cases where there's a connector physically connected but it can't be used5767 * by our hardware we also return false, since the rest of the driver should5768 * pretty much treat the port as disconnected. This is relevant for type-C5769 * (starting on ICL) where there's ownership involved.5770 *5771 * The caller must hold the lock acquired by calling intel_digital_port_lock()5772 * when calling this function.5773 *5774 * Return %true if port is connected, %false otherwise.5775 */5776bool intel_digital_port_connected_locked(struct intel_encoder *encoder)5777{5778	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);5779	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);5780	bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);5781	bool is_connected = false;5782	intel_wakeref_t wakeref;5783 5784	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {5785		unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);5786 5787		do {5788			is_connected = dig_port->connected(encoder);5789			if (is_connected || is_glitch_free)5790				break;5791			usleep_range(10, 30);5792		} while (time_before(jiffies, wait_expires));5793	}5794 5795	return is_connected;5796}5797 5798bool intel_digital_port_connected(struct intel_encoder *encoder)5799{5800	bool ret;5801 5802	intel_digital_port_lock(encoder);5803	ret = intel_digital_port_connected_locked(encoder);5804	intel_digital_port_unlock(encoder);5805 5806	return ret;5807}5808 5809static const struct drm_edid *5810intel_dp_get_edid(struct intel_dp *intel_dp)5811{5812	struct intel_connector *connector = intel_dp->attached_connector;5813	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;5814 5815	/* Use panel fixed edid if we have one */5816	if (fixed_edid) {5817		/* invalid edid */5818		if (IS_ERR(fixed_edid))5819			return NULL;5820 5821		return drm_edid_dup(fixed_edid);5822	}5823 5824	return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);5825}5826 5827static void5828intel_dp_update_dfp(struct intel_dp *intel_dp,5829		    const struct drm_edid *drm_edid)5830{5831	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5832	struct intel_connector *connector = intel_dp->attached_connector;5833 5834	intel_dp->dfp.max_bpc =5835		drm_dp_downstream_max_bpc(intel_dp->dpcd,5836					  intel_dp->downstream_ports, drm_edid);5837 5838	intel_dp->dfp.max_dotclock =5839		drm_dp_downstream_max_dotclock(intel_dp->dpcd,5840					       intel_dp->downstream_ports);5841 5842	intel_dp->dfp.min_tmds_clock =5843		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,5844						 intel_dp->downstream_ports,5845						 drm_edid);5846	intel_dp->dfp.max_tmds_clock =5847		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,5848						 intel_dp->downstream_ports,5849						 drm_edid);5850 5851	intel_dp->dfp.pcon_max_frl_bw =5852		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,5853					   intel_dp->downstream_ports);5854 5855	drm_dbg_kms(&i915->drm,5856		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",5857		    connector->base.base.id, connector->base.name,5858		    intel_dp->dfp.max_bpc,5859		    intel_dp->dfp.max_dotclock,5860		    intel_dp->dfp.min_tmds_clock,5861		    intel_dp->dfp.max_tmds_clock,5862		    intel_dp->dfp.pcon_max_frl_bw);5863 5864	intel_dp_get_pcon_dsc_cap(intel_dp);5865}5866 5867static bool5868intel_dp_can_ycbcr420(struct intel_dp *intel_dp)5869{5870	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&5871	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))5872		return true;5873 5874	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&5875	    dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))5876		return true;5877 5878	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&5879	    dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))5880		return true;5881 5882	return false;5883}5884 5885static void5886intel_dp_update_420(struct intel_dp *intel_dp)5887{5888	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5889	struct intel_connector *connector = intel_dp->attached_connector;5890 5891	intel_dp->dfp.ycbcr420_passthrough =5892		drm_dp_downstream_420_passthrough(intel_dp->dpcd,5893						  intel_dp->downstream_ports);5894	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */5895	intel_dp->dfp.ycbcr_444_to_420 =5896		dp_to_dig_port(intel_dp)->lspcon.active ||5897		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,5898							intel_dp->downstream_ports);5899	intel_dp->dfp.rgb_to_ycbcr =5900		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,5901							  intel_dp->downstream_ports,5902							  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);5903 5904	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);5905 5906	drm_dbg_kms(&i915->drm,5907		    "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",5908		    connector->base.base.id, connector->base.name,5909		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),5910		    str_yes_no(connector->base.ycbcr_420_allowed),5911		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));5912}5913 5914static void5915intel_dp_set_edid(struct intel_dp *intel_dp)5916{5917	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5918	struct intel_connector *connector = intel_dp->attached_connector;5919	const struct drm_edid *drm_edid;5920	bool vrr_capable;5921 5922	intel_dp_unset_edid(intel_dp);5923	drm_edid = intel_dp_get_edid(intel_dp);5924	connector->detect_edid = drm_edid;5925 5926	/* Below we depend on display info having been updated */5927	drm_edid_connector_update(&connector->base, drm_edid);5928 5929	vrr_capable = intel_vrr_is_capable(connector);5930	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",5931		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));5932	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);5933 5934	intel_dp_update_dfp(intel_dp, drm_edid);5935	intel_dp_update_420(intel_dp);5936 5937	drm_dp_cec_attach(&intel_dp->aux,5938			  connector->base.display_info.source_physical_address);5939}5940 5941static void5942intel_dp_unset_edid(struct intel_dp *intel_dp)5943{5944	struct intel_connector *connector = intel_dp->attached_connector;5945 5946	drm_dp_cec_unset_edid(&intel_dp->aux);5947	drm_edid_free(connector->detect_edid);5948	connector->detect_edid = NULL;5949 5950	intel_dp->dfp.max_bpc = 0;5951	intel_dp->dfp.max_dotclock = 0;5952	intel_dp->dfp.min_tmds_clock = 0;5953	intel_dp->dfp.max_tmds_clock = 0;5954 5955	intel_dp->dfp.pcon_max_frl_bw = 0;5956 5957	intel_dp->dfp.ycbcr_444_to_420 = false;5958	connector->base.ycbcr_420_allowed = false;5959 5960	drm_connector_set_vrr_capable_property(&connector->base,5961					       false);5962}5963 5964static void5965intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)5966{5967	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5968 5969	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */5970	if (!HAS_DSC(i915))5971		return;5972 5973	if (intel_dp_is_edp(intel_dp))5974		intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],5975					   connector);5976	else5977		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],5978					  connector);5979}5980 5981static void5982intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)5983{5984	struct drm_i915_private *i915 = dp_to_i915(intel_dp);5985 5986	intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&5987		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);5988}5989 5990static int5991intel_dp_detect(struct drm_connector *connector,5992		struct drm_modeset_acquire_ctx *ctx,5993		bool force)5994{5995	struct drm_i915_private *dev_priv = to_i915(connector->dev);5996	struct intel_connector *intel_connector =5997		to_intel_connector(connector);5998	struct intel_dp *intel_dp = intel_attached_dp(intel_connector);5999	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);6000	struct intel_encoder *encoder = &dig_port->base;6001	enum drm_connector_status status;6002	int ret;6003 6004	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",6005		    connector->base.id, connector->name);6006	drm_WARN_ON(&dev_priv->drm,6007		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));6008 6009	if (!intel_display_device_enabled(dev_priv))6010		return connector_status_disconnected;6011 6012	if (!intel_display_driver_check_access(dev_priv))6013		return connector->status;6014 6015	/* Can't disconnect eDP */6016	if (intel_dp_is_edp(intel_dp))6017		status = edp_detect(intel_dp);6018	else if (intel_digital_port_connected(encoder))6019		status = intel_dp_detect_dpcd(intel_dp);6020	else6021		status = connector_status_disconnected;6022 6023	if (status != connector_status_disconnected &&6024	    !intel_dp_mst_verify_dpcd_state(intel_dp))6025		/*6026		 * This requires retrying detection for instance to re-enable6027		 * the MST mode that got reset via a long HPD pulse. The retry6028		 * will happen either via the hotplug handler's retry logic,6029		 * ensured by setting the connector here to SST/disconnected,6030		 * or via a userspace connector probing in response to the6031		 * hotplug uevent sent when removing the MST connectors.6032		 */6033		status = connector_status_disconnected;6034 6035	if (status == connector_status_disconnected) {6036		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));6037		memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));6038		intel_dp->psr.sink_panel_replay_support = false;6039		intel_dp->psr.sink_panel_replay_su_support = false;6040 6041		intel_dp_mst_disconnect(intel_dp);6042 6043		intel_dp_tunnel_disconnect(intel_dp);6044 6045		goto out;6046	}6047 6048	ret = intel_dp_tunnel_detect(intel_dp, ctx);6049	if (ret == -EDEADLK)6050		return ret;6051 6052	if (ret == 1)6053		intel_connector->base.epoch_counter++;6054 6055	if (!intel_dp_is_edp(intel_dp))6056		intel_psr_init_dpcd(intel_dp);6057 6058	intel_dp_detect_dsc_caps(intel_dp, intel_connector);6059 6060	intel_dp_detect_sdp_caps(intel_dp);6061 6062	if (intel_dp->reset_link_params) {6063		intel_dp_reset_link_params(intel_dp);6064		intel_dp->reset_link_params = false;6065	}6066 6067	intel_dp_mst_configure(intel_dp);6068 6069	intel_dp_print_rates(intel_dp);6070 6071	if (intel_dp->is_mst) {6072		/*6073		 * If we are in MST mode then this connector6074		 * won't appear connected or have anything6075		 * with EDID on it6076		 */6077		status = connector_status_disconnected;6078		goto out;6079	}6080 6081	/*6082	 * Some external monitors do not signal loss of link synchronization6083	 * with an IRQ_HPD, so force a link status check.6084	 *6085	 * TODO: this probably became redundant, so remove it: the link state6086	 * is rechecked/recovered now after modesets, where the loss of6087	 * synchronization tends to occur.6088	 */6089	if (!intel_dp_is_edp(intel_dp))6090		intel_dp_check_link_state(intel_dp);6091 6092	/*6093	 * Clearing NACK and defer counts to get their exact values6094	 * while reading EDID which are required by Compliance tests6095	 * 4.2.2.4 and 4.2.2.56096	 */6097	intel_dp->aux.i2c_nack_count = 0;6098	intel_dp->aux.i2c_defer_count = 0;6099 6100	intel_dp_set_edid(intel_dp);6101	if (intel_dp_is_edp(intel_dp) ||6102	    to_intel_connector(connector)->detect_edid)6103		status = connector_status_connected;6104 6105	intel_dp_check_device_service_irq(intel_dp);6106 6107out:6108	if (status != connector_status_connected && !intel_dp->is_mst)6109		intel_dp_unset_edid(intel_dp);6110 6111	if (!intel_dp_is_edp(intel_dp))6112		drm_dp_set_subconnector_property(connector,6113						 status,6114						 intel_dp->dpcd,6115						 intel_dp->downstream_ports);6116	return status;6117}6118 6119static void6120intel_dp_force(struct drm_connector *connector)6121{6122	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));6123	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);6124	struct intel_encoder *intel_encoder = &dig_port->base;6125	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);6126 6127	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",6128		    connector->base.id, connector->name);6129 6130	if (!intel_display_driver_check_access(dev_priv))6131		return;6132 6133	intel_dp_unset_edid(intel_dp);6134 6135	if (connector->status != connector_status_connected)6136		return;6137 6138	intel_dp_set_edid(intel_dp);6139}6140 6141static int intel_dp_get_modes(struct drm_connector *connector)6142{6143	struct intel_connector *intel_connector = to_intel_connector(connector);6144	int num_modes;6145 6146	/* drm_edid_connector_update() done in ->detect() or ->force() */6147	num_modes = drm_edid_connector_add_modes(connector);6148 6149	/* Also add fixed mode, which may or may not be present in EDID */6150	if (intel_dp_is_edp(intel_attached_dp(intel_connector)))6151		num_modes += intel_panel_get_modes(intel_connector);6152 6153	if (num_modes)6154		return num_modes;6155 6156	if (!intel_connector->detect_edid) {6157		struct intel_dp *intel_dp = intel_attached_dp(intel_connector);6158		struct drm_display_mode *mode;6159 6160		mode = drm_dp_downstream_mode(connector->dev,6161					      intel_dp->dpcd,6162					      intel_dp->downstream_ports);6163		if (mode) {6164			drm_mode_probed_add(connector, mode);6165			num_modes++;6166		}6167	}6168 6169	return num_modes;6170}6171 6172static int6173intel_dp_connector_register(struct drm_connector *connector)6174{6175	struct drm_i915_private *i915 = to_i915(connector->dev);6176	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));6177	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);6178	struct intel_lspcon *lspcon = &dig_port->lspcon;6179	int ret;6180 6181	ret = intel_connector_register(connector);6182	if (ret)6183		return ret;6184 6185	drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",6186		    intel_dp->aux.name, connector->kdev->kobj.name);6187 6188	intel_dp->aux.dev = connector->kdev;6189	ret = drm_dp_aux_register(&intel_dp->aux);6190	if (!ret)6191		drm_dp_cec_register_connector(&intel_dp->aux, connector);6192 6193	if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))6194		return ret;6195 6196	/*6197	 * ToDo: Clean this up to handle lspcon init and resume more6198	 * efficiently and streamlined.6199	 */6200	if (lspcon_init(dig_port)) {6201		lspcon_detect_hdr_capability(lspcon);6202		if (lspcon->hdr_supported)6203			drm_connector_attach_hdr_output_metadata_property(connector);6204	}6205 6206	return ret;6207}6208 6209static void6210intel_dp_connector_unregister(struct drm_connector *connector)6211{6212	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));6213 6214	drm_dp_cec_unregister_connector(&intel_dp->aux);6215	drm_dp_aux_unregister(&intel_dp->aux);6216	intel_connector_unregister(connector);6217}6218 6219void intel_dp_connector_sync_state(struct intel_connector *connector,6220				   const struct intel_crtc_state *crtc_state)6221{6222	struct drm_i915_private *i915 = to_i915(connector->base.dev);6223 6224	if (crtc_state && crtc_state->dsc.compression_enable) {6225		drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);6226		connector->dp.dsc_decompression_enabled = true;6227	} else {6228		connector->dp.dsc_decompression_enabled = false;6229	}6230}6231 6232void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)6233{6234	struct intel_encoder *encoder = to_intel_encoder(_encoder);6235	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);6236	struct intel_dp *intel_dp = &dig_port->dp;6237 6238	intel_encoder_link_check_flush_work(encoder);6239 6240	intel_dp_mst_encoder_cleanup(dig_port);6241 6242	intel_dp_tunnel_destroy(intel_dp);6243 6244	intel_pps_vdd_off_sync(intel_dp);6245 6246	/*6247	 * Ensure power off delay is respected on module remove, so that we can6248	 * reduce delays at driver probe. See pps_init_timestamps().6249	 */6250	intel_pps_wait_power_cycle(intel_dp);6251 6252	intel_dp_aux_fini(intel_dp);6253}6254 6255void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)6256{6257	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);6258 6259	intel_pps_vdd_off_sync(intel_dp);6260 6261	intel_dp_tunnel_suspend(intel_dp);6262}6263 6264void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)6265{6266	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);6267 6268	intel_pps_wait_power_cycle(intel_dp);6269}6270 6271static int intel_modeset_tile_group(struct intel_atomic_state *state,6272				    int tile_group_id)6273{6274	struct drm_i915_private *dev_priv = to_i915(state->base.dev);6275	struct drm_connector_list_iter conn_iter;6276	struct drm_connector *connector;6277	int ret = 0;6278 6279	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);6280	drm_for_each_connector_iter(connector, &conn_iter) {6281		struct drm_connector_state *conn_state;6282		struct intel_crtc_state *crtc_state;6283		struct intel_crtc *crtc;6284 6285		if (!connector->has_tile ||6286		    connector->tile_group->id != tile_group_id)6287			continue;6288 6289		conn_state = drm_atomic_get_connector_state(&state->base,6290							    connector);6291		if (IS_ERR(conn_state)) {6292			ret = PTR_ERR(conn_state);6293			break;6294		}6295 6296		crtc = to_intel_crtc(conn_state->crtc);6297 6298		if (!crtc)6299			continue;6300 6301		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);6302		crtc_state->uapi.mode_changed = true;6303 6304		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);6305		if (ret)6306			break;6307	}6308	drm_connector_list_iter_end(&conn_iter);6309 6310	return ret;6311}6312 6313static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)6314{6315	struct drm_i915_private *dev_priv = to_i915(state->base.dev);6316	struct intel_crtc *crtc;6317 6318	if (transcoders == 0)6319		return 0;6320 6321	for_each_intel_crtc(&dev_priv->drm, crtc) {6322		struct intel_crtc_state *crtc_state;6323		int ret;6324 6325		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);6326		if (IS_ERR(crtc_state))6327			return PTR_ERR(crtc_state);6328 6329		if (!crtc_state->hw.enable)6330			continue;6331 6332		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))6333			continue;6334 6335		crtc_state->uapi.mode_changed = true;6336 6337		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);6338		if (ret)6339			return ret;6340 6341		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);6342		if (ret)6343			return ret;6344 6345		transcoders &= ~BIT(crtc_state->cpu_transcoder);6346	}6347 6348	drm_WARN_ON(&dev_priv->drm, transcoders != 0);6349 6350	return 0;6351}6352 6353static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,6354				      struct drm_connector *connector)6355{6356	const struct drm_connector_state *old_conn_state =6357		drm_atomic_get_old_connector_state(&state->base, connector);6358	const struct intel_crtc_state *old_crtc_state;6359	struct intel_crtc *crtc;6360	u8 transcoders;6361 6362	crtc = to_intel_crtc(old_conn_state->crtc);6363	if (!crtc)6364		return 0;6365 6366	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);6367 6368	if (!old_crtc_state->hw.active)6369		return 0;6370 6371	transcoders = old_crtc_state->sync_mode_slaves_mask;6372	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)6373		transcoders |= BIT(old_crtc_state->master_transcoder);6374 6375	return intel_modeset_affected_transcoders(state,6376						  transcoders);6377}6378 6379static int intel_dp_connector_atomic_check(struct drm_connector *conn,6380					   struct drm_atomic_state *_state)6381{6382	struct drm_i915_private *dev_priv = to_i915(conn->dev);6383	struct intel_atomic_state *state = to_intel_atomic_state(_state);6384	struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);6385	struct intel_connector *intel_conn = to_intel_connector(conn);6386	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);6387	int ret;6388 6389	ret = intel_digital_connector_atomic_check(conn, &state->base);6390	if (ret)6391		return ret;6392 6393	if (intel_dp_mst_source_support(intel_dp)) {6394		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);6395		if (ret)6396			return ret;6397	}6398 6399	if (!intel_connector_needs_modeset(state, conn))6400		return 0;6401 6402	ret = intel_dp_tunnel_atomic_check_state(state,6403						 intel_dp,6404						 intel_conn);6405	if (ret)6406		return ret;6407 6408	/*6409	 * We don't enable port sync on BDW due to missing w/as and6410	 * due to not having adjusted the modeset sequence appropriately.6411	 */6412	if (DISPLAY_VER(dev_priv) < 9)6413		return 0;6414 6415	if (conn->has_tile) {6416		ret = intel_modeset_tile_group(state, conn->tile_group->id);6417		if (ret)6418			return ret;6419	}6420 6421	return intel_modeset_synced_crtcs(state, conn);6422}6423 6424static void intel_dp_oob_hotplug_event(struct drm_connector *connector,6425				       enum drm_connector_status hpd_state)6426{6427	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));6428	struct drm_i915_private *i915 = to_i915(connector->dev);6429	bool hpd_high = hpd_state == connector_status_connected;6430	unsigned int hpd_pin = encoder->hpd_pin;6431	bool need_work = false;6432 6433	spin_lock_irq(&i915->irq_lock);6434	if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {6435		i915->display.hotplug.event_bits |= BIT(hpd_pin);6436 6437		__assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);6438		need_work = true;6439	}6440	spin_unlock_irq(&i915->irq_lock);6441 6442	if (need_work)6443		intel_hpd_schedule_detection(i915);6444}6445 6446static const struct drm_connector_funcs intel_dp_connector_funcs = {6447	.force = intel_dp_force,6448	.fill_modes = drm_helper_probe_single_connector_modes,6449	.atomic_get_property = intel_digital_connector_atomic_get_property,6450	.atomic_set_property = intel_digital_connector_atomic_set_property,6451	.late_register = intel_dp_connector_register,6452	.early_unregister = intel_dp_connector_unregister,6453	.destroy = intel_connector_destroy,6454	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,6455	.atomic_duplicate_state = intel_digital_connector_duplicate_state,6456	.oob_hotplug_event = intel_dp_oob_hotplug_event,6457};6458 6459static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {6460	.detect_ctx = intel_dp_detect,6461	.get_modes = intel_dp_get_modes,6462	.mode_valid = intel_dp_mode_valid,6463	.atomic_check = intel_dp_connector_atomic_check,6464};6465 6466enum irqreturn6467intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)6468{6469	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);6470	struct intel_dp *intel_dp = &dig_port->dp;6471	u8 dpcd[DP_RECEIVER_CAP_SIZE];6472 6473	if (dig_port->base.type == INTEL_OUTPUT_EDP &&6474	    (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {6475		/*6476		 * vdd off can generate a long/short pulse on eDP which6477		 * would require vdd on to handle it, and thus we6478		 * would end up in an endless cycle of6479		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."6480		 */6481		drm_dbg_kms(&i915->drm,6482			    "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",6483			    long_hpd ? "long" : "short",6484			    dig_port->base.base.base.id,6485			    dig_port->base.base.name);6486		return IRQ_HANDLED;6487	}6488 6489	drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",6490		    dig_port->base.base.base.id,6491		    dig_port->base.base.name,6492		    long_hpd ? "long" : "short");6493 6494	/*6495	 * TBT DP tunnels require the GFX driver to read out the DPRX caps in6496	 * response to long HPD pulses. The DP hotplug handler does that,6497	 * however the hotplug handler may be blocked by another6498	 * connector's/encoder's hotplug handler. Since the TBT CM may not6499	 * complete the DP tunnel BW request for the latter connector/encoder6500	 * waiting for this encoder's DPRX read, perform a dummy read here.6501	 */6502	if (long_hpd)6503		intel_dp_read_dprx_caps(intel_dp, dpcd);6504 6505	if (long_hpd) {6506		intel_dp->reset_link_params = true;6507		return IRQ_NONE;6508	}6509 6510	if (intel_dp->is_mst) {6511		if (!intel_dp_check_mst_status(intel_dp))6512			return IRQ_NONE;6513	} else if (!intel_dp_short_pulse(intel_dp)) {6514		return IRQ_NONE;6515	}6516 6517	return IRQ_HANDLED;6518}6519 6520static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,6521				  const struct intel_bios_encoder_data *devdata,6522				  enum port port)6523{6524	/*6525	 * eDP not supported on g4x. so bail out early just6526	 * for a bit extra safety in case the VBT is bonkers.6527	 */6528	if (DISPLAY_VER(dev_priv) < 5)6529		return false;6530 6531	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)6532		return true;6533 6534	return devdata && intel_bios_encoder_supports_edp(devdata);6535}6536 6537bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)6538{6539	struct intel_display *display = &i915->display;6540	const struct intel_bios_encoder_data *devdata =6541		intel_bios_encoder_data_lookup(display, port);6542 6543	return _intel_dp_is_port_edp(i915, devdata, port);6544}6545 6546bool6547intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)6548{6549	struct drm_i915_private *i915 = to_i915(encoder->base.dev);6550	enum port port = encoder->port;6551 6552	if (intel_bios_encoder_is_lspcon(encoder->devdata))6553		return false;6554 6555	if (DISPLAY_VER(i915) >= 11)6556		return true;6557 6558	if (port == PORT_A)6559		return false;6560 6561	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||6562	    DISPLAY_VER(i915) >= 9)6563		return true;6564 6565	return false;6566}6567 6568static void6569intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)6570{6571	struct drm_i915_private *dev_priv = to_i915(connector->dev);6572	enum port port = dp_to_dig_port(intel_dp)->base.port;6573 6574	if (!intel_dp_is_edp(intel_dp))6575		drm_connector_attach_dp_subconnector_property(connector);6576 6577	if (!IS_G4X(dev_priv) && port != PORT_A)6578		intel_attach_force_audio_property(connector);6579 6580	intel_attach_broadcast_rgb_property(connector);6581	if (HAS_GMCH(dev_priv))6582		drm_connector_attach_max_bpc_property(connector, 6, 10);6583	else if (DISPLAY_VER(dev_priv) >= 5)6584		drm_connector_attach_max_bpc_property(connector, 6, 12);6585 6586	/* Register HDMI colorspace for case of lspcon */6587	if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {6588		drm_connector_attach_content_type_property(connector);6589		intel_attach_hdmi_colorspace_property(connector);6590	} else {6591		intel_attach_dp_colorspace_property(connector);6592	}6593 6594	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))6595		drm_connector_attach_hdr_output_metadata_property(connector);6596 6597	if (HAS_VRR(dev_priv))6598		drm_connector_attach_vrr_capable_property(connector);6599}6600 6601static void6602intel_edp_add_properties(struct intel_dp *intel_dp)6603{6604	struct intel_connector *connector = intel_dp->attached_connector;6605	struct drm_i915_private *i915 = to_i915(connector->base.dev);6606	const struct drm_display_mode *fixed_mode =6607		intel_panel_preferred_fixed_mode(connector);6608 6609	intel_attach_scaling_mode_property(&connector->base);6610 6611	drm_connector_set_panel_orientation_with_quirk(&connector->base,6612						       i915->display.vbt.orientation,6613						       fixed_mode->hdisplay,6614						       fixed_mode->vdisplay);6615}6616 6617static void intel_edp_backlight_setup(struct intel_dp *intel_dp,6618				      struct intel_connector *connector)6619{6620	struct drm_i915_private *i915 = dp_to_i915(intel_dp);6621	enum pipe pipe = INVALID_PIPE;6622 6623	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {6624		/*6625		 * Figure out the current pipe for the initial backlight setup.6626		 * If the current pipe isn't valid, try the PPS pipe, and if that6627		 * fails just assume pipe A.6628		 */6629		pipe = vlv_active_pipe(intel_dp);6630 6631		if (pipe != PIPE_A && pipe != PIPE_B)6632			pipe = intel_dp->pps.pps_pipe;6633 6634		if (pipe != PIPE_A && pipe != PIPE_B)6635			pipe = PIPE_A;6636	}6637 6638	intel_backlight_setup(connector, pipe);6639}6640 6641static bool intel_edp_init_connector(struct intel_dp *intel_dp,6642				     struct intel_connector *intel_connector)6643{6644	struct intel_display *display = to_intel_display(intel_dp);6645	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);6646	struct drm_connector *connector = &intel_connector->base;6647	struct drm_display_mode *fixed_mode;6648	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;6649	bool has_dpcd;6650	const struct drm_edid *drm_edid;6651 6652	if (!intel_dp_is_edp(intel_dp))6653		return true;6654 6655	/*6656	 * On IBX/CPT we may get here with LVDS already registered. Since the6657	 * driver uses the only internal power sequencer available for both6658	 * eDP and LVDS bail out early in this case to prevent interfering6659	 * with an already powered-on LVDS power sequencer.6660	 */6661	if (intel_get_lvds_encoder(dev_priv)) {6662		drm_WARN_ON(&dev_priv->drm,6663			    !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));6664		drm_info(&dev_priv->drm,6665			 "LVDS was detected, not registering eDP\n");6666 6667		return false;6668	}6669 6670	intel_bios_init_panel_early(display, &intel_connector->panel,6671				    encoder->devdata);6672 6673	if (!intel_pps_init(intel_dp)) {6674		drm_info(&dev_priv->drm,6675			 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",6676			 encoder->base.base.id, encoder->base.name);6677		/*6678		 * The BIOS may have still enabled VDD on the PPS even6679		 * though it's unusable. Make sure we turn it back off6680		 * and to release the power domain references/etc.6681		 */6682		goto out_vdd_off;6683	}6684 6685	/*6686	 * Enable HPD sense for live status check.6687	 * intel_hpd_irq_setup() will turn it off again6688	 * if it's no longer needed later.6689	 *6690	 * The DPCD probe below will make sure VDD is on.6691	 */6692	intel_hpd_enable_detection(encoder);6693 6694	intel_alpm_init_dpcd(intel_dp);6695 6696	/* Cache DPCD and EDID for edp. */6697	has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);6698 6699	if (!has_dpcd) {6700		/* if this fails, presume the device is a ghost */6701		drm_info(&dev_priv->drm,6702			 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",6703			 encoder->base.base.id, encoder->base.name);6704		goto out_vdd_off;6705	}6706 6707	/*6708	 * VBT and straps are liars. Also check HPD as that seems6709	 * to be the most reliable piece of information available.6710	 *6711	 * ... expect on devices that forgot to hook HPD up for eDP6712	 * (eg. Acer Chromebook C710), so we'll check it only if multiple6713	 * ports are attempting to use the same AUX CH, according to VBT.6714	 */6715	if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {6716		/*6717		 * If this fails, presume the DPCD answer came6718		 * from some other port using the same AUX CH.6719		 *6720		 * FIXME maybe cleaner to check this before the6721		 * DPCD read? Would need sort out the VDD handling...6722		 */6723		if (!intel_digital_port_connected(encoder)) {6724			drm_info(&dev_priv->drm,6725				 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",6726				 encoder->base.base.id, encoder->base.name);6727			goto out_vdd_off;6728		}6729 6730		/*6731		 * Unfortunately even the HPD based detection fails on6732		 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall6733		 * back to checking for a VGA branch device. Only do this6734		 * on known affected platforms to minimize false positives.6735		 */6736		if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&6737		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==6738		    DP_DWN_STRM_PORT_TYPE_ANALOG) {6739			drm_info(&dev_priv->drm,6740				 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",6741				 encoder->base.base.id, encoder->base.name);6742			goto out_vdd_off;6743		}6744	}6745 6746	mutex_lock(&dev_priv->drm.mode_config.mutex);6747	drm_edid = drm_edid_read_ddc(connector, connector->ddc);6748	if (!drm_edid) {6749		/* Fallback to EDID from ACPI OpRegion, if any */6750		drm_edid = intel_opregion_get_edid(intel_connector);6751		if (drm_edid)6752			drm_dbg_kms(&dev_priv->drm,6753				    "[CONNECTOR:%d:%s] Using OpRegion EDID\n",6754				    connector->base.id, connector->name);6755	}6756	if (drm_edid) {6757		if (drm_edid_connector_update(connector, drm_edid) ||6758		    !drm_edid_connector_add_modes(connector)) {6759			drm_edid_connector_update(connector, NULL);6760			drm_edid_free(drm_edid);6761			drm_edid = ERR_PTR(-EINVAL);6762		}6763	} else {6764		drm_edid = ERR_PTR(-ENOENT);6765	}6766 6767	intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata,6768				   IS_ERR(drm_edid) ? NULL : drm_edid);6769 6770	intel_panel_add_edid_fixed_modes(intel_connector, true);6771 6772	/* MSO requires information from the EDID */6773	intel_edp_mso_init(intel_dp);6774 6775	/* multiply the mode clock and horizontal timings for MSO */6776	list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)6777		intel_edp_mso_mode_fixup(intel_connector, fixed_mode);6778 6779	/* fallback to VBT if available for eDP */6780	if (!intel_panel_preferred_fixed_mode(intel_connector))6781		intel_panel_add_vbt_lfp_fixed_mode(intel_connector);6782 6783	mutex_unlock(&dev_priv->drm.mode_config.mutex);6784 6785	if (!intel_panel_preferred_fixed_mode(intel_connector)) {6786		drm_info(&dev_priv->drm,6787			 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",6788			 encoder->base.base.id, encoder->base.name);6789		goto out_vdd_off;6790	}6791 6792	intel_panel_init(intel_connector, drm_edid);6793 6794	intel_edp_backlight_setup(intel_dp, intel_connector);6795 6796	intel_edp_add_properties(intel_dp);6797 6798	intel_pps_init_late(intel_dp);6799 6800	return true;6801 6802out_vdd_off:6803	intel_pps_vdd_off_sync(intel_dp);6804 6805	return false;6806}6807 6808static void intel_dp_modeset_retry_work_fn(struct work_struct *work)6809{6810	struct intel_connector *intel_connector;6811	struct drm_connector *connector;6812 6813	intel_connector = container_of(work, typeof(*intel_connector),6814				       modeset_retry_work);6815	connector = &intel_connector->base;6816	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,6817		    connector->name);6818 6819	/* Grab the locks before changing connector property*/6820	mutex_lock(&connector->dev->mode_config.mutex);6821	/* Set connector link status to BAD and send a Uevent to notify6822	 * userspace to do a modeset.6823	 */6824	drm_connector_set_link_status_property(connector,6825					       DRM_MODE_LINK_STATUS_BAD);6826	mutex_unlock(&connector->dev->mode_config.mutex);6827	/* Send Hotplug uevent so userspace can reprobe */6828	drm_kms_helper_connector_hotplug_event(connector);6829 6830	drm_connector_put(connector);6831}6832 6833void intel_dp_init_modeset_retry_work(struct intel_connector *connector)6834{6835	INIT_WORK(&connector->modeset_retry_work,6836		  intel_dp_modeset_retry_work_fn);6837}6838 6839bool6840intel_dp_init_connector(struct intel_digital_port *dig_port,6841			struct intel_connector *intel_connector)6842{6843	struct drm_connector *connector = &intel_connector->base;6844	struct intel_dp *intel_dp = &dig_port->dp;6845	struct intel_encoder *intel_encoder = &dig_port->base;6846	struct drm_device *dev = intel_encoder->base.dev;6847	struct drm_i915_private *dev_priv = to_i915(dev);6848	enum port port = intel_encoder->port;6849	int type;6850 6851	/* Initialize the work for modeset in case of link train failure */6852	intel_dp_init_modeset_retry_work(intel_connector);6853 6854	if (drm_WARN(dev, dig_port->max_lanes < 1,6855		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",6856		     dig_port->max_lanes, intel_encoder->base.base.id,6857		     intel_encoder->base.name))6858		return false;6859 6860	intel_dp->reset_link_params = true;6861	intel_dp->pps.pps_pipe = INVALID_PIPE;6862	intel_dp->pps.active_pipe = INVALID_PIPE;6863 6864	/* Preserve the current hw state. */6865	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);6866	intel_dp->attached_connector = intel_connector;6867 6868	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {6869		/*6870		 * Currently we don't support eDP on TypeC ports, although in6871		 * theory it could work on TypeC legacy ports.6872		 */6873		drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder));6874		type = DRM_MODE_CONNECTOR_eDP;6875		intel_encoder->type = INTEL_OUTPUT_EDP;6876 6877		/* eDP only on port B and/or C on vlv/chv */6878		if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||6879				      IS_CHERRYVIEW(dev_priv)) &&6880				port != PORT_B && port != PORT_C))6881			return false;6882	} else {6883		type = DRM_MODE_CONNECTOR_DisplayPort;6884	}6885 6886	intel_dp_set_default_sink_rates(intel_dp);6887	intel_dp_set_default_max_sink_lane_count(intel_dp);6888 6889	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))6890		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);6891 6892	intel_dp_aux_init(intel_dp);6893	intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;6894 6895	drm_dbg_kms(&dev_priv->drm,6896		    "Adding %s connector on [ENCODER:%d:%s]\n",6897		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",6898		    intel_encoder->base.base.id, intel_encoder->base.name);6899 6900	drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,6901				    type, &intel_dp->aux.ddc);6902	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);6903 6904	if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)6905		connector->interlace_allowed = true;6906 6907	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;6908	intel_connector->base.polled = intel_connector->polled;6909 6910	intel_connector_attach_encoder(intel_connector, intel_encoder);6911 6912	if (HAS_DDI(dev_priv))6913		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;6914	else6915		intel_connector->get_hw_state = intel_connector_get_hw_state;6916	intel_connector->sync_state = intel_dp_connector_sync_state;6917 6918	if (!intel_edp_init_connector(intel_dp, intel_connector)) {6919		intel_dp_aux_fini(intel_dp);6920		goto fail;6921	}6922 6923	intel_dp_set_source_rates(intel_dp);6924	intel_dp_set_common_rates(intel_dp);6925	intel_dp_reset_link_params(intel_dp);6926 6927	/* init MST on ports that can support it */6928	intel_dp_mst_encoder_init(dig_port,6929				  intel_connector->base.base.id);6930 6931	intel_dp_add_properties(intel_dp, connector);6932 6933	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {6934		int ret = intel_dp_hdcp_init(dig_port, intel_connector);6935		if (ret)6936			drm_dbg_kms(&dev_priv->drm,6937				    "HDCP init failed, skipping.\n");6938	}6939 6940	intel_dp->frl.is_trained = false;6941	intel_dp->frl.trained_rate_gbps = 0;6942 6943	intel_psr_init(intel_dp);6944 6945	return true;6946 6947fail:6948	intel_display_power_flush_work(dev_priv);6949	drm_connector_cleanup(connector);6950 6951	return false;6952}6953 6954void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)6955{6956	struct intel_encoder *encoder;6957 6958	if (!HAS_DISPLAY(dev_priv))6959		return;6960 6961	for_each_intel_encoder(&dev_priv->drm, encoder) {6962		struct intel_dp *intel_dp;6963 6964		if (encoder->type != INTEL_OUTPUT_DDI)6965			continue;6966 6967		intel_dp = enc_to_intel_dp(encoder);6968 6969		if (!intel_dp_mst_source_support(intel_dp))6970			continue;6971 6972		if (intel_dp->is_mst)6973			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);6974	}6975}6976 6977void intel_dp_mst_resume(struct drm_i915_private *dev_priv)6978{6979	struct intel_encoder *encoder;6980 6981	if (!HAS_DISPLAY(dev_priv))6982		return;6983 6984	for_each_intel_encoder(&dev_priv->drm, encoder) {6985		struct intel_dp *intel_dp;6986		int ret;6987 6988		if (encoder->type != INTEL_OUTPUT_DDI)6989			continue;6990 6991		intel_dp = enc_to_intel_dp(encoder);6992 6993		if (!intel_dp_mst_source_support(intel_dp))6994			continue;6995 6996		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,6997						     true);6998		if (ret) {6999			intel_dp->is_mst = false;7000			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,7001							false);7002		}7003	}7004}7005