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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2019 Intel Corporation4 */5 6#ifndef __INTEL_DP_H__7#define __INTEL_DP_H__8 9#include <linux/types.h>10 11enum intel_output_format;12enum pipe;13enum port;14struct drm_connector_state;15struct drm_encoder;16struct drm_i915_private;17struct drm_modeset_acquire_ctx;18struct drm_dp_vsc_sdp;19struct intel_atomic_state;20struct intel_connector;21struct intel_crtc_state;22struct intel_digital_port;23struct intel_dp;24struct intel_encoder;25 26struct link_config_limits {27 int min_rate, max_rate;28 int min_lane_count, max_lane_count;29 struct {30 /* Uncompressed DSC input or link output bpp in 1 bpp units */31 int min_bpp, max_bpp;32 } pipe;33 struct {34 /* Compressed or uncompressed link output bpp in 1/16 bpp units */35 int min_bpp_x16, max_bpp_x16;36 } link;37};38 39void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);40void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,41 struct intel_crtc_state *pipe_config,42 struct link_config_limits *limits);43bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,44 const struct drm_connector_state *conn_state);45int intel_dp_min_bpp(enum intel_output_format output_format);46void intel_dp_init_modeset_retry_work(struct intel_connector *connector);47void48intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,49 struct intel_encoder *encoder,50 const struct intel_crtc_state *crtc_state);51bool intel_dp_init_connector(struct intel_digital_port *dig_port,52 struct intel_connector *intel_connector);53void intel_dp_connector_sync_state(struct intel_connector *connector,54 const struct intel_crtc_state *crtc_state);55void intel_dp_set_link_params(struct intel_dp *intel_dp,56 int link_rate, int lane_count);57int intel_dp_get_active_pipes(struct intel_dp *intel_dp,58 struct drm_modeset_acquire_ctx *ctx,59 u8 *pipe_mask);60void intel_dp_link_check(struct intel_encoder *encoder);61void intel_dp_check_link_state(struct intel_dp *intel_dp);62void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);63void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,64 const struct intel_crtc_state *crtc_state);65void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,66 struct intel_connector *connector,67 const struct intel_crtc_state *new_crtc_state);68void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,69 struct intel_connector *connector,70 const struct intel_crtc_state *old_crtc_state);71void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);72void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);73void intel_dp_encoder_flush_work(struct drm_encoder *encoder);74int intel_dp_compute_config(struct intel_encoder *encoder,75 struct intel_crtc_state *pipe_config,76 struct drm_connector_state *conn_state);77int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,78 struct intel_crtc_state *pipe_config,79 struct drm_connector_state *conn_state,80 struct link_config_limits *limits,81 int timeslots,82 bool recompute_pipe_bpp);83void intel_dp_audio_compute_config(struct intel_encoder *encoder,84 struct intel_crtc_state *pipe_config,85 struct drm_connector_state *conn_state);86bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);87bool intel_dp_is_edp(struct intel_dp *intel_dp);88bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);89bool intel_dp_has_dsc(const struct intel_connector *connector);90int intel_dp_link_symbol_size(int rate);91int intel_dp_link_symbol_clock(int rate);92bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);93enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,94 bool long_hpd);95void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,96 const struct drm_connector_state *conn_state);97void intel_edp_backlight_off(const struct drm_connector_state *conn_state);98void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);99void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);100void intel_dp_mst_resume(struct drm_i915_private *dev_priv);101int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);102int intel_dp_max_link_rate(struct intel_dp *intel_dp);103int intel_dp_max_lane_count(struct intel_dp *intel_dp);104int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);105int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);106int intel_dp_max_common_rate(struct intel_dp *intel_dp);107int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);108int intel_dp_common_rate(struct intel_dp *intel_dp, int index);109int intel_dp_rate_index(const int *rates, int len, int rate);110int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);111void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);112void intel_dp_update_sink_caps(struct intel_dp *intel_dp);113void intel_dp_reset_link_params(struct intel_dp *intel_dp);114 115void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,116 u8 *link_bw, u8 *rate_select);117bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);118bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);119 120bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);121int intel_dp_link_required(int pixel_clock, int bpp);122int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,123 int bw_overhead);124int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,125 int max_dprx_rate, int max_dprx_lanes);126bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915, bool use_joiner);127bool intel_dp_has_joiner(struct intel_dp *intel_dp);128bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,129 const struct drm_connector_state *conn_state);130void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,131 const struct intel_crtc_state *crtc_state,132 const struct drm_connector_state *conn_state);133void intel_read_dp_sdp(struct intel_encoder *encoder,134 struct intel_crtc_state *crtc_state,135 unsigned int type);136void intel_digital_port_lock(struct intel_encoder *encoder);137void intel_digital_port_unlock(struct intel_encoder *encoder);138bool intel_digital_port_connected(struct intel_encoder *encoder);139bool intel_digital_port_connected_locked(struct intel_encoder *encoder);140int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,141 u8 dsc_max_bpc);142u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,143 u32 link_clock, u32 lane_count,144 u32 mode_clock, u32 mode_hdisplay,145 bool bigjoiner,146 enum intel_output_format output_format,147 u32 pipe_bpp,148 u32 timeslots);149int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);150int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,151 struct intel_crtc_state *pipe_config,152 int bpc);153u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,154 int mode_clock, int mode_hdisplay,155 bool bigjoiner);156bool intel_dp_need_joiner(struct intel_dp *intel_dp,157 struct intel_connector *connector,158 int hdisplay, int clock);159 160static inline unsigned int intel_dp_unused_lane_mask(int lane_count)161{162 return ~((1 << lane_count) - 1) & 0xf;163}164 165bool intel_dp_supports_fec(struct intel_dp *intel_dp,166 const struct intel_connector *connector,167 const struct intel_crtc_state *pipe_config);168u32 intel_dp_mode_to_fec_clock(u32 mode_clock);169int intel_dp_bw_fec_overhead(bool fec_enabled);170 171bool intel_dp_supports_fec(struct intel_dp *intel_dp,172 const struct intel_connector *connector,173 const struct intel_crtc_state *pipe_config);174 175bool intel_dp_supports_dsc(const struct intel_connector *connector,176 const struct intel_crtc_state *crtc_state);177 178u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);179 180void intel_ddi_update_pipe(struct intel_atomic_state *state,181 struct intel_encoder *encoder,182 const struct intel_crtc_state *crtc_state,183 const struct drm_connector_state *conn_state);184 185bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,186 struct intel_crtc_state *crtc_state);187void intel_dp_sync_state(struct intel_encoder *encoder,188 const struct intel_crtc_state *crtc_state);189 190void intel_dp_check_frl_training(struct intel_dp *intel_dp);191void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,192 const struct intel_crtc_state *crtc_state);193void intel_dp_phy_test(struct intel_encoder *encoder);194 195void intel_dp_wait_source_oui(struct intel_dp *intel_dp);196int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);197 198bool199intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,200 const struct intel_crtc_state *crtc_state,201 bool dsc,202 struct link_config_limits *limits);203 204void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);205bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);206 207#endif /* __INTEL_DP_H__ */208