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1/*2 * Copyright © 2008 Intel Corporation3 * 2014 Red Hat Inc.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice (including the next13 * paragraph) shall be included in all copies or substantial portions of the14 * Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS22 * IN THE SOFTWARE.23 *24 */25 26#include <drm/drm_atomic.h>27#include <drm/drm_atomic_helper.h>28#include <drm/drm_edid.h>29#include <drm/drm_fixed.h>30#include <drm/drm_probe_helper.h>31 32#include "i915_drv.h"33#include "i915_reg.h"34#include "intel_atomic.h"35#include "intel_audio.h"36#include "intel_connector.h"37#include "intel_crtc.h"38#include "intel_ddi.h"39#include "intel_de.h"40#include "intel_display_driver.h"41#include "intel_display_types.h"42#include "intel_dp.h"43#include "intel_dp_hdcp.h"44#include "intel_dp_mst.h"45#include "intel_dp_tunnel.h"46#include "intel_dp_link_training.h"47#include "intel_dpio_phy.h"48#include "intel_hdcp.h"49#include "intel_hotplug.h"50#include "intel_link_bw.h"51#include "intel_psr.h"52#include "intel_vdsc.h"53#include "skl_scaler.h"54 55static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,56 bool dsc)57{58 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);59 const struct drm_display_mode *adjusted_mode =60 &crtc_state->hw.adjusted_mode;61 62 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc)63 return INT_MAX;64 65 /*66 * DSC->DPT interface width:67 * ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used)68 * LNL+: 144 bits (not a bottleneck in any config)69 *70 * Bspec/49259 suggests that the FEC overhead needs to be71 * applied here, though HW people claim that neither this FEC72 * or any other overhead is applicable here (that is the actual73 * available_bw is just symbol_clock * 72). However based on74 * testing on MTL-P the75 * - DELL U3224KBA display76 * - Unigraf UCD-500 CTS test sink77 * devices the78 * - 5120x2880/995.59Mhz79 * - 6016x3384/1357.23Mhz80 * - 6144x3456/1413.39Mhz81 * modes (all the ones having a DPT limit on the above devices),82 * both the channel coding efficiency and an additional 3%83 * overhead needs to be accounted for.84 */85 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,86 drm_dp_bw_channel_coding_efficiency(true)),87 mul_u32_u32(adjusted_mode->crtc_clock, 1030000));88}89 90static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,91 const struct intel_connector *connector,92 bool ssc, int dsc_slice_count, int bpp_x16)93{94 const struct drm_display_mode *adjusted_mode =95 &crtc_state->hw.adjusted_mode;96 unsigned long flags = DRM_DP_BW_OVERHEAD_MST;97 int overhead;98 99 flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;100 flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;101 flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;102 103 if (dsc_slice_count)104 flags |= DRM_DP_BW_OVERHEAD_DSC;105 106 overhead = drm_dp_bw_overhead(crtc_state->lane_count,107 adjusted_mode->hdisplay,108 dsc_slice_count,109 bpp_x16,110 flags);111 112 /*113 * TODO: clarify whether a minimum required by the fixed FEC overhead114 * in the bspec audio programming sequence is required here.115 */116 return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));117}118 119static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,120 const struct intel_connector *connector,121 int overhead,122 int bpp_x16,123 struct intel_link_m_n *m_n)124{125 const struct drm_display_mode *adjusted_mode =126 &crtc_state->hw.adjusted_mode;127 128 /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */129 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,130 adjusted_mode->crtc_clock,131 crtc_state->port_clock,132 overhead,133 m_n);134 135 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);136}137 138static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)139{140 int effective_data_rate =141 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);142 143 /*144 * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted145 * to calculate PBN with the BW overhead passed to it.146 */147 return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);148}149 150static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connector,151 const struct intel_crtc_state *crtc_state)152{153 const struct drm_display_mode *adjusted_mode =154 &crtc_state->hw.adjusted_mode;155 int num_joined_pipes = crtc_state->joiner_pipes;156 157 return intel_dp_dsc_get_slice_count(connector,158 adjusted_mode->clock,159 adjusted_mode->hdisplay,160 num_joined_pipes);161}162 163static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,164 struct intel_crtc_state *crtc_state,165 int max_bpp,166 int min_bpp,167 struct link_config_limits *limits,168 struct drm_connector_state *conn_state,169 int step,170 bool dsc)171{172 struct drm_atomic_state *state = crtc_state->uapi.state;173 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);174 struct intel_dp *intel_dp = &intel_mst->primary->dp;175 struct drm_dp_mst_topology_state *mst_state;176 struct intel_connector *connector =177 to_intel_connector(conn_state->connector);178 struct drm_i915_private *i915 = to_i915(connector->base.dev);179 const struct drm_display_mode *adjusted_mode =180 &crtc_state->hw.adjusted_mode;181 int bpp, slots = -EINVAL;182 int dsc_slice_count = 0;183 int max_dpt_bpp;184 int ret = 0;185 186 mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);187 if (IS_ERR(mst_state))188 return PTR_ERR(mst_state);189 190 crtc_state->lane_count = limits->max_lane_count;191 crtc_state->port_clock = limits->max_rate;192 193 if (dsc) {194 if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))195 return -EINVAL;196 197 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);198 }199 200 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,201 crtc_state->port_clock,202 crtc_state->lane_count);203 204 max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);205 if (max_bpp > max_dpt_bpp) {206 drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n",207 max_bpp, max_dpt_bpp);208 max_bpp = max_dpt_bpp;209 }210 211 drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",212 min_bpp, max_bpp);213 214 if (dsc) {215 dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state);216 if (!dsc_slice_count) {217 drm_dbg_kms(&i915->drm, "Can't get valid DSC slice count\n");218 219 return -ENOSPC;220 }221 }222 223 for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {224 int local_bw_overhead;225 int remote_bw_overhead;226 int link_bpp_x16;227 int remote_tu;228 fixed20_12 pbn;229 230 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);231 232 link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :233 intel_dp_output_bpp(crtc_state->output_format, bpp));234 235 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,236 false, dsc_slice_count, link_bpp_x16);237 remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,238 true, dsc_slice_count, link_bpp_x16);239 240 intel_dp_mst_compute_m_n(crtc_state, connector,241 local_bw_overhead,242 link_bpp_x16,243 &crtc_state->dp_m_n);244 245 /*246 * The TU size programmed to the HW determines which slots in247 * an MTP frame are used for this stream, which needs to match248 * the payload size programmed to the first downstream branch249 * device's payload table.250 *251 * Note that atm the payload's PBN value DRM core sends via252 * the ALLOCATE_PAYLOAD side-band message matches the payload253 * size (which it calculates from the PBN value) it programs254 * to the first branch device's payload table. The allocation255 * in the payload table could be reduced though (to256 * crtc_state->dp_m_n.tu), provided that the driver doesn't257 * enable SSC on the corresponding link.258 */259 pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,260 link_bpp_x16,261 remote_bw_overhead));262 remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);263 264 /*265 * Aligning the TUs ensures that symbols consisting of multiple266 * (4) symbol cycles don't get split between two consecutive267 * MTPs, as required by Bspec.268 * TODO: remove the alignment restriction for 128b/132b links269 * on some platforms, where Bspec allows this.270 */271 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);272 273 /*274 * Also align PBNs accordingly, since MST core will derive its275 * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().276 * The above comment about the difference between the PBN277 * allocated for the whole path and the TUs allocated for the278 * first branch device's link also applies here.279 */280 pbn.full = remote_tu * mst_state->pbn_div.full;281 crtc_state->pbn = dfixed_trunc(pbn);282 283 drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu);284 crtc_state->dp_m_n.tu = remote_tu;285 286 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,287 connector->port,288 crtc_state->pbn);289 if (slots == -EDEADLK)290 return slots;291 292 if (slots >= 0) {293 drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu);294 295 break;296 }297 }298 299 /* We failed to find a proper bpp/timeslots, return error */300 if (ret)301 slots = ret;302 303 if (slots < 0) {304 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",305 slots);306 } else {307 if (!dsc)308 crtc_state->pipe_bpp = bpp;309 else310 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);311 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);312 }313 314 return slots;315}316 317static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,318 struct intel_crtc_state *crtc_state,319 struct drm_connector_state *conn_state,320 struct link_config_limits *limits)321{322 int slots = -EINVAL;323 324 /*325 * FIXME: allocate the BW according to link_bpp, which in the case of326 * YUV420 is only half of the pipe bpp value.327 */328 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,329 fxp_q4_to_int(limits->link.max_bpp_x16),330 fxp_q4_to_int(limits->link.min_bpp_x16),331 limits,332 conn_state, 2 * 3, false);333 334 if (slots < 0)335 return slots;336 337 return 0;338}339 340static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,341 struct intel_crtc_state *crtc_state,342 struct drm_connector_state *conn_state,343 struct link_config_limits *limits)344{345 struct intel_connector *connector =346 to_intel_connector(conn_state->connector);347 struct drm_i915_private *i915 = to_i915(connector->base.dev);348 int slots = -EINVAL;349 int i, num_bpc;350 u8 dsc_bpc[3] = {};351 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;352 u8 dsc_max_bpc;353 int min_compressed_bpp, max_compressed_bpp;354 355 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */356 if (DISPLAY_VER(i915) >= 12)357 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);358 else359 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);360 361 max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);362 min_bpp = limits->pipe.min_bpp;363 364 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,365 dsc_bpc);366 367 drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",368 min_bpp, max_bpp);369 370 sink_max_bpp = dsc_bpc[0] * 3;371 sink_min_bpp = sink_max_bpp;372 373 for (i = 1; i < num_bpc; i++) {374 if (sink_min_bpp > dsc_bpc[i] * 3)375 sink_min_bpp = dsc_bpc[i] * 3;376 if (sink_max_bpp < dsc_bpc[i] * 3)377 sink_max_bpp = dsc_bpc[i] * 3;378 }379 380 drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",381 sink_min_bpp, sink_max_bpp);382 383 if (min_bpp < sink_min_bpp)384 min_bpp = sink_min_bpp;385 386 if (max_bpp > sink_max_bpp)387 max_bpp = sink_max_bpp;388 389 crtc_state->pipe_bpp = max_bpp;390 391 max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,392 crtc_state,393 max_bpp / 3);394 max_compressed_bpp = min(max_compressed_bpp,395 fxp_q4_to_int(limits->link.max_bpp_x16));396 397 min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);398 min_compressed_bpp = max(min_compressed_bpp,399 fxp_q4_to_int_roundup(limits->link.min_bpp_x16));400 401 drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",402 min_compressed_bpp, max_compressed_bpp);403 404 /* Align compressed bpps according to our own constraints */405 max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,406 crtc_state->pipe_bpp);407 min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,408 crtc_state->pipe_bpp);409 410 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,411 min_compressed_bpp, limits,412 conn_state, 1, true);413 414 if (slots < 0)415 return slots;416 417 return 0;418}419static int intel_dp_mst_update_slots(struct intel_encoder *encoder,420 struct intel_crtc_state *crtc_state,421 struct drm_connector_state *conn_state)422{423 struct drm_i915_private *i915 = to_i915(encoder->base.dev);424 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);425 struct intel_dp *intel_dp = &intel_mst->primary->dp;426 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;427 struct drm_dp_mst_topology_state *topology_state;428 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?429 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;430 431 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);432 if (IS_ERR(topology_state)) {433 drm_dbg_kms(&i915->drm, "slot update failed\n");434 return PTR_ERR(topology_state);435 }436 437 drm_dp_mst_update_slots(topology_state, link_coding_cap);438 439 return 0;440}441 442static int mode_hblank_period_ns(const struct drm_display_mode *mode)443{444 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,445 NSEC_PER_SEC / 1000),446 mode->crtc_clock);447}448 449static bool450hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,451 const struct intel_crtc_state *crtc_state,452 const struct link_config_limits *limits)453{454 const struct drm_display_mode *adjusted_mode =455 &crtc_state->hw.adjusted_mode;456 bool is_uhbr_sink = connector->mst_port &&457 drm_dp_128b132b_supported(connector->mst_port->dpcd);458 int hblank_limit = is_uhbr_sink ? 500 : 300;459 460 if (!connector->dp.dsc_hblank_expansion_quirk)461 return false;462 463 if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))464 return false;465 466 if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)467 return false;468 469 if (!intel_dp_mst_dsc_get_slice_count(connector, crtc_state))470 return false;471 472 return true;473}474 475static bool476adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,477 const struct intel_crtc_state *crtc_state,478 struct link_config_limits *limits,479 bool dsc)480{481 struct drm_i915_private *i915 = to_i915(connector->base.dev);482 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);483 int min_bpp_x16 = limits->link.min_bpp_x16;484 485 if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))486 return true;487 488 if (!dsc) {489 if (intel_dp_supports_dsc(connector, crtc_state)) {490 drm_dbg_kms(&i915->drm,491 "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",492 crtc->base.base.id, crtc->base.name,493 connector->base.base.id, connector->base.name);494 return false;495 }496 497 drm_dbg_kms(&i915->drm,498 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",499 crtc->base.base.id, crtc->base.name,500 connector->base.base.id, connector->base.name);501 502 if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))503 return false;504 505 limits->link.min_bpp_x16 = fxp_q4_from_int(24);506 507 return true;508 }509 510 drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);511 512 if (limits->max_rate < 540000)513 min_bpp_x16 = fxp_q4_from_int(13);514 else if (limits->max_rate < 810000)515 min_bpp_x16 = fxp_q4_from_int(10);516 517 if (limits->link.min_bpp_x16 >= min_bpp_x16)518 return true;519 520 drm_dbg_kms(&i915->drm,521 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n",522 crtc->base.base.id, crtc->base.name,523 connector->base.base.id, connector->base.name,524 FXP_Q4_ARGS(min_bpp_x16));525 526 if (limits->link.max_bpp_x16 < min_bpp_x16)527 return false;528 529 limits->link.min_bpp_x16 = min_bpp_x16;530 531 return true;532}533 534static bool535intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,536 const struct intel_connector *connector,537 struct intel_crtc_state *crtc_state,538 bool dsc,539 struct link_config_limits *limits)540{541 /*542 * for MST we always configure max link bw - the spec doesn't543 * seem to suggest we should do otherwise.544 */545 limits->min_rate = limits->max_rate =546 intel_dp_max_link_rate(intel_dp);547 548 limits->min_lane_count = limits->max_lane_count =549 intel_dp_max_lane_count(intel_dp);550 551 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);552 /*553 * FIXME: If all the streams can't fit into the link with554 * their current pipe_bpp we should reduce pipe_bpp across555 * the board until things start to fit. Until then we556 * limit to <= 8bpc since that's what was hardcoded for all557 * MST streams previously. This hack should be removed once558 * we have the proper retry logic in place.559 */560 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);561 562 intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);563 564 if (!intel_dp_compute_config_link_bpp_limits(intel_dp,565 crtc_state,566 dsc,567 limits))568 return false;569 570 return adjust_limits_for_dsc_hblank_expansion_quirk(connector,571 crtc_state,572 limits,573 dsc);574}575 576static int intel_dp_mst_compute_config(struct intel_encoder *encoder,577 struct intel_crtc_state *pipe_config,578 struct drm_connector_state *conn_state)579{580 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);581 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);582 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);583 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);584 struct intel_dp *intel_dp = &intel_mst->primary->dp;585 struct intel_connector *connector =586 to_intel_connector(conn_state->connector);587 const struct drm_display_mode *adjusted_mode =588 &pipe_config->hw.adjusted_mode;589 struct link_config_limits limits;590 bool dsc_needed, joiner_needs_dsc;591 int ret = 0;592 593 if (pipe_config->fec_enable &&594 !intel_dp_supports_fec(intel_dp, connector, pipe_config))595 return -EINVAL;596 597 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)598 return -EINVAL;599 600 if (intel_dp_need_joiner(intel_dp, connector,601 adjusted_mode->crtc_hdisplay,602 adjusted_mode->crtc_clock))603 pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);604 605 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;606 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;607 pipe_config->has_pch_encoder = false;608 609 joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, pipe_config->joiner_pipes);610 611 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||612 !intel_dp_mst_compute_config_limits(intel_dp,613 connector,614 pipe_config,615 false,616 &limits);617 618 if (!dsc_needed) {619 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,620 conn_state, &limits);621 622 if (ret == -EDEADLK)623 return ret;624 625 if (ret)626 dsc_needed = true;627 }628 629 /* enable compression if the mode doesn't fit available BW */630 if (dsc_needed) {631 drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",632 str_yes_no(ret), str_yes_no(joiner_needs_dsc),633 str_yes_no(intel_dp->force_dsc_en));634 635 if (!intel_dp_supports_dsc(connector, pipe_config))636 return -EINVAL;637 638 if (!intel_dp_mst_compute_config_limits(intel_dp,639 connector,640 pipe_config,641 true,642 &limits))643 return -EINVAL;644 645 /*646 * FIXME: As bpc is hardcoded to 8, as mentioned above,647 * WARN and ignore the debug flag force_dsc_bpc for now.648 */649 drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");650 /*651 * Try to get at least some timeslots and then see, if652 * we can fit there with DSC.653 */654 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");655 656 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,657 conn_state, &limits);658 if (ret < 0)659 return ret;660 661 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,662 conn_state, &limits,663 pipe_config->dp_m_n.tu, false);664 }665 666 if (ret)667 return ret;668 669 ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);670 if (ret)671 return ret;672 673 pipe_config->limited_color_range =674 intel_dp_limited_color_range(pipe_config, conn_state);675 676 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))677 pipe_config->lane_lat_optim_mask =678 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);679 680 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);681 682 intel_ddi_compute_min_voltage_level(pipe_config);683 684 intel_psr_compute_config(intel_dp, pipe_config, conn_state);685 686 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,687 pipe_config);688}689 690/*691 * Iterate over all connectors and return a mask of692 * all CPU transcoders streaming over the same DP link.693 */694static unsigned int695intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,696 struct intel_dp *mst_port)697{698 struct drm_i915_private *dev_priv = to_i915(state->base.dev);699 const struct intel_digital_connector_state *conn_state;700 struct intel_connector *connector;701 u8 transcoders = 0;702 int i;703 704 if (DISPLAY_VER(dev_priv) < 12)705 return 0;706 707 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {708 const struct intel_crtc_state *crtc_state;709 struct intel_crtc *crtc;710 711 if (connector->mst_port != mst_port || !conn_state->base.crtc)712 continue;713 714 crtc = to_intel_crtc(conn_state->base.crtc);715 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);716 717 if (!crtc_state->hw.active)718 continue;719 720 transcoders |= BIT(crtc_state->cpu_transcoder);721 }722 723 return transcoders;724}725 726static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,727 struct drm_dp_mst_topology_mgr *mst_mgr,728 struct drm_dp_mst_port *parent_port)729{730 const struct intel_digital_connector_state *conn_state;731 struct intel_connector *connector;732 u8 mask = 0;733 int i;734 735 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {736 if (!conn_state->base.crtc)737 continue;738 739 if (&connector->mst_port->mst_mgr != mst_mgr)740 continue;741 742 if (connector->port != parent_port &&743 !drm_dp_mst_port_downstream_of_parent(mst_mgr,744 connector->port,745 parent_port))746 continue;747 748 mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);749 }750 751 return mask;752}753 754static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,755 struct drm_dp_mst_topology_mgr *mst_mgr,756 struct intel_link_bw_limits *limits)757{758 struct drm_i915_private *i915 = to_i915(state->base.dev);759 struct intel_crtc *crtc;760 u8 mst_pipe_mask;761 u8 fec_pipe_mask = 0;762 int ret;763 764 mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);765 766 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {767 struct intel_crtc_state *crtc_state =768 intel_atomic_get_new_crtc_state(state, crtc);769 770 /* Atomic connector check should've added all the MST CRTCs. */771 if (drm_WARN_ON(&i915->drm, !crtc_state))772 return -EINVAL;773 774 if (crtc_state->fec_enable)775 fec_pipe_mask |= BIT(crtc->pipe);776 }777 778 if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)779 return 0;780 781 limits->force_fec_pipes |= mst_pipe_mask;782 783 ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",784 mst_pipe_mask);785 786 return ret ? : -EAGAIN;787}788 789static int intel_dp_mst_check_bw(struct intel_atomic_state *state,790 struct drm_dp_mst_topology_mgr *mst_mgr,791 struct drm_dp_mst_topology_state *mst_state,792 struct intel_link_bw_limits *limits)793{794 struct drm_dp_mst_port *mst_port;795 u8 mst_port_pipes;796 int ret;797 798 ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);799 if (ret != -ENOSPC)800 return ret;801 802 mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);803 804 ret = intel_link_bw_reduce_bpp(state, limits,805 mst_port_pipes, "MST link BW");806 807 return ret ? : -EAGAIN;808}809 810/**811 * intel_dp_mst_atomic_check_link - check all modeset MST link configuration812 * @state: intel atomic state813 * @limits: link BW limits814 *815 * Check the link configuration for all modeset MST outputs. If the816 * configuration is invalid @limits will be updated if possible to817 * reduce the total BW, after which the configuration for all CRTCs in818 * @state must be recomputed with the updated @limits.819 *820 * Returns:821 * - 0 if the confugration is valid822 * - %-EAGAIN, if the configuration is invalid and @limits got updated823 * with fallback values with which the configuration of all CRTCs in824 * @state must be recomputed825 * - Other negative error, if the configuration is invalid without a826 * fallback possibility, or the check failed for another reason827 */828int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,829 struct intel_link_bw_limits *limits)830{831 struct drm_dp_mst_topology_mgr *mgr;832 struct drm_dp_mst_topology_state *mst_state;833 int ret;834 int i;835 836 for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {837 ret = intel_dp_mst_check_fec_change(state, mgr, limits);838 if (ret)839 return ret;840 841 ret = intel_dp_mst_check_bw(state, mgr, mst_state,842 limits);843 if (ret)844 return ret;845 }846 847 return 0;848}849 850static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,851 struct intel_crtc_state *crtc_state,852 struct drm_connector_state *conn_state)853{854 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);855 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);856 struct intel_dp *intel_dp = &intel_mst->primary->dp;857 858 /* lowest numbered transcoder will be designated master */859 crtc_state->mst_master_transcoder =860 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;861 862 return 0;863}864 865/*866 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs867 * that shares the same MST stream as mode changed,868 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do869 * a fastset when possible.870 *871 * On TGL+ this is required since each stream go through a master transcoder,872 * so if the master transcoder needs modeset, all other streams in the873 * topology need a modeset. All platforms need to add the atomic state874 * for all streams in the topology, since a modeset on one may require875 * changing the MST link BW usage of the others, which in turn needs a876 * recomputation of the corresponding CRTC states.877 */878static int879intel_dp_mst_atomic_topology_check(struct intel_connector *connector,880 struct intel_atomic_state *state)881{882 struct drm_i915_private *dev_priv = to_i915(state->base.dev);883 struct drm_connector_list_iter connector_list_iter;884 struct intel_connector *connector_iter;885 int ret = 0;886 887 if (!intel_connector_needs_modeset(state, &connector->base))888 return 0;889 890 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);891 for_each_intel_connector_iter(connector_iter, &connector_list_iter) {892 struct intel_digital_connector_state *conn_iter_state;893 struct intel_crtc_state *crtc_state;894 struct intel_crtc *crtc;895 896 if (connector_iter->mst_port != connector->mst_port ||897 connector_iter == connector)898 continue;899 900 conn_iter_state = intel_atomic_get_digital_connector_state(state,901 connector_iter);902 if (IS_ERR(conn_iter_state)) {903 ret = PTR_ERR(conn_iter_state);904 break;905 }906 907 if (!conn_iter_state->base.crtc)908 continue;909 910 crtc = to_intel_crtc(conn_iter_state->base.crtc);911 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);912 if (IS_ERR(crtc_state)) {913 ret = PTR_ERR(crtc_state);914 break;915 }916 917 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);918 if (ret)919 break;920 crtc_state->uapi.mode_changed = true;921 }922 drm_connector_list_iter_end(&connector_list_iter);923 924 return ret;925}926 927static int928intel_dp_mst_atomic_check(struct drm_connector *connector,929 struct drm_atomic_state *_state)930{931 struct intel_atomic_state *state = to_intel_atomic_state(_state);932 struct intel_connector *intel_connector =933 to_intel_connector(connector);934 int ret;935 936 ret = intel_digital_connector_atomic_check(connector, &state->base);937 if (ret)938 return ret;939 940 ret = intel_dp_mst_atomic_topology_check(intel_connector, state);941 if (ret)942 return ret;943 944 if (intel_connector_needs_modeset(state, connector)) {945 ret = intel_dp_tunnel_atomic_check_state(state,946 intel_connector->mst_port,947 intel_connector);948 if (ret)949 return ret;950 }951 952 return drm_dp_atomic_release_time_slots(&state->base,953 &intel_connector->mst_port->mst_mgr,954 intel_connector->port);955}956 957static void clear_act_sent(struct intel_encoder *encoder,958 const struct intel_crtc_state *crtc_state)959{960 struct drm_i915_private *i915 = to_i915(encoder->base.dev);961 962 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),963 DP_TP_STATUS_ACT_SENT);964}965 966static void wait_for_act_sent(struct intel_encoder *encoder,967 const struct intel_crtc_state *crtc_state)968{969 struct drm_i915_private *i915 = to_i915(encoder->base.dev);970 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);971 struct intel_dp *intel_dp = &intel_mst->primary->dp;972 973 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),974 DP_TP_STATUS_ACT_SENT, 1))975 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");976 977 drm_dp_check_act_status(&intel_dp->mst_mgr);978}979 980static void intel_mst_disable_dp(struct intel_atomic_state *state,981 struct intel_encoder *encoder,982 const struct intel_crtc_state *old_crtc_state,983 const struct drm_connector_state *old_conn_state)984{985 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);986 struct intel_digital_port *dig_port = intel_mst->primary;987 struct intel_dp *intel_dp = &dig_port->dp;988 struct intel_connector *connector =989 to_intel_connector(old_conn_state->connector);990 struct drm_i915_private *i915 = to_i915(connector->base.dev);991 992 drm_dbg_kms(&i915->drm, "active links %d\n",993 intel_dp->active_mst_links);994 995 if (intel_dp->active_mst_links == 1)996 intel_dp->link_trained = false;997 998 intel_hdcp_disable(intel_mst->connector);999 1000 intel_dp_sink_disable_decompression(state, connector, old_crtc_state);1001}1002 1003static void intel_mst_post_disable_dp(struct intel_atomic_state *state,1004 struct intel_encoder *encoder,1005 const struct intel_crtc_state *old_crtc_state,1006 const struct drm_connector_state *old_conn_state)1007{1008 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1009 struct intel_digital_port *dig_port = intel_mst->primary;1010 struct intel_dp *intel_dp = &dig_port->dp;1011 struct intel_connector *connector =1012 to_intel_connector(old_conn_state->connector);1013 struct drm_dp_mst_topology_state *old_mst_state =1014 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);1015 struct drm_dp_mst_topology_state *new_mst_state =1016 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);1017 const struct drm_dp_mst_atomic_payload *old_payload =1018 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);1019 struct drm_dp_mst_atomic_payload *new_payload =1020 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);1021 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);1022 struct intel_crtc *pipe_crtc;1023 bool last_mst_stream;1024 1025 intel_dp->active_mst_links--;1026 last_mst_stream = intel_dp->active_mst_links == 0;1027 drm_WARN_ON(&dev_priv->drm,1028 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&1029 !intel_dp_mst_is_master_trans(old_crtc_state));1030 1031 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,1032 intel_crtc_joined_pipe_mask(old_crtc_state)) {1033 const struct intel_crtc_state *old_pipe_crtc_state =1034 intel_atomic_get_old_crtc_state(state, pipe_crtc);1035 1036 intel_crtc_vblank_off(old_pipe_crtc_state);1037 }1038 1039 intel_disable_transcoder(old_crtc_state);1040 1041 drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);1042 1043 clear_act_sent(encoder, old_crtc_state);1044 1045 intel_de_rmw(dev_priv,1046 TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder),1047 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);1048 1049 wait_for_act_sent(encoder, old_crtc_state);1050 1051 drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,1052 old_payload, new_payload);1053 1054 intel_ddi_disable_transcoder_func(old_crtc_state);1055 1056 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,1057 intel_crtc_joined_pipe_mask(old_crtc_state)) {1058 const struct intel_crtc_state *old_pipe_crtc_state =1059 intel_atomic_get_old_crtc_state(state, pipe_crtc);1060 1061 intel_dsc_disable(old_pipe_crtc_state);1062 1063 if (DISPLAY_VER(dev_priv) >= 9)1064 skl_scaler_disable(old_pipe_crtc_state);1065 else1066 ilk_pfit_disable(old_pipe_crtc_state);1067 }1068 1069 /*1070 * Power down mst path before disabling the port, otherwise we end1071 * up getting interrupts from the sink upon detecting link loss.1072 */1073 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,1074 false);1075 1076 /*1077 * BSpec 4287: disable DIP after the transcoder is disabled and before1078 * the transcoder clock select is set to none.1079 */1080 intel_dp_set_infoframes(&dig_port->base, false,1081 old_crtc_state, NULL);1082 /*1083 * From TGL spec: "If multi-stream slave transcoder: Configure1084 * Transcoder Clock Select to direct no clock to the transcoder"1085 *1086 * From older GENs spec: "Configure Transcoder Clock Select to direct1087 * no clock to the transcoder"1088 */1089 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)1090 intel_ddi_disable_transcoder_clock(old_crtc_state);1091 1092 1093 intel_mst->connector = NULL;1094 if (last_mst_stream)1095 dig_port->base.post_disable(state, &dig_port->base,1096 old_crtc_state, NULL);1097 1098 drm_dbg_kms(&dev_priv->drm, "active links %d\n",1099 intel_dp->active_mst_links);1100}1101 1102static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,1103 struct intel_encoder *encoder,1104 const struct intel_crtc_state *old_crtc_state,1105 const struct drm_connector_state *old_conn_state)1106{1107 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1108 struct intel_digital_port *dig_port = intel_mst->primary;1109 struct intel_dp *intel_dp = &dig_port->dp;1110 1111 if (intel_dp->active_mst_links == 0 &&1112 dig_port->base.post_pll_disable)1113 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);1114}1115 1116static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,1117 struct intel_encoder *encoder,1118 const struct intel_crtc_state *pipe_config,1119 const struct drm_connector_state *conn_state)1120{1121 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1122 struct intel_digital_port *dig_port = intel_mst->primary;1123 struct intel_dp *intel_dp = &dig_port->dp;1124 1125 if (intel_dp->active_mst_links == 0)1126 dig_port->base.pre_pll_enable(state, &dig_port->base,1127 pipe_config, NULL);1128 else1129 /*1130 * The port PLL state needs to get updated for secondary1131 * streams as for the primary stream.1132 */1133 intel_ddi_update_active_dpll(state, &dig_port->base,1134 to_intel_crtc(pipe_config->uapi.crtc));1135}1136 1137static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,1138 int link_rate, int lane_count)1139{1140 return intel_dp->link.mst_probed_rate == link_rate &&1141 intel_dp->link.mst_probed_lane_count == lane_count;1142}1143 1144static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp,1145 int link_rate, int lane_count)1146{1147 intel_dp->link.mst_probed_rate = link_rate;1148 intel_dp->link.mst_probed_lane_count = lane_count;1149}1150 1151static void intel_mst_reprobe_topology(struct intel_dp *intel_dp,1152 const struct intel_crtc_state *crtc_state)1153{1154 if (intel_mst_probed_link_params_valid(intel_dp,1155 crtc_state->port_clock, crtc_state->lane_count))1156 return;1157 1158 drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr);1159 1160 intel_mst_set_probed_link_params(intel_dp,1161 crtc_state->port_clock, crtc_state->lane_count);1162}1163 1164static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,1165 struct intel_encoder *encoder,1166 const struct intel_crtc_state *pipe_config,1167 const struct drm_connector_state *conn_state)1168{1169 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1170 struct intel_digital_port *dig_port = intel_mst->primary;1171 struct intel_dp *intel_dp = &dig_port->dp;1172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1173 struct intel_connector *connector =1174 to_intel_connector(conn_state->connector);1175 struct drm_dp_mst_topology_state *mst_state =1176 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);1177 int ret;1178 bool first_mst_stream;1179 1180 /* MST encoders are bound to a crtc, not to a connector,1181 * force the mapping here for get_hw_state.1182 */1183 connector->encoder = encoder;1184 intel_mst->connector = connector;1185 first_mst_stream = intel_dp->active_mst_links == 0;1186 drm_WARN_ON(&dev_priv->drm,1187 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&1188 !intel_dp_mst_is_master_trans(pipe_config));1189 1190 drm_dbg_kms(&dev_priv->drm, "active links %d\n",1191 intel_dp->active_mst_links);1192 1193 if (first_mst_stream)1194 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);1195 1196 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);1197 1198 intel_dp_sink_enable_decompression(state, connector, pipe_config);1199 1200 if (first_mst_stream) {1201 dig_port->base.pre_enable(state, &dig_port->base,1202 pipe_config, NULL);1203 1204 intel_mst_reprobe_topology(intel_dp, pipe_config);1205 }1206 1207 intel_dp->active_mst_links++;1208 1209 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,1210 drm_atomic_get_mst_payload_state(mst_state, connector->port));1211 if (ret < 0)1212 intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);1213 1214 /*1215 * Before Gen 12 this is not done as part of1216 * dig_port->base.pre_enable() and should be done here. For1217 * Gen 12+ the step in which this should be done is different for the1218 * first MST stream, so it's done on the DDI for the first stream and1219 * here for the following ones.1220 */1221 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)1222 intel_ddi_enable_transcoder_clock(encoder, pipe_config);1223 1224 intel_dsc_dp_pps_write(&dig_port->base, pipe_config);1225 intel_ddi_set_dp_msa(pipe_config, conn_state);1226}1227 1228static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)1229{1230 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);1231 u32 clear = 0;1232 u32 set = 0;1233 1234 if (!IS_ALDERLAKE_P(i915))1235 return;1236 1237 if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))1238 return;1239 1240 /* Wa_14013163432:adlp */1241 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))1242 set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);1243 1244 /* Wa_14014143976:adlp */1245 if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {1246 if (intel_dp_is_uhbr(crtc_state))1247 set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);1248 else if (crtc_state->fec_enable)1249 clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);1250 1251 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))1252 set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);1253 }1254 1255 if (!clear && !set)1256 return;1257 1258 intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);1259}1260 1261static void intel_mst_enable_dp(struct intel_atomic_state *state,1262 struct intel_encoder *encoder,1263 const struct intel_crtc_state *pipe_config,1264 const struct drm_connector_state *conn_state)1265{1266 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1267 struct intel_digital_port *dig_port = intel_mst->primary;1268 struct intel_dp *intel_dp = &dig_port->dp;1269 struct intel_connector *connector = to_intel_connector(conn_state->connector);1270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1271 struct drm_dp_mst_topology_state *mst_state =1272 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);1273 enum transcoder trans = pipe_config->cpu_transcoder;1274 bool first_mst_stream = intel_dp->active_mst_links == 1;1275 struct intel_crtc *pipe_crtc;1276 int ret;1277 1278 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);1279 1280 if (intel_dp_is_uhbr(pipe_config)) {1281 const struct drm_display_mode *adjusted_mode =1282 &pipe_config->hw.adjusted_mode;1283 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);1284 1285 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),1286 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));1287 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),1288 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));1289 }1290 1291 enable_bs_jitter_was(pipe_config);1292 1293 intel_ddi_enable_transcoder_func(encoder, pipe_config);1294 1295 clear_act_sent(encoder, pipe_config);1296 1297 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0,1298 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);1299 1300 drm_dbg_kms(&dev_priv->drm, "active links %d\n",1301 intel_dp->active_mst_links);1302 1303 wait_for_act_sent(encoder, pipe_config);1304 1305 if (first_mst_stream)1306 intel_ddi_wait_for_fec_status(encoder, pipe_config, true);1307 1308 ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr,1309 drm_atomic_get_mst_payload_state(mst_state,1310 connector->port));1311 if (ret < 0)1312 intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);1313 1314 if (DISPLAY_VER(dev_priv) >= 12)1315 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),1316 FECSTALL_DIS_DPTSTREAM_DPTTG,1317 pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);1318 1319 intel_audio_sdp_split_update(pipe_config);1320 1321 intel_enable_transcoder(pipe_config);1322 1323 for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,1324 intel_crtc_joined_pipe_mask(pipe_config)) {1325 const struct intel_crtc_state *pipe_crtc_state =1326 intel_atomic_get_new_crtc_state(state, pipe_crtc);1327 1328 intel_crtc_vblank_on(pipe_crtc_state);1329 }1330 1331 intel_hdcp_enable(state, encoder, pipe_config, conn_state);1332}1333 1334static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,1335 enum pipe *pipe)1336{1337 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1338 *pipe = intel_mst->pipe;1339 if (intel_mst->connector)1340 return true;1341 return false;1342}1343 1344static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,1345 struct intel_crtc_state *pipe_config)1346{1347 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1348 struct intel_digital_port *dig_port = intel_mst->primary;1349 1350 dig_port->base.get_config(&dig_port->base, pipe_config);1351}1352 1353static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,1354 struct intel_crtc_state *crtc_state)1355{1356 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);1357 struct intel_digital_port *dig_port = intel_mst->primary;1358 1359 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);1360}1361 1362static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)1363{1364 struct intel_connector *intel_connector = to_intel_connector(connector);1365 struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);1366 struct intel_dp *intel_dp = intel_connector->mst_port;1367 const struct drm_edid *drm_edid;1368 int ret;1369 1370 if (drm_connector_is_unregistered(connector))1371 return intel_connector_update_modes(connector, NULL);1372 1373 if (!intel_display_driver_check_access(i915))1374 return drm_edid_connector_add_modes(connector);1375 1376 drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);1377 1378 ret = intel_connector_update_modes(connector, drm_edid);1379 1380 drm_edid_free(drm_edid);1381 1382 return ret;1383}1384 1385static int1386intel_dp_mst_connector_late_register(struct drm_connector *connector)1387{1388 struct intel_connector *intel_connector = to_intel_connector(connector);1389 int ret;1390 1391 ret = drm_dp_mst_connector_late_register(connector,1392 intel_connector->port);1393 if (ret < 0)1394 return ret;1395 1396 ret = intel_connector_register(connector);1397 if (ret < 0)1398 drm_dp_mst_connector_early_unregister(connector,1399 intel_connector->port);1400 1401 return ret;1402}1403 1404static void1405intel_dp_mst_connector_early_unregister(struct drm_connector *connector)1406{1407 struct intel_connector *intel_connector = to_intel_connector(connector);1408 1409 intel_connector_unregister(connector);1410 drm_dp_mst_connector_early_unregister(connector,1411 intel_connector->port);1412}1413 1414static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {1415 .fill_modes = drm_helper_probe_single_connector_modes,1416 .atomic_get_property = intel_digital_connector_atomic_get_property,1417 .atomic_set_property = intel_digital_connector_atomic_set_property,1418 .late_register = intel_dp_mst_connector_late_register,1419 .early_unregister = intel_dp_mst_connector_early_unregister,1420 .destroy = intel_connector_destroy,1421 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,1422 .atomic_duplicate_state = intel_digital_connector_duplicate_state,1423};1424 1425static int intel_dp_mst_get_modes(struct drm_connector *connector)1426{1427 return intel_dp_mst_get_ddc_modes(connector);1428}1429 1430static int1431intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,1432 struct drm_display_mode *mode,1433 struct drm_modeset_acquire_ctx *ctx,1434 enum drm_mode_status *status)1435{1436 struct drm_i915_private *dev_priv = to_i915(connector->dev);1437 struct intel_connector *intel_connector = to_intel_connector(connector);1438 struct intel_dp *intel_dp = intel_connector->mst_port;1439 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;1440 struct drm_dp_mst_port *port = intel_connector->port;1441 const int min_bpp = 18;1442 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;1443 int max_rate, mode_rate, max_lanes, max_link_clock;1444 int ret;1445 bool dsc = false, joiner = false;1446 u16 dsc_max_compressed_bpp = 0;1447 u8 dsc_slice_count = 0;1448 int target_clock = mode->clock;1449 1450 if (drm_connector_is_unregistered(connector)) {1451 *status = MODE_ERROR;1452 return 0;1453 }1454 1455 *status = intel_cpu_transcoder_mode_valid(dev_priv, mode);1456 if (*status != MODE_OK)1457 return 0;1458 1459 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {1460 *status = MODE_H_ILLEGAL;1461 return 0;1462 }1463 1464 if (mode->clock < 10000) {1465 *status = MODE_CLOCK_LOW;1466 return 0;1467 }1468 1469 max_link_clock = intel_dp_max_link_rate(intel_dp);1470 max_lanes = intel_dp_max_lane_count(intel_dp);1471 1472 max_rate = intel_dp_max_link_data_rate(intel_dp,1473 max_link_clock, max_lanes);1474 mode_rate = intel_dp_link_required(mode->clock, min_bpp);1475 1476 /*1477 * TODO:1478 * - Also check if compression would allow for the mode1479 * - Calculate the overhead using drm_dp_bw_overhead() /1480 * drm_dp_bw_channel_coding_efficiency(), similarly to the1481 * compute config code, as drm_dp_calc_pbn_mode() doesn't1482 * account with all the overheads.1483 * - Check here and during compute config the BW reported by1484 * DFP_Link_Available_Payload_Bandwidth_Number (or the1485 * corresponding link capabilities of the sink) in case the1486 * stream is uncompressed for it by the last branch device.1487 */1488 if (intel_dp_need_joiner(intel_dp, intel_connector,1489 mode->hdisplay, target_clock)) {1490 joiner = true;1491 max_dotclk *= 2;1492 }1493 1494 ret = drm_modeset_lock(&mgr->base.lock, ctx);1495 if (ret)1496 return ret;1497 1498 if (mode_rate > max_rate || mode->clock > max_dotclk ||1499 drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {1500 *status = MODE_CLOCK_HIGH;1501 return 0;1502 }1503 1504 if (intel_dp_has_dsc(intel_connector)) {1505 /*1506 * TBD pass the connector BPC,1507 * for now U8_MAX so that max BPC on that platform would be picked1508 */1509 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);1510 1511 if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {1512 dsc_max_compressed_bpp =1513 intel_dp_dsc_get_max_compressed_bpp(dev_priv,1514 max_link_clock,1515 max_lanes,1516 target_clock,1517 mode->hdisplay,1518 joiner,1519 INTEL_OUTPUT_FORMAT_RGB,1520 pipe_bpp, 64);1521 dsc_slice_count =1522 intel_dp_dsc_get_slice_count(intel_connector,1523 target_clock,1524 mode->hdisplay,1525 joiner);1526 }1527 1528 dsc = dsc_max_compressed_bpp && dsc_slice_count;1529 }1530 1531 if (intel_dp_joiner_needs_dsc(dev_priv, joiner) && !dsc) {1532 *status = MODE_CLOCK_HIGH;1533 return 0;1534 }1535 1536 if (mode_rate > max_rate && !dsc) {1537 *status = MODE_CLOCK_HIGH;1538 return 0;1539 }1540 1541 *status = intel_mode_valid_max_plane_size(dev_priv, mode, joiner);1542 return 0;1543}1544 1545static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,1546 struct drm_atomic_state *state)1547{1548 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,1549 connector);1550 struct intel_connector *intel_connector = to_intel_connector(connector);1551 struct intel_dp *intel_dp = intel_connector->mst_port;1552 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);1553 1554 return &intel_dp->mst_encoders[crtc->pipe]->base.base;1555}1556 1557static int1558intel_dp_mst_detect(struct drm_connector *connector,1559 struct drm_modeset_acquire_ctx *ctx, bool force)1560{1561 struct drm_i915_private *i915 = to_i915(connector->dev);1562 struct intel_connector *intel_connector = to_intel_connector(connector);1563 struct intel_dp *intel_dp = intel_connector->mst_port;1564 1565 if (!intel_display_device_enabled(i915))1566 return connector_status_disconnected;1567 1568 if (drm_connector_is_unregistered(connector))1569 return connector_status_disconnected;1570 1571 if (!intel_display_driver_check_access(i915))1572 return connector->status;1573 1574 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,1575 intel_connector->port);1576}1577 1578static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {1579 .get_modes = intel_dp_mst_get_modes,1580 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,1581 .atomic_best_encoder = intel_mst_atomic_best_encoder,1582 .atomic_check = intel_dp_mst_atomic_check,1583 .detect_ctx = intel_dp_mst_detect,1584};1585 1586static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)1587{1588 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));1589 1590 drm_encoder_cleanup(encoder);1591 kfree(intel_mst);1592}1593 1594static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {1595 .destroy = intel_dp_mst_encoder_destroy,1596};1597 1598static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)1599{1600 if (intel_attached_encoder(connector) && connector->base.state->crtc) {1601 enum pipe pipe;1602 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))1603 return false;1604 return true;1605 }1606 return false;1607}1608 1609static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,1610 struct drm_connector *connector,1611 const char *pathprop)1612{1613 struct drm_i915_private *i915 = to_i915(connector->dev);1614 1615 drm_object_attach_property(&connector->base,1616 i915->drm.mode_config.path_property, 0);1617 drm_object_attach_property(&connector->base,1618 i915->drm.mode_config.tile_property, 0);1619 1620 intel_attach_force_audio_property(connector);1621 intel_attach_broadcast_rgb_property(connector);1622 1623 /*1624 * Reuse the prop from the SST connector because we're1625 * not allowed to create new props after device registration.1626 */1627 connector->max_bpc_property =1628 intel_dp->attached_connector->base.max_bpc_property;1629 if (connector->max_bpc_property)1630 drm_connector_attach_max_bpc_property(connector, 6, 12);1631 1632 return drm_connector_set_path_property(connector, pathprop);1633}1634 1635static void1636intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,1637 struct intel_connector *connector)1638{1639 u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];1640 1641 if (!connector->dp.dsc_decompression_aux)1642 return;1643 1644 if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)1645 return;1646 1647 intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);1648}1649 1650static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)1651{1652 struct drm_i915_private *i915 = to_i915(connector->base.dev);1653 struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;1654 struct drm_dp_desc desc;1655 u8 dpcd[DP_RECEIVER_CAP_SIZE];1656 1657 if (!aux)1658 return false;1659 1660 /*1661 * A logical port's OUI (at least for affected sinks) is all 0, so1662 * instead of that the parent port's OUI is used for identification.1663 */1664 if (drm_dp_mst_port_is_logical(connector->port)) {1665 aux = drm_dp_mst_aux_for_parent(connector->port);1666 if (!aux)1667 aux = &connector->mst_port->aux;1668 }1669 1670 if (drm_dp_read_dpcd_caps(aux, dpcd) < 0)1671 return false;1672 1673 if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(dpcd)) < 0)1674 return false;1675 1676 if (!drm_dp_has_quirk(&desc,1677 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))1678 return false;1679 1680 /*1681 * UHBR (MST sink) devices requiring this quirk don't advertise the1682 * HBLANK expansion support. Presuming that they perform HBLANK1683 * expansion internally, or are affected by this issue on modes with a1684 * short HBLANK for other reasons.1685 */1686 if (!drm_dp_128b132b_supported(dpcd) &&1687 !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))1688 return false;1689 1690 drm_dbg_kms(&i915->drm,1691 "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",1692 connector->base.base.id, connector->base.name);1693 1694 return true;1695}1696 1697static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,1698 struct drm_dp_mst_port *port,1699 const char *pathprop)1700{1701 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);1702 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);1703 struct drm_device *dev = dig_port->base.base.dev;1704 struct drm_i915_private *dev_priv = to_i915(dev);1705 struct intel_connector *intel_connector;1706 struct drm_connector *connector;1707 enum pipe pipe;1708 int ret;1709 1710 intel_connector = intel_connector_alloc();1711 if (!intel_connector)1712 return NULL;1713 1714 intel_connector->get_hw_state = intel_dp_mst_get_hw_state;1715 intel_connector->sync_state = intel_dp_connector_sync_state;1716 intel_connector->mst_port = intel_dp;1717 intel_connector->port = port;1718 drm_dp_mst_get_port_malloc(port);1719 1720 intel_dp_init_modeset_retry_work(intel_connector);1721 1722 intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);1723 intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);1724 intel_connector->dp.dsc_hblank_expansion_quirk =1725 detect_dsc_hblank_expansion_quirk(intel_connector);1726 1727 connector = &intel_connector->base;1728 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,1729 DRM_MODE_CONNECTOR_DisplayPort);1730 if (ret) {1731 drm_dp_mst_put_port_malloc(port);1732 intel_connector_free(intel_connector);1733 return NULL;1734 }1735 1736 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);1737 1738 for_each_pipe(dev_priv, pipe) {1739 struct drm_encoder *enc =1740 &intel_dp->mst_encoders[pipe]->base.base;1741 1742 ret = drm_connector_attach_encoder(&intel_connector->base, enc);1743 if (ret)1744 goto err;1745 }1746 1747 ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);1748 if (ret)1749 goto err;1750 1751 ret = intel_dp_hdcp_init(dig_port, intel_connector);1752 if (ret)1753 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",1754 connector->name, connector->base.id);1755 1756 return connector;1757 1758err:1759 drm_connector_cleanup(connector);1760 return NULL;1761}1762 1763static void1764intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)1765{1766 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);1767 1768 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));1769}1770 1771static const struct drm_dp_mst_topology_cbs mst_cbs = {1772 .add_connector = intel_dp_add_mst_connector,1773 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,1774};1775 1776static struct intel_dp_mst_encoder *1777intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)1778{1779 struct intel_dp_mst_encoder *intel_mst;1780 struct intel_encoder *intel_encoder;1781 struct drm_device *dev = dig_port->base.base.dev;1782 1783 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);1784 1785 if (!intel_mst)1786 return NULL;1787 1788 intel_mst->pipe = pipe;1789 intel_encoder = &intel_mst->base;1790 intel_mst->primary = dig_port;1791 1792 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,1793 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));1794 1795 intel_encoder->type = INTEL_OUTPUT_DP_MST;1796 intel_encoder->power_domain = dig_port->base.power_domain;1797 intel_encoder->port = dig_port->base.port;1798 intel_encoder->cloneable = 0;1799 /*1800 * This is wrong, but broken userspace uses the intersection1801 * of possible_crtcs of all the encoders of a given connector1802 * to figure out which crtcs can drive said connector. What1803 * should be used instead is the union of possible_crtcs.1804 * To keep such userspace functioning we must misconfigure1805 * this to make sure the intersection is not empty :(1806 */1807 intel_encoder->pipe_mask = ~0;1808 1809 intel_encoder->compute_config = intel_dp_mst_compute_config;1810 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;1811 intel_encoder->disable = intel_mst_disable_dp;1812 intel_encoder->post_disable = intel_mst_post_disable_dp;1813 intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;1814 intel_encoder->update_pipe = intel_ddi_update_pipe;1815 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;1816 intel_encoder->pre_enable = intel_mst_pre_enable_dp;1817 intel_encoder->enable = intel_mst_enable_dp;1818 intel_encoder->audio_enable = intel_audio_codec_enable;1819 intel_encoder->audio_disable = intel_audio_codec_disable;1820 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;1821 intel_encoder->get_config = intel_dp_mst_enc_get_config;1822 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;1823 1824 return intel_mst;1825 1826}1827 1828static bool1829intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)1830{1831 struct intel_dp *intel_dp = &dig_port->dp;1832 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);1833 enum pipe pipe;1834 1835 for_each_pipe(dev_priv, pipe)1836 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);1837 return true;1838}1839 1840int1841intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)1842{1843 return dig_port->dp.active_mst_links;1844}1845 1846int1847intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)1848{1849 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);1850 struct intel_dp *intel_dp = &dig_port->dp;1851 enum port port = dig_port->base.port;1852 int ret;1853 1854 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))1855 return 0;1856 1857 if (DISPLAY_VER(i915) < 12 && port == PORT_A)1858 return 0;1859 1860 if (DISPLAY_VER(i915) < 11 && port == PORT_E)1861 return 0;1862 1863 intel_dp->mst_mgr.cbs = &mst_cbs;1864 1865 /* create encoders */1866 intel_dp_create_fake_mst_encoders(dig_port);1867 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,1868 &intel_dp->aux, 16, 3, conn_base_id);1869 if (ret) {1870 intel_dp->mst_mgr.cbs = NULL;1871 return ret;1872 }1873 1874 return 0;1875}1876 1877bool intel_dp_mst_source_support(struct intel_dp *intel_dp)1878{1879 return intel_dp->mst_mgr.cbs;1880}1881 1882void1883intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)1884{1885 struct intel_dp *intel_dp = &dig_port->dp;1886 1887 if (!intel_dp_mst_source_support(intel_dp))1888 return;1889 1890 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);1891 /* encoders will get killed by normal cleanup */1892 1893 intel_dp->mst_mgr.cbs = NULL;1894}1895 1896bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)1897{1898 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;1899}1900 1901bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)1902{1903 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&1904 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;1905}1906 1907/**1908 * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector1909 * @state: atomic state1910 * @connector: connector to add the state for1911 * @crtc: the CRTC @connector is attached to1912 *1913 * Add the MST topology state for @connector to @state.1914 *1915 * Returns 0 on success, negative error code on failure.1916 */1917static int1918intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,1919 struct intel_connector *connector,1920 struct intel_crtc *crtc)1921{1922 struct drm_dp_mst_topology_state *mst_state;1923 1924 if (!connector->mst_port)1925 return 0;1926 1927 mst_state = drm_atomic_get_mst_topology_state(&state->base,1928 &connector->mst_port->mst_mgr);1929 if (IS_ERR(mst_state))1930 return PTR_ERR(mst_state);1931 1932 mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);1933 1934 return 0;1935}1936 1937/**1938 * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC1939 * @state: atomic state1940 * @crtc: CRTC to add the state for1941 *1942 * Add the MST topology state for @crtc to @state.1943 *1944 * Returns 0 on success, negative error code on failure.1945 */1946int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,1947 struct intel_crtc *crtc)1948{1949 struct drm_connector *_connector;1950 struct drm_connector_state *conn_state;1951 int i;1952 1953 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {1954 struct intel_connector *connector = to_intel_connector(_connector);1955 int ret;1956 1957 if (conn_state->crtc != &crtc->base)1958 continue;1959 1960 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);1961 if (ret)1962 return ret;1963 }1964 1965 return 0;1966}1967 1968static struct intel_connector *1969get_connector_in_state_for_crtc(struct intel_atomic_state *state,1970 const struct intel_crtc *crtc)1971{1972 struct drm_connector_state *old_conn_state;1973 struct drm_connector_state *new_conn_state;1974 struct drm_connector *_connector;1975 int i;1976 1977 for_each_oldnew_connector_in_state(&state->base, _connector,1978 old_conn_state, new_conn_state, i) {1979 struct intel_connector *connector =1980 to_intel_connector(_connector);1981 1982 if (old_conn_state->crtc == &crtc->base ||1983 new_conn_state->crtc == &crtc->base)1984 return connector;1985 }1986 1987 return NULL;1988}1989 1990/**1991 * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC1992 * @state: atomic state1993 * @crtc: CRTC for which to check the modeset requirement1994 *1995 * Check if any change in a MST topology requires a forced modeset on @crtc in1996 * this topology. One such change is enabling/disabling the DSC decompression1997 * state in the first branch device's UFP DPCD as required by one CRTC, while1998 * the other @crtc in the same topology is still active, requiring a full modeset1999 * on @crtc.2000 */2001bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,2002 struct intel_crtc *crtc)2003{2004 const struct intel_connector *crtc_connector;2005 const struct drm_connector_state *conn_state;2006 const struct drm_connector *_connector;2007 int i;2008 2009 if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),2010 INTEL_OUTPUT_DP_MST))2011 return false;2012 2013 crtc_connector = get_connector_in_state_for_crtc(state, crtc);2014 2015 if (!crtc_connector)2016 /* None of the connectors in the topology needs modeset */2017 return false;2018 2019 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {2020 const struct intel_connector *connector =2021 to_intel_connector(_connector);2022 const struct intel_crtc_state *new_crtc_state;2023 const struct intel_crtc_state *old_crtc_state;2024 struct intel_crtc *crtc_iter;2025 2026 if (connector->mst_port != crtc_connector->mst_port ||2027 !conn_state->crtc)2028 continue;2029 2030 crtc_iter = to_intel_crtc(conn_state->crtc);2031 2032 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);2033 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);2034 2035 if (!intel_crtc_needs_modeset(new_crtc_state))2036 continue;2037 2038 if (old_crtc_state->dsc.compression_enable ==2039 new_crtc_state->dsc.compression_enable)2040 continue;2041 /*2042 * Toggling the decompression flag because of this stream in2043 * the first downstream branch device's UFP DPCD may reset the2044 * whole branch device. To avoid the reset while other streams2045 * are also active modeset the whole MST topology in this2046 * case.2047 */2048 if (connector->dp.dsc_decompression_aux ==2049 &connector->mst_port->aux)2050 return true;2051 }2052 2053 return false;2054}2055 2056/**2057 * intel_dp_mst_prepare_probe - Prepare an MST link for topology probing2058 * @intel_dp: DP port object2059 *2060 * Prepare an MST link for topology probing, programming the target2061 * link parameters to DPCD. This step is a requirement of the enumaration2062 * of path resources during probing.2063 */2064void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)2065{2066 int link_rate = intel_dp_max_link_rate(intel_dp);2067 int lane_count = intel_dp_max_lane_count(intel_dp);2068 u8 rate_select;2069 u8 link_bw;2070 2071 if (intel_dp->link_trained)2072 return;2073 2074 if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))2075 return;2076 2077 intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);2078 2079 intel_dp_link_training_set_mode(intel_dp, link_rate, false);2080 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,2081 drm_dp_enhanced_frame_cap(intel_dp->dpcd));2082 2083 intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);2084}2085 2086/*2087 * intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD2088 * @intel_dp: DP port object2089 *2090 * Verify if @intel_dp's MST enabled SW state matches the corresponding DPCD2091 * state. A long HPD pulse - not long enough to be detected as a disconnected2092 * state - could've reset the DPCD state, which requires tearing2093 * down/recreating the MST topology.2094 *2095 * Returns %true if the SW MST enabled and DPCD states match, %false2096 * otherwise.2097 */2098bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)2099{2100 struct intel_display *display = to_intel_display(intel_dp);2101 struct intel_connector *connector = intel_dp->attached_connector;2102 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);2103 struct intel_encoder *encoder = &dig_port->base;2104 int ret;2105 u8 val;2106 2107 if (!intel_dp->is_mst)2108 return true;2109 2110 ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val);2111 2112 /* Adjust the expected register value for SST + SideBand. */2113 if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) {2114 drm_dbg_kms(display->drm,2115 "[CONNECTOR:%d:%s][ENCODER:%d:%s] MST mode got reset, removing topology (ret=%d, ctrl=0x%02x)\n",2116 connector->base.base.id, connector->base.name,2117 encoder->base.base.id, encoder->base.name,2118 ret, val);2119 2120 return false;2121 }2122 2123 return true;2124}2125