1159 lines · c
1/*2 * Copyright © 2014-2016 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER21 * DEALINGS IN THE SOFTWARE.22 */23 24#include "bxt_dpio_phy_regs.h"25#include "i915_reg.h"26#include "intel_ddi.h"27#include "intel_ddi_buf_trans.h"28#include "intel_de.h"29#include "intel_display_power_well.h"30#include "intel_display_types.h"31#include "intel_dp.h"32#include "intel_dpio_phy.h"33#include "vlv_dpio_phy_regs.h"34#include "vlv_sideband.h"35 36/**37 * DOC: DPIO38 *39 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI40 * ports. DPIO is the name given to such a display PHY. These PHYs41 * don't follow the standard programming model using direct MMIO42 * registers, and instead their registers must be accessed trough IOSF43 * sideband. VLV has one such PHY for driving ports B and C, and CHV44 * adds another PHY for driving port D. Each PHY responds to specific45 * IOSF-SB port.46 *47 * Each display PHY is made up of one or two channels. Each channel48 * houses a common lane part which contains the PLL and other common49 * logic. CH0 common lane also contains the IOSF-SB logic for the50 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock51 * must be running when any DPIO registers are accessed.52 *53 * In addition to having their own registers, the PHYs are also54 * controlled through some dedicated signals from the display55 * controller. These include PLL reference clock enable, PLL enable,56 * and CRI clock selection, for example.57 *58 * Eeach channel also has two splines (also called data lanes), and59 * each spline is made up of one Physical Access Coding Sub-Layer60 * (PCS) block and two TX lanes. So each channel has two PCS blocks61 * and four TX lanes. The TX lanes are used as DP lanes or TMDS62 * data/clock pairs depending on the output type.63 *64 * Additionally the PHY also contains an AUX lane with AUX blocks65 * for each channel. This is used for DP AUX communication, but66 * this fact isn't really relevant for the driver since AUX is67 * controlled from the display controller side. No DPIO registers68 * need to be accessed during AUX communication,69 *70 * Generally on VLV/CHV the common lane corresponds to the pipe and71 * the spline (PCS/TX) corresponds to the port.72 *73 * For dual channel PHY (VLV/CHV):74 *75 * pipe A == CMN/PLL/REF CH076 *77 * pipe B == CMN/PLL/REF CH178 *79 * port B == PCS/TX CH080 *81 * port C == PCS/TX CH182 *83 * This is especially important when we cross the streams84 * ie. drive port B with pipe B, or port C with pipe A.85 *86 * For single channel PHY (CHV):87 *88 * pipe C == CMN/PLL/REF CH089 *90 * port D == PCS/TX CH091 *92 * On BXT the entire PHY channel corresponds to the port. That means93 * the PLL is also now associated with the port rather than the pipe,94 * and so the clock needs to be routed to the appropriate transcoder.95 * Port A PLL is directly connected to transcoder EDP and port B/C96 * PLLs can be routed to any transcoder A/B/C.97 *98 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is99 * digital port D (CHV) or port A (BXT). ::100 *101 *102 * Dual channel PHY (VLV/CHV/BXT)103 * ---------------------------------104 * | CH0 | CH1 |105 * | CMN/PLL/REF | CMN/PLL/REF |106 * |---------------|---------------| Display PHY107 * | PCS01 | PCS23 | PCS01 | PCS23 |108 * |-------|-------|-------|-------|109 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|110 * ---------------------------------111 * | DDI0 | DDI1 | DP/HDMI ports112 * ---------------------------------113 *114 * Single channel PHY (CHV/BXT)115 * -----------------116 * | CH0 |117 * | CMN/PLL/REF |118 * |---------------| Display PHY119 * | PCS01 | PCS23 |120 * |-------|-------|121 * |TX0|TX1|TX2|TX3|122 * -----------------123 * | DDI2 | DP/HDMI port124 * -----------------125 */126 127/**128 * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy129 */130struct bxt_dpio_phy_info {131 /**132 * @dual_channel: true if this phy has a second channel.133 */134 bool dual_channel;135 136 /**137 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.138 * Otherwise the GRC value will be copied from the phy indicated by139 * this field.140 */141 enum dpio_phy rcomp_phy;142 143 /**144 * @reset_delay: delay in us to wait before setting the common reset145 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.146 */147 int reset_delay;148 149 /**150 * @pwron_mask: Mask with the appropriate bit set that would cause the151 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.152 */153 u32 pwron_mask;154 155 /**156 * @channel: struct containing per channel information.157 */158 struct {159 /**160 * @channel.port: which port maps to this channel.161 */162 enum port port;163 } channel[2];164};165 166static const struct bxt_dpio_phy_info bxt_dpio_phy_info[] = {167 [DPIO_PHY0] = {168 .dual_channel = true,169 .rcomp_phy = DPIO_PHY1,170 .pwron_mask = BIT(0),171 172 .channel = {173 [DPIO_CH0] = { .port = PORT_B },174 [DPIO_CH1] = { .port = PORT_C },175 }176 },177 [DPIO_PHY1] = {178 .dual_channel = false,179 .rcomp_phy = -1,180 .pwron_mask = BIT(1),181 182 .channel = {183 [DPIO_CH0] = { .port = PORT_A },184 }185 },186};187 188static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = {189 [DPIO_PHY0] = {190 .dual_channel = false,191 .rcomp_phy = DPIO_PHY1,192 .pwron_mask = BIT(0),193 .reset_delay = 20,194 195 .channel = {196 [DPIO_CH0] = { .port = PORT_B },197 }198 },199 [DPIO_PHY1] = {200 .dual_channel = false,201 .rcomp_phy = -1,202 .pwron_mask = BIT(3),203 .reset_delay = 20,204 205 .channel = {206 [DPIO_CH0] = { .port = PORT_A },207 }208 },209 [DPIO_PHY2] = {210 .dual_channel = false,211 .rcomp_phy = DPIO_PHY1,212 .pwron_mask = BIT(1),213 .reset_delay = 20,214 215 .channel = {216 [DPIO_CH0] = { .port = PORT_C },217 }218 },219};220 221static const struct bxt_dpio_phy_info *222bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)223{224 if (IS_GEMINILAKE(dev_priv)) {225 *count = ARRAY_SIZE(glk_dpio_phy_info);226 return glk_dpio_phy_info;227 } else {228 *count = ARRAY_SIZE(bxt_dpio_phy_info);229 return bxt_dpio_phy_info;230 }231}232 233static const struct bxt_dpio_phy_info *234bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)235{236 int count;237 const struct bxt_dpio_phy_info *phy_list =238 bxt_get_phy_list(dev_priv, &count);239 240 return &phy_list[phy];241}242 243void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,244 enum dpio_phy *phy, enum dpio_channel *ch)245{246 const struct bxt_dpio_phy_info *phy_info, *phys;247 int i, count;248 249 phys = bxt_get_phy_list(dev_priv, &count);250 251 for (i = 0; i < count; i++) {252 phy_info = &phys[i];253 254 if (port == phy_info->channel[DPIO_CH0].port) {255 *phy = i;256 *ch = DPIO_CH0;257 return;258 }259 260 if (phy_info->dual_channel &&261 port == phy_info->channel[DPIO_CH1].port) {262 *phy = i;263 *ch = DPIO_CH1;264 return;265 }266 }267 268 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",269 port_name(port));270 *phy = DPIO_PHY0;271 *ch = DPIO_CH0;272}273 274/*275 * Like intel_de_rmw() but reads from a single per-lane register and276 * writes to the group register to write the same value to all the lanes.277 */278static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,279 i915_reg_t reg_single,280 i915_reg_t reg_group,281 u32 clear, u32 set)282{283 u32 old, val;284 285 old = intel_de_read(i915, reg_single);286 val = (old & ~clear) | set;287 intel_de_write(i915, reg_group, val);288 289 return old;290}291 292void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,293 const struct intel_crtc_state *crtc_state)294{295 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);296 const struct intel_ddi_buf_trans *trans;297 enum dpio_channel ch;298 enum dpio_phy phy;299 int lane, n_entries;300 301 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);302 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))303 return;304 305 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);306 307 /*308 * While we write to the group register to program all lanes at once we309 * can read only lane registers and we pick lanes 0/1 for that.310 */311 bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),312 BXT_PORT_PCS_DW10_GRP(phy, ch),313 TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);314 315 for (lane = 0; lane < crtc_state->lane_count; lane++) {316 int level = intel_ddi_level(encoder, crtc_state, lane);317 318 intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),319 MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,320 MARGIN_000(trans->entries[level].bxt.margin) |321 UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));322 }323 324 for (lane = 0; lane < crtc_state->lane_count; lane++) {325 int level = intel_ddi_level(encoder, crtc_state, lane);326 u32 val;327 328 intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),329 SCALE_DCOMP_METHOD,330 trans->entries[level].bxt.enable ?331 SCALE_DCOMP_METHOD : 0);332 333 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));334 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))335 drm_err(&dev_priv->drm,336 "Disabled scaling while ouniqetrangenmethod was set");337 }338 339 for (lane = 0; lane < crtc_state->lane_count; lane++) {340 int level = intel_ddi_level(encoder, crtc_state, lane);341 342 intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),343 DE_EMPHASIS_MASK,344 DE_EMPHASIS(trans->entries[level].bxt.deemphasis));345 }346 347 bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),348 BXT_PORT_PCS_DW10_GRP(phy, ch),349 0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);350}351 352bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,353 enum dpio_phy phy)354{355 const struct bxt_dpio_phy_info *phy_info;356 357 phy_info = bxt_get_phy_info(dev_priv, phy);358 359 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))360 return false;361 362 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &363 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {364 drm_dbg(&dev_priv->drm,365 "DDI PHY %d powered, but power hasn't settled\n", phy);366 367 return false;368 }369 370 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {371 drm_dbg(&dev_priv->drm,372 "DDI PHY %d powered, but still in reset\n", phy);373 374 return false;375 }376 377 return true;378}379 380static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)381{382 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));383 384 return REG_FIELD_GET(GRC_CODE_MASK, val);385}386 387static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,388 enum dpio_phy phy)389{390 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),391 GRC_DONE, 10))392 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",393 phy);394}395 396static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,397 enum dpio_phy phy)398{399 const struct bxt_dpio_phy_info *phy_info;400 u32 val;401 402 phy_info = bxt_get_phy_info(dev_priv, phy);403 404 if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {405 /* Still read out the GRC value for state verification */406 if (phy_info->rcomp_phy != -1)407 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);408 409 if (bxt_dpio_phy_verify_state(dev_priv, phy)) {410 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "411 "won't reprogram it\n", phy);412 return;413 }414 415 drm_dbg(&dev_priv->drm,416 "DDI PHY %d enabled with invalid state, "417 "force reprogramming it\n", phy);418 }419 420 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);421 422 /*423 * The PHY registers start out inaccessible and respond to reads with424 * all 1s. Eventually they become accessible as they power up, then425 * the reserved bit will give the default 0. Poll on the reserved bit426 * becoming 0 to find when the PHY is accessible.427 * The flag should get set in 100us according to the HW team, but428 * use 1ms due to occasional timeouts observed with that.429 */430 if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),431 PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1))432 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",433 phy);434 435 /* Program PLL Rcomp code offset */436 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),437 IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));438 439 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),440 IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));441 442 /* Program power gating */443 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,444 OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);445 446 if (phy_info->dual_channel)447 intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,448 DW6_OLDO_DYN_PWR_DOWN_EN);449 450 if (phy_info->rcomp_phy != -1) {451 u32 grc_code;452 453 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);454 455 /*456 * PHY0 isn't connected to an RCOMP resistor so copy over457 * the corresponding calibrated value from PHY1, and disable458 * the automatic calibration on PHY0.459 */460 val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);461 dev_priv->display.state.bxt_phy_grc = val;462 463 grc_code = GRC_CODE_FAST(val) |464 GRC_CODE_SLOW(val) |465 GRC_CODE_NOM(val);466 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);467 intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),468 0, GRC_DIS | GRC_RDY_OVRD);469 }470 471 if (phy_info->reset_delay)472 udelay(phy_info->reset_delay);473 474 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);475}476 477void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)478{479 const struct bxt_dpio_phy_info *phy_info;480 481 phy_info = bxt_get_phy_info(dev_priv, phy);482 483 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);484 485 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);486}487 488void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)489{490 const struct bxt_dpio_phy_info *phy_info =491 bxt_get_phy_info(dev_priv, phy);492 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;493 bool was_enabled;494 495 lockdep_assert_held(&dev_priv->display.power.domains.lock);496 497 was_enabled = true;498 if (rcomp_phy != -1)499 was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy);500 501 /*502 * We need to copy the GRC calibration value from rcomp_phy,503 * so make sure it's powered up.504 */505 if (!was_enabled)506 _bxt_dpio_phy_init(dev_priv, rcomp_phy);507 508 _bxt_dpio_phy_init(dev_priv, phy);509 510 if (!was_enabled)511 bxt_dpio_phy_uninit(dev_priv, rcomp_phy);512}513 514static bool __printf(6, 7)515__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,516 i915_reg_t reg, u32 mask, u32 expected,517 const char *reg_fmt, ...)518{519 struct va_format vaf;520 va_list args;521 u32 val;522 523 val = intel_de_read(dev_priv, reg);524 if ((val & mask) == expected)525 return true;526 527 va_start(args, reg_fmt);528 vaf.fmt = reg_fmt;529 vaf.va = &args;530 531 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "532 "current %08x, expected %08x (mask %08x)\n",533 phy, &vaf, reg.reg, val, (val & ~mask) | expected,534 mask);535 536 va_end(args);537 538 return false;539}540 541bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,542 enum dpio_phy phy)543{544 const struct bxt_dpio_phy_info *phy_info;545 u32 mask;546 bool ok;547 548 phy_info = bxt_get_phy_info(dev_priv, phy);549 550#define _CHK(reg, mask, exp, fmt, ...) \551 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \552 ## __VA_ARGS__)553 554 if (!bxt_dpio_phy_is_enabled(dev_priv, phy))555 return false;556 557 ok = true;558 559 /* PLL Rcomp code offset */560 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),561 IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xe4),562 "BXT_PORT_CL1CM_DW9(%d)", phy);563 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),564 IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xe4),565 "BXT_PORT_CL1CM_DW10(%d)", phy);566 567 /* Power gating */568 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;569 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,570 "BXT_PORT_CL1CM_DW28(%d)", phy);571 572 if (phy_info->dual_channel)573 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),574 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,575 "BXT_PORT_CL2CM_DW6(%d)", phy);576 577 if (phy_info->rcomp_phy != -1) {578 u32 grc_code = dev_priv->display.state.bxt_phy_grc;579 580 grc_code = GRC_CODE_FAST(grc_code) |581 GRC_CODE_SLOW(grc_code) |582 GRC_CODE_NOM(grc_code);583 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |584 GRC_CODE_NOM_MASK;585 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,586 "BXT_PORT_REF_DW6(%d)", phy);587 588 mask = GRC_DIS | GRC_RDY_OVRD;589 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,590 "BXT_PORT_REF_DW8(%d)", phy);591 }592 593 return ok;594#undef _CHK595}596 597u8598bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)599{600 switch (lane_count) {601 case 1:602 return 0;603 case 2:604 return BIT(2) | BIT(0);605 case 4:606 return BIT(3) | BIT(2) | BIT(0);607 default:608 MISSING_CASE(lane_count);609 610 return 0;611 }612}613 614void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,615 u8 lane_lat_optim_mask)616{617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);618 enum port port = encoder->port;619 enum dpio_phy phy;620 enum dpio_channel ch;621 int lane;622 623 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);624 625 for (lane = 0; lane < 4; lane++) {626 /*627 * Note that on CHV this flag is called UPAR, but has628 * the same function.629 */630 intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),631 LATENCY_OPTIM,632 lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);633 }634}635 636u8637bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)638{639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);640 enum port port = encoder->port;641 enum dpio_phy phy;642 enum dpio_channel ch;643 int lane;644 u8 mask;645 646 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);647 648 mask = 0;649 for (lane = 0; lane < 4; lane++) {650 u32 val = intel_de_read(dev_priv,651 BXT_PORT_TX_DW14_LN(phy, ch, lane));652 653 if (val & LATENCY_OPTIM)654 mask |= BIT(lane);655 }656 657 return mask;658}659 660enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)661{662 switch (dig_port->base.port) {663 default:664 MISSING_CASE(dig_port->base.port);665 fallthrough;666 case PORT_B:667 case PORT_D:668 return DPIO_CH0;669 case PORT_C:670 return DPIO_CH1;671 }672}673 674enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)675{676 switch (dig_port->base.port) {677 default:678 MISSING_CASE(dig_port->base.port);679 fallthrough;680 case PORT_B:681 case PORT_C:682 return DPIO_PHY0;683 case PORT_D:684 return DPIO_PHY1;685 }686}687 688enum dpio_phy vlv_pipe_to_phy(enum pipe pipe)689{690 switch (pipe) {691 default:692 MISSING_CASE(pipe);693 fallthrough;694 case PIPE_A:695 case PIPE_B:696 return DPIO_PHY0;697 case PIPE_C:698 return DPIO_PHY1;699 }700}701 702enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)703{704 switch (pipe) {705 default:706 MISSING_CASE(pipe);707 fallthrough;708 case PIPE_A:709 case PIPE_C:710 return DPIO_CH0;711 case PIPE_B:712 return DPIO_CH1;713 }714}715 716void chv_set_phy_signal_level(struct intel_encoder *encoder,717 const struct intel_crtc_state *crtc_state,718 u32 deemph_reg_value, u32 margin_reg_value,719 bool uniq_trans_scale)720{721 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);722 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);723 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);724 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);725 u32 val;726 int i;727 728 vlv_dpio_get(dev_priv);729 730 /* Clear calc init */731 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));732 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);733 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);734 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;735 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);736 737 if (crtc_state->lane_count > 2) {738 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));739 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);740 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);741 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;742 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);743 }744 745 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch));746 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);747 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;748 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val);749 750 if (crtc_state->lane_count > 2) {751 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch));752 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);753 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;754 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val);755 }756 757 /* Program swing deemph */758 for (i = 0; i < crtc_state->lane_count; i++) {759 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));760 val &= ~DPIO_SWING_DEEMPH9P5_MASK;761 val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value);762 vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);763 }764 765 /* Program swing margin */766 for (i = 0; i < crtc_state->lane_count; i++) {767 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));768 769 val &= ~DPIO_SWING_MARGIN000_MASK;770 val |= DPIO_SWING_MARGIN000(margin_reg_value);771 772 /*773 * Supposedly this value shouldn't matter when unique transition774 * scale is disabled, but in fact it does matter. Let's just775 * always program the same value and hope it's OK.776 */777 val &= ~DPIO_UNIQ_TRANS_SCALE_MASK;778 val |= DPIO_UNIQ_TRANS_SCALE(0x9a);779 780 vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);781 }782 783 /*784 * The document said it needs to set bit 27 for ch0 and bit 26785 * for ch1. Might be a typo in the doc.786 * For now, for this unique transition scale selection, set bit787 * 27 for ch0 and ch1.788 */789 for (i = 0; i < crtc_state->lane_count; i++) {790 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i));791 if (uniq_trans_scale)792 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;793 else794 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;795 vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val);796 }797 798 /* Start swing calculation */799 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));800 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;801 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);802 803 if (crtc_state->lane_count > 2) {804 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));805 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;806 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);807 }808 809 vlv_dpio_put(dev_priv);810}811 812void chv_data_lane_soft_reset(struct intel_encoder *encoder,813 const struct intel_crtc_state *crtc_state,814 bool reset)815{816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);817 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);818 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);819 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);820 u32 val;821 822 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));823 if (reset)824 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);825 else826 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;827 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val);828 829 if (crtc_state->lane_count > 2) {830 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch));831 if (reset)832 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);833 else834 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;835 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val);836 }837 838 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch));839 val |= CHV_PCS_REQ_SOFTRESET_EN;840 if (reset)841 val &= ~DPIO_PCS_CLK_SOFT_RESET;842 else843 val |= DPIO_PCS_CLK_SOFT_RESET;844 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val);845 846 if (crtc_state->lane_count > 2) {847 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch));848 val |= CHV_PCS_REQ_SOFTRESET_EN;849 if (reset)850 val &= ~DPIO_PCS_CLK_SOFT_RESET;851 else852 val |= DPIO_PCS_CLK_SOFT_RESET;853 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val);854 }855}856 857void chv_phy_pre_pll_enable(struct intel_encoder *encoder,858 const struct intel_crtc_state *crtc_state)859{860 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);863 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);864 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);865 enum pipe pipe = crtc->pipe;866 unsigned int lane_mask =867 intel_dp_unused_lane_mask(crtc_state->lane_count);868 u32 val;869 870 /*871 * Must trick the second common lane into life.872 * Otherwise we can't even access the PLL.873 */874 if (ch == DPIO_CH0 && pipe == PIPE_B)875 dig_port->release_cl2_override =876 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);877 878 chv_phy_powergate_lanes(encoder, true, lane_mask);879 880 vlv_dpio_get(dev_priv);881 882 /* Assert data lane reset */883 chv_data_lane_soft_reset(encoder, crtc_state, true);884 885 /* program left/right clock distribution */886 if (pipe != PIPE_B) {887 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);888 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);889 if (ch == DPIO_CH0)890 val |= CHV_BUFLEFTENA1_FORCE;891 if (ch == DPIO_CH1)892 val |= CHV_BUFRIGHTENA1_FORCE;893 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);894 } else {895 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);896 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);897 if (ch == DPIO_CH0)898 val |= CHV_BUFLEFTENA2_FORCE;899 if (ch == DPIO_CH1)900 val |= CHV_BUFRIGHTENA2_FORCE;901 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);902 }903 904 /* program clock channel usage */905 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));906 val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;907 if (pipe == PIPE_B)908 val |= DPIO_PCS_USEDCLKCHANNEL;909 else910 val &= ~DPIO_PCS_USEDCLKCHANNEL;911 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);912 913 if (crtc_state->lane_count > 2) {914 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));915 val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;916 if (pipe == PIPE_B)917 val |= DPIO_PCS_USEDCLKCHANNEL;918 else919 val &= ~DPIO_PCS_USEDCLKCHANNEL;920 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);921 }922 923 /*924 * This a a bit weird since generally CL925 * matches the pipe, but here we need to926 * pick the CL based on the port.927 */928 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));929 if (pipe == PIPE_B)930 val |= CHV_CMN_USEDCLKCHANNEL;931 else932 val &= ~CHV_CMN_USEDCLKCHANNEL;933 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);934 935 vlv_dpio_put(dev_priv);936}937 938void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,939 const struct intel_crtc_state *crtc_state)940{941 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);942 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);943 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);944 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);945 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);946 int data, i, stagger;947 u32 val;948 949 vlv_dpio_get(dev_priv);950 951 /* allow hardware to manage TX FIFO reset source */952 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));953 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;954 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);955 956 if (crtc_state->lane_count > 2) {957 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));958 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;959 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);960 }961 962 /* Program Tx lane latency optimal setting*/963 for (i = 0; i < crtc_state->lane_count; i++) {964 /* Set the upar bit */965 if (crtc_state->lane_count == 1)966 data = 0;967 else968 data = (i == 1) ? 0 : DPIO_UPAR;969 vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data);970 }971 972 /* Data lane stagger programming */973 if (crtc_state->port_clock > 270000)974 stagger = 0x18;975 else if (crtc_state->port_clock > 135000)976 stagger = 0xd;977 else if (crtc_state->port_clock > 67500)978 stagger = 0x7;979 else if (crtc_state->port_clock > 33750)980 stagger = 0x4;981 else982 stagger = 0x2;983 984 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));985 val |= DPIO_TX2_STAGGER_MASK(0x1f);986 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);987 988 if (crtc_state->lane_count > 2) {989 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));990 val |= DPIO_TX2_STAGGER_MASK(0x1f);991 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);992 }993 994 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch),995 DPIO_LANESTAGGER_STRAP(stagger) |996 DPIO_LANESTAGGER_STRAP_OVRD |997 DPIO_TX1_STAGGER_MASK(0x1f) |998 DPIO_TX1_STAGGER_MULT(6) |999 DPIO_TX2_STAGGER_MULT(0));1000 1001 if (crtc_state->lane_count > 2) {1002 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch),1003 DPIO_LANESTAGGER_STRAP(stagger) |1004 DPIO_LANESTAGGER_STRAP_OVRD |1005 DPIO_TX1_STAGGER_MASK(0x1f) |1006 DPIO_TX1_STAGGER_MULT(7) |1007 DPIO_TX2_STAGGER_MULT(5));1008 }1009 1010 /* Deassert data lane reset */1011 chv_data_lane_soft_reset(encoder, crtc_state, false);1012 1013 vlv_dpio_put(dev_priv);1014}1015 1016void chv_phy_release_cl2_override(struct intel_encoder *encoder)1017{1018 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1020 1021 if (dig_port->release_cl2_override) {1022 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);1023 dig_port->release_cl2_override = false;1024 }1025}1026 1027void chv_phy_post_pll_disable(struct intel_encoder *encoder,1028 const struct intel_crtc_state *old_crtc_state)1029{1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1031 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));1032 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;1033 u32 val;1034 1035 vlv_dpio_get(dev_priv);1036 1037 /* disable left/right clock distribution */1038 if (pipe != PIPE_B) {1039 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);1040 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);1041 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);1042 } else {1043 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);1044 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);1045 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);1046 }1047 1048 vlv_dpio_put(dev_priv);1049 1050 /*1051 * Leave the power down bit cleared for at least one1052 * lane so that chv_powergate_phy_ch() will power1053 * on something when the channel is otherwise unused.1054 * When the port is off and the override is removed1055 * the lanes power down anyway, so otherwise it doesn't1056 * really matter what the state of power down bits is1057 * after this.1058 */1059 chv_phy_powergate_lanes(encoder, false, 0x0);1060}1061 1062void vlv_set_phy_signal_level(struct intel_encoder *encoder,1063 const struct intel_crtc_state *crtc_state,1064 u32 demph_reg_value, u32 preemph_reg_value,1065 u32 uniqtranscale_reg_value, u32 tx3_demph)1066{1067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1068 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);1069 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);1070 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);1071 1072 vlv_dpio_get(dev_priv);1073 1074 vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);1075 vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);1076 vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),1077 uniqtranscale_reg_value);1078 vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);1079 1080 if (tx3_demph)1081 vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);1082 1083 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);1084 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);1085 vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);1086 1087 vlv_dpio_put(dev_priv);1088}1089 1090void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,1091 const struct intel_crtc_state *crtc_state)1092{1093 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);1094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1095 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);1096 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);1097 1098 /* Program Tx lane resets to default */1099 vlv_dpio_get(dev_priv);1100 1101 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),1102 DPIO_PCS_TX_LANE2_RESET |1103 DPIO_PCS_TX_LANE1_RESET);1104 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),1105 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |1106 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |1107 DPIO_PCS_CLK_DATAWIDTH_8_10 |1108 DPIO_PCS_CLK_SOFT_RESET);1109 1110 /* Fix up inter-pair skew failure */1111 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);1112 vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);1113 vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);1114 1115 vlv_dpio_put(dev_priv);1116}1117 1118void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,1119 const struct intel_crtc_state *crtc_state)1120{1121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);1122 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);1125 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);1126 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);1127 enum pipe pipe = crtc->pipe;1128 u32 val;1129 1130 vlv_dpio_get(dev_priv);1131 1132 /* Enable clock channels for this port */1133 val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;1134 if (pipe == PIPE_B)1135 val |= DPIO_PCS_USEDCLKCHANNEL;1136 val |= 0xc4;1137 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);1138 1139 /* Program lane clock */1140 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);1141 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);1142 1143 vlv_dpio_put(dev_priv);1144}1145 1146void vlv_phy_reset_lanes(struct intel_encoder *encoder,1147 const struct intel_crtc_state *old_crtc_state)1148{1149 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);1151 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);1152 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);1153 1154 vlv_dpio_get(dev_priv);1155 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);1156 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);1157 vlv_dpio_put(dev_priv);1158}1159