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1/*2 * Copyright © 2012-2016 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS21 * IN THE SOFTWARE.22 *23 */24 25#ifndef _INTEL_DPLL_MGR_H_26#define _INTEL_DPLL_MGR_H_27 28#include <linux/types.h>29 30#include "intel_display_power.h"31#include "intel_wakeref.h"32 33#define for_each_shared_dpll(__i915, __pll, __i) \34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)36 37enum tc_port;38struct drm_i915_private;39struct drm_printer;40struct intel_atomic_state;41struct intel_crtc;42struct intel_crtc_state;43struct intel_encoder;44struct intel_shared_dpll;45struct intel_shared_dpll_funcs;46 47/**48 * enum intel_dpll_id - possible DPLL ids49 *50 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.51 */52enum intel_dpll_id {53 /**54 * @DPLL_ID_PRIVATE: non-shared dpll in use55 */56 DPLL_ID_PRIVATE = -1,57 58 /**59 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB60 */61 DPLL_ID_PCH_PLL_A = 0,62 /**63 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB64 */65 DPLL_ID_PCH_PLL_B = 1,66 67 68 /**69 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL170 */71 DPLL_ID_WRPLL1 = 0,72 /**73 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL274 */75 DPLL_ID_WRPLL2 = 1,76 /**77 * @DPLL_ID_SPLL: HSW and BDW SPLL78 */79 DPLL_ID_SPLL = 2,80 /**81 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL82 */83 DPLL_ID_LCPLL_810 = 3,84 /**85 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL86 */87 DPLL_ID_LCPLL_1350 = 4,88 /**89 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL90 */91 DPLL_ID_LCPLL_2700 = 5,92 93 94 /**95 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL096 */97 DPLL_ID_SKL_DPLL0 = 0,98 /**99 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1100 */101 DPLL_ID_SKL_DPLL1 = 1,102 /**103 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2104 */105 DPLL_ID_SKL_DPLL2 = 2,106 /**107 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3108 */109 DPLL_ID_SKL_DPLL3 = 3,110 111 112 /**113 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0114 */115 DPLL_ID_ICL_DPLL0 = 0,116 /**117 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1118 */119 DPLL_ID_ICL_DPLL1 = 1,120 /**121 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4122 */123 DPLL_ID_EHL_DPLL4 = 2,124 /**125 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL126 */127 DPLL_ID_ICL_TBTPLL = 2,128 /**129 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),130 * TGL TC PLL 1 port 1 (TC1)131 */132 DPLL_ID_ICL_MGPLL1 = 3,133 /**134 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)135 * TGL TC PLL 1 port 2 (TC2)136 */137 DPLL_ID_ICL_MGPLL2 = 4,138 /**139 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)140 * TGL TC PLL 1 port 3 (TC3)141 */142 DPLL_ID_ICL_MGPLL3 = 5,143 /**144 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)145 * TGL TC PLL 1 port 4 (TC4)146 */147 DPLL_ID_ICL_MGPLL4 = 6,148 /**149 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)150 */151 DPLL_ID_TGL_MGPLL5 = 7,152 /**153 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)154 */155 DPLL_ID_TGL_MGPLL6 = 8,156 157 /**158 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0159 */160 DPLL_ID_DG1_DPLL0 = 0,161 /**162 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1163 */164 DPLL_ID_DG1_DPLL1 = 1,165 /**166 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2167 */168 DPLL_ID_DG1_DPLL2 = 2,169 /**170 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3171 */172 DPLL_ID_DG1_DPLL3 = 3,173};174 175#define I915_NUM_PLLS 9176 177enum icl_port_dpll_id {178 ICL_PORT_DPLL_DEFAULT,179 ICL_PORT_DPLL_MG_PHY,180 181 ICL_PORT_DPLL_COUNT,182};183 184struct i9xx_dpll_hw_state {185 u32 dpll;186 u32 dpll_md;187 u32 fp0;188 u32 fp1;189};190 191struct hsw_dpll_hw_state {192 u32 wrpll;193 u32 spll;194};195 196struct skl_dpll_hw_state {197 /*198 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in199 * lower part of ctrl1 and they get shifted into position when writing200 * the register. This allows us to easily compare the state to share201 * the DPLL.202 */203 u32 ctrl1;204 /* HDMI only, 0 when used for DP */205 u32 cfgcr1, cfgcr2;206};207 208struct bxt_dpll_hw_state {209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;210};211 212struct icl_dpll_hw_state {213 u32 cfgcr0, cfgcr1;214 215 /* tgl */216 u32 div0;217 218 u32 mg_refclkin_ctl;219 u32 mg_clktop2_coreclkctl1;220 u32 mg_clktop2_hsclkctl;221 u32 mg_pll_div0;222 u32 mg_pll_div1;223 u32 mg_pll_lf;224 u32 mg_pll_frac_lock;225 u32 mg_pll_ssc;226 u32 mg_pll_bias;227 u32 mg_pll_tdc_coldst_bias;228 u32 mg_pll_bias_mask;229 u32 mg_pll_tdc_coldst_bias_mask;230};231 232struct intel_mpllb_state {233 u32 clock; /* in KHz */234 u32 ref_control;235 u32 mpllb_cp;236 u32 mpllb_div;237 u32 mpllb_div2;238 u32 mpllb_fracn1;239 u32 mpllb_fracn2;240 u32 mpllb_sscen;241 u32 mpllb_sscstep;242};243 244struct intel_c10pll_state {245 u32 clock; /* in KHz */246 u8 tx;247 u8 cmn;248 u8 pll[20];249};250 251struct intel_c20pll_state {252 u32 clock; /* in kHz */253 u16 tx[3];254 u16 cmn[4];255 union {256 u16 mplla[10];257 u16 mpllb[11];258 };259};260 261struct intel_cx0pll_state {262 union {263 struct intel_c10pll_state c10;264 struct intel_c20pll_state c20;265 };266 bool ssc_enabled;267 bool use_c10;268 bool tbt_mode;269};270 271struct intel_dpll_hw_state {272 union {273 struct i9xx_dpll_hw_state i9xx;274 struct hsw_dpll_hw_state hsw;275 struct skl_dpll_hw_state skl;276 struct bxt_dpll_hw_state bxt;277 struct icl_dpll_hw_state icl;278 struct intel_mpllb_state mpllb;279 struct intel_cx0pll_state cx0pll;280 };281};282 283/**284 * struct intel_shared_dpll_state - hold the DPLL atomic state285 *286 * This structure holds an atomic state for the DPLL, that can represent287 * either its current state (in struct &intel_shared_dpll) or a desired288 * future state which would be applied by an atomic mode set (stored in289 * a struct &intel_atomic_state).290 *291 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().292 */293struct intel_shared_dpll_state {294 /**295 * @pipe_mask: mask of pipes using this DPLL, active or not296 */297 u8 pipe_mask;298 299 /**300 * @hw_state: hardware configuration for the DPLL stored in301 * struct &intel_dpll_hw_state.302 */303 struct intel_dpll_hw_state hw_state;304};305 306/**307 * struct dpll_info - display PLL platform specific info308 */309struct dpll_info {310 /**311 * @name: DPLL name; used for logging312 */313 const char *name;314 315 /**316 * @funcs: platform specific hooks317 */318 const struct intel_shared_dpll_funcs *funcs;319 320 /**321 * @id: unique indentifier for this DPLL322 */323 enum intel_dpll_id id;324 325 /**326 * @power_domain: extra power domain required by the DPLL327 */328 enum intel_display_power_domain power_domain;329 330 /**331 * @always_on:332 *333 * Inform the state checker that the DPLL is kept enabled even if334 * not in use by any CRTC.335 */336 bool always_on;337 338 /**339 * @is_alt_port_dpll:340 *341 * Inform the state checker that the DPLL can be used as a fallback342 * (for TC->TBT fallback).343 */344 bool is_alt_port_dpll;345};346 347/**348 * struct intel_shared_dpll - display PLL with tracked state and users349 */350struct intel_shared_dpll {351 /**352 * @state:353 *354 * Store the state for the pll, including its hw state355 * and CRTCs using it.356 */357 struct intel_shared_dpll_state state;358 359 /**360 * @index: index for atomic state361 */362 u8 index;363 364 /**365 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL366 */367 u8 active_mask;368 369 /**370 * @on: is the PLL actually active? Disabled during modeset371 */372 bool on;373 374 /**375 * @info: platform specific info376 */377 const struct dpll_info *info;378 379 /**380 * @wakeref: In some platforms a device-level runtime pm reference may381 * need to be grabbed to disable DC states while this DPLL is enabled382 */383 intel_wakeref_t wakeref;384};385 386#define SKL_DPLL0 0387#define SKL_DPLL1 1388#define SKL_DPLL2 2389#define SKL_DPLL3 3390 391/* shared dpll functions */392struct intel_shared_dpll *393intel_get_shared_dpll_by_id(struct drm_i915_private *i915,394 enum intel_dpll_id id);395void assert_shared_dpll(struct drm_i915_private *i915,396 struct intel_shared_dpll *pll,397 bool state);398#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)399#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)400int intel_compute_shared_dplls(struct intel_atomic_state *state,401 struct intel_crtc *crtc,402 struct intel_encoder *encoder);403int intel_reserve_shared_dplls(struct intel_atomic_state *state,404 struct intel_crtc *crtc,405 struct intel_encoder *encoder);406void intel_release_shared_dplls(struct intel_atomic_state *state,407 struct intel_crtc *crtc);408void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,409 const struct intel_shared_dpll *pll,410 struct intel_shared_dpll_state *shared_dpll_state);411void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,412 enum icl_port_dpll_id port_dpll_id);413void intel_update_active_dpll(struct intel_atomic_state *state,414 struct intel_crtc *crtc,415 struct intel_encoder *encoder);416int intel_dpll_get_freq(struct drm_i915_private *i915,417 const struct intel_shared_dpll *pll,418 const struct intel_dpll_hw_state *dpll_hw_state);419bool intel_dpll_get_hw_state(struct drm_i915_private *i915,420 struct intel_shared_dpll *pll,421 struct intel_dpll_hw_state *dpll_hw_state);422void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);423void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);424void intel_shared_dpll_swap_state(struct intel_atomic_state *state);425void intel_shared_dpll_init(struct drm_i915_private *i915);426void intel_dpll_update_ref_clks(struct drm_i915_private *i915);427void intel_dpll_readout_hw_state(struct drm_i915_private *i915);428void intel_dpll_sanitize_state(struct drm_i915_private *i915);429 430void intel_dpll_dump_hw_state(struct drm_i915_private *i915,431 struct drm_printer *p,432 const struct intel_dpll_hw_state *dpll_hw_state);433bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,434 const struct intel_dpll_hw_state *a,435 const struct intel_dpll_hw_state *b);436enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);437bool intel_dpll_is_combophy(enum intel_dpll_id id);438 439void intel_shared_dpll_state_verify(struct intel_atomic_state *state,440 struct intel_crtc *crtc);441void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);442 443#endif /* _INTEL_DPLL_MGR_H_ */444