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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2021 Intel Corporation4 */5 6#include "i915_drv.h"7#include "i915_reg.h"8#include "intel_atomic.h"9#include "intel_de.h"10#include "intel_display_types.h"11#include "intel_drrs.h"12#include "intel_frontbuffer.h"13#include "intel_panel.h"14 15/**16 * DOC: Display Refresh Rate Switching (DRRS)17 *18 * Display Refresh Rate Switching (DRRS) is a power conservation feature19 * which enables swtching between low and high refresh rates,20 * dynamically, based on the usage scenario. This feature is applicable21 * for internal panels.22 *23 * Indication that the panel supports DRRS is given by the panel EDID, which24 * would list multiple refresh rates for one resolution.25 *26 * DRRS is of 2 types - static and seamless.27 * Static DRRS involves changing refresh rate (RR) by doing a full modeset28 * (may appear as a blink on screen) and is used in dock-undock scenario.29 * Seamless DRRS involves changing RR without any visual effect to the user30 * and can be used during normal system usage. This is done by programming31 * certain registers.32 *33 * Support for static/seamless DRRS may be indicated in the VBT based on34 * inputs from the panel spec.35 *36 * DRRS saves power by switching to low RR based on usage scenarios.37 *38 * The implementation is based on frontbuffer tracking implementation. When39 * there is a disturbance on the screen triggered by user activity or a periodic40 * system activity, DRRS is disabled (RR is changed to high RR). When there is41 * no movement on screen, after a timeout of 1 second, a switch to low RR is42 * made.43 *44 * For integration with frontbuffer tracking code, intel_drrs_invalidate()45 * and intel_drrs_flush() are called.46 *47 * DRRS can be further extended to support other internal panels and also48 * the scenario of video playback wherein RR is set based on the rate49 * requested by userspace.50 */51 52const char *intel_drrs_type_str(enum drrs_type drrs_type)53{54 static const char * const str[] = {55 [DRRS_TYPE_NONE] = "none",56 [DRRS_TYPE_STATIC] = "static",57 [DRRS_TYPE_SEAMLESS] = "seamless",58 };59 60 if (drrs_type >= ARRAY_SIZE(str))61 return "<invalid>";62 63 return str[drrs_type];64}65 66bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915,67 enum transcoder cpu_transcoder)68{69 if (HAS_DOUBLE_BUFFERED_M_N(i915))70 return true;71 72 return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);73}74 75static void76intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc,77 enum drrs_refresh_rate refresh_rate)78{79 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);80 enum transcoder cpu_transcoder = crtc->drrs.cpu_transcoder;81 u32 bit;82 83 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))84 bit = TRANSCONF_REFRESH_RATE_ALT_VLV;85 else86 bit = TRANSCONF_REFRESH_RATE_ALT_ILK;87 88 intel_de_rmw(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),89 bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0);90}91 92static void93intel_drrs_set_refresh_rate_m_n(struct intel_crtc *crtc,94 enum drrs_refresh_rate refresh_rate)95{96 intel_cpu_transcoder_set_m1_n1(crtc, crtc->drrs.cpu_transcoder,97 refresh_rate == DRRS_REFRESH_RATE_LOW ?98 &crtc->drrs.m2_n2 : &crtc->drrs.m_n);99}100 101bool intel_drrs_is_active(struct intel_crtc *crtc)102{103 return crtc->drrs.cpu_transcoder != INVALID_TRANSCODER;104}105 106static void intel_drrs_set_state(struct intel_crtc *crtc,107 enum drrs_refresh_rate refresh_rate)108{109 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);110 111 if (refresh_rate == crtc->drrs.refresh_rate)112 return;113 114 if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder))115 intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate);116 else117 intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate);118 119 crtc->drrs.refresh_rate = refresh_rate;120}121 122static void intel_drrs_schedule_work(struct intel_crtc *crtc)123{124 struct drm_i915_private *i915 = to_i915(crtc->base.dev);125 126 mod_delayed_work(i915->unordered_wq, &crtc->drrs.work, msecs_to_jiffies(1000));127}128 129static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *crtc_state)130{131 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);132 struct drm_i915_private *i915 = to_i915(crtc->base.dev);133 unsigned int frontbuffer_bits;134 135 frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);136 137 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc,138 crtc_state->joiner_pipes)139 frontbuffer_bits |= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);140 141 return frontbuffer_bits;142}143 144/**145 * intel_drrs_activate - activate DRRS146 * @crtc_state: the crtc state147 *148 * Activates DRRS on the crtc.149 */150void intel_drrs_activate(const struct intel_crtc_state *crtc_state)151{152 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);153 154 if (!crtc_state->has_drrs)155 return;156 157 if (!crtc_state->hw.active)158 return;159 160 if (intel_crtc_is_joiner_secondary(crtc_state))161 return;162 163 mutex_lock(&crtc->drrs.mutex);164 165 crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder;166 crtc->drrs.m_n = crtc_state->dp_m_n;167 crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;168 crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);169 crtc->drrs.busy_frontbuffer_bits = 0;170 171 intel_drrs_schedule_work(crtc);172 173 mutex_unlock(&crtc->drrs.mutex);174}175 176/**177 * intel_drrs_deactivate - deactivate DRRS178 * @old_crtc_state: the old crtc state179 *180 * Deactivates DRRS on the crtc.181 */182void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)183{184 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);185 186 if (!old_crtc_state->has_drrs)187 return;188 189 if (!old_crtc_state->hw.active)190 return;191 192 if (intel_crtc_is_joiner_secondary(old_crtc_state))193 return;194 195 mutex_lock(&crtc->drrs.mutex);196 197 if (intel_drrs_is_active(crtc))198 intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);199 200 crtc->drrs.cpu_transcoder = INVALID_TRANSCODER;201 crtc->drrs.frontbuffer_bits = 0;202 crtc->drrs.busy_frontbuffer_bits = 0;203 204 mutex_unlock(&crtc->drrs.mutex);205 206 cancel_delayed_work_sync(&crtc->drrs.work);207}208 209static void intel_drrs_downclock_work(struct work_struct *work)210{211 struct intel_crtc *crtc = container_of(work, typeof(*crtc), drrs.work.work);212 213 mutex_lock(&crtc->drrs.mutex);214 215 if (intel_drrs_is_active(crtc) && !crtc->drrs.busy_frontbuffer_bits)216 intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_LOW);217 218 mutex_unlock(&crtc->drrs.mutex);219}220 221static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,222 unsigned int all_frontbuffer_bits,223 bool invalidate)224{225 struct intel_crtc *crtc;226 227 for_each_intel_crtc(&dev_priv->drm, crtc) {228 unsigned int frontbuffer_bits;229 230 mutex_lock(&crtc->drrs.mutex);231 232 frontbuffer_bits = all_frontbuffer_bits & crtc->drrs.frontbuffer_bits;233 if (!frontbuffer_bits) {234 mutex_unlock(&crtc->drrs.mutex);235 continue;236 }237 238 if (invalidate)239 crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits;240 else241 crtc->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;242 243 /* flush/invalidate means busy screen hence upclock */244 intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);245 246 /*247 * flush also means no more activity hence schedule downclock, if all248 * other fbs are quiescent too249 */250 if (!crtc->drrs.busy_frontbuffer_bits)251 intel_drrs_schedule_work(crtc);252 else253 cancel_delayed_work(&crtc->drrs.work);254 255 mutex_unlock(&crtc->drrs.mutex);256 }257}258 259/**260 * intel_drrs_invalidate - Disable Idleness DRRS261 * @dev_priv: i915 device262 * @frontbuffer_bits: frontbuffer plane tracking bits263 *264 * This function gets called everytime rendering on the given planes start.265 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).266 *267 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.268 */269void intel_drrs_invalidate(struct drm_i915_private *dev_priv,270 unsigned int frontbuffer_bits)271{272 intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true);273}274 275/**276 * intel_drrs_flush - Restart Idleness DRRS277 * @dev_priv: i915 device278 * @frontbuffer_bits: frontbuffer plane tracking bits279 *280 * This function gets called every time rendering on the given planes has281 * completed or flip on a crtc is completed. So DRRS should be upclocked282 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,283 * if no other planes are dirty.284 *285 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.286 */287void intel_drrs_flush(struct drm_i915_private *dev_priv,288 unsigned int frontbuffer_bits)289{290 intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false);291}292 293/**294 * intel_drrs_crtc_init - Init DRRS for CRTC295 * @crtc: crtc296 *297 * This function is called only once at driver load to initialize basic298 * DRRS stuff.299 *300 */301void intel_drrs_crtc_init(struct intel_crtc *crtc)302{303 INIT_DELAYED_WORK(&crtc->drrs.work, intel_drrs_downclock_work);304 mutex_init(&crtc->drrs.mutex);305 crtc->drrs.cpu_transcoder = INVALID_TRANSCODER;306}307 308static int intel_drrs_debugfs_status_show(struct seq_file *m, void *unused)309{310 struct intel_crtc *crtc = m->private;311 struct drm_i915_private *i915 = to_i915(crtc->base.dev);312 const struct intel_crtc_state *crtc_state;313 int ret;314 315 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);316 if (ret)317 return ret;318 319 crtc_state = to_intel_crtc_state(crtc->base.state);320 321 mutex_lock(&crtc->drrs.mutex);322 323 seq_printf(m, "DRRS capable: %s\n",324 str_yes_no(intel_cpu_transcoder_has_drrs(i915,325 crtc_state->cpu_transcoder)));326 327 seq_printf(m, "DRRS enabled: %s\n",328 str_yes_no(crtc_state->has_drrs));329 330 seq_printf(m, "DRRS active: %s\n",331 str_yes_no(intel_drrs_is_active(crtc)));332 333 seq_printf(m, "DRRS refresh rate: %s\n",334 crtc->drrs.refresh_rate == DRRS_REFRESH_RATE_LOW ?335 "low" : "high");336 337 seq_printf(m, "DRRS busy frontbuffer bits: 0x%x\n",338 crtc->drrs.busy_frontbuffer_bits);339 340 mutex_unlock(&crtc->drrs.mutex);341 342 drm_modeset_unlock(&crtc->base.mutex);343 344 return 0;345}346 347DEFINE_SHOW_ATTRIBUTE(intel_drrs_debugfs_status);348 349static int intel_drrs_debugfs_ctl_set(void *data, u64 val)350{351 struct intel_crtc *crtc = data;352 struct drm_i915_private *i915 = to_i915(crtc->base.dev);353 struct intel_crtc_state *crtc_state;354 struct drm_crtc_commit *commit;355 int ret;356 357 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex);358 if (ret)359 return ret;360 361 crtc_state = to_intel_crtc_state(crtc->base.state);362 363 if (!crtc_state->hw.active ||364 !crtc_state->has_drrs)365 goto out;366 367 commit = crtc_state->uapi.commit;368 if (commit) {369 ret = wait_for_completion_interruptible(&commit->hw_done);370 if (ret)371 goto out;372 }373 374 drm_dbg(&i915->drm,375 "Manually %sactivating DRRS\n", val ? "" : "de");376 377 if (val)378 intel_drrs_activate(crtc_state);379 else380 intel_drrs_deactivate(crtc_state);381 382out:383 drm_modeset_unlock(&crtc->base.mutex);384 385 return ret;386}387 388DEFINE_DEBUGFS_ATTRIBUTE(intel_drrs_debugfs_ctl_fops,389 NULL, intel_drrs_debugfs_ctl_set, "%llu\n");390 391void intel_drrs_crtc_debugfs_add(struct intel_crtc *crtc)392{393 debugfs_create_file("i915_drrs_status", 0444, crtc->base.debugfs_entry,394 crtc, &intel_drrs_debugfs_status_fops);395 396 debugfs_create_file_unsafe("i915_drrs_ctl", 0644, crtc->base.debugfs_entry,397 crtc, &intel_drrs_debugfs_ctl_fops);398}399 400static int intel_drrs_debugfs_type_show(struct seq_file *m, void *unused)401{402 struct intel_connector *connector = m->private;403 404 seq_printf(m, "DRRS type: %s\n",405 intel_drrs_type_str(intel_panel_drrs_type(connector)));406 407 return 0;408}409 410DEFINE_SHOW_ATTRIBUTE(intel_drrs_debugfs_type);411 412void intel_drrs_connector_debugfs_add(struct intel_connector *connector)413{414 if (intel_panel_drrs_type(connector) == DRRS_TYPE_NONE)415 return;416 417 debugfs_create_file("i915_drrs_type", 0444, connector->base.debugfs_entry,418 connector, &intel_drrs_debugfs_type_fops);419}420