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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2021 Intel Corporation4 */5 6#include <drm/drm_blend.h>7#include <drm/drm_modeset_helper.h>8 9#include <linux/dma-fence.h>10#include <linux/dma-resv.h>11 12#include "gem/i915_gem_object.h"13#include "i915_drv.h"14#include "intel_atomic_plane.h"15#include "intel_display.h"16#include "intel_display_types.h"17#include "intel_dpt.h"18#include "intel_fb.h"19#include "intel_fb_bo.h"20#include "intel_frontbuffer.h"21 22#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))23 24/*25 * From the Sky Lake PRM:26 * "The Color Control Surface (CCS) contains the compression status of27 * the cache-line pairs. The compression state of the cache-line pair28 * is specified by 2 bits in the CCS. Each CCS cache-line represents29 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled30 * cache-line-pairs. CCS is always Y tiled."31 *32 * Since cache line pairs refers to horizontally adjacent cache lines,33 * each cache line in the CCS corresponds to an area of 32x16 cache34 * lines on the main surface. Since each pixel is 4 bytes, this gives35 * us a ratio of one byte in the CCS for each 8x16 pixels in the36 * main surface.37 */38static const struct drm_format_info skl_ccs_formats[] = {39 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,40 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },41 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,42 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },43 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,44 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },45 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,46 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },47};48 49/*50 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the51 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles52 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of53 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in54 * the main surface.55 */56static const struct drm_format_info gen12_ccs_formats[] = {57 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,58 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },59 .hsub = 1, .vsub = 1, },60 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,61 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },62 .hsub = 1, .vsub = 1, },63 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,64 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },65 .hsub = 1, .vsub = 1, .has_alpha = true },66 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,67 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },68 .hsub = 1, .vsub = 1, .has_alpha = true },69 { .format = DRM_FORMAT_YUYV, .num_planes = 2,70 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },71 .hsub = 2, .vsub = 1, .is_yuv = true },72 { .format = DRM_FORMAT_YVYU, .num_planes = 2,73 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },74 .hsub = 2, .vsub = 1, .is_yuv = true },75 { .format = DRM_FORMAT_UYVY, .num_planes = 2,76 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },77 .hsub = 2, .vsub = 1, .is_yuv = true },78 { .format = DRM_FORMAT_VYUY, .num_planes = 2,79 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },80 .hsub = 2, .vsub = 1, .is_yuv = true },81 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,82 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },83 .hsub = 1, .vsub = 1, .is_yuv = true },84 { .format = DRM_FORMAT_NV12, .num_planes = 4,85 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },86 .hsub = 2, .vsub = 2, .is_yuv = true },87 { .format = DRM_FORMAT_P010, .num_planes = 4,88 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },89 .hsub = 2, .vsub = 2, .is_yuv = true },90 { .format = DRM_FORMAT_P012, .num_planes = 4,91 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },92 .hsub = 2, .vsub = 2, .is_yuv = true },93 { .format = DRM_FORMAT_P016, .num_planes = 4,94 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },95 .hsub = 2, .vsub = 2, .is_yuv = true },96};97 98/*99 * Same as gen12_ccs_formats[] above, but with additional surface used100 * to pass Clear Color information in plane 2 with 64 bits of data.101 */102static const struct drm_format_info gen12_ccs_cc_formats[] = {103 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,104 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },105 .hsub = 1, .vsub = 1, },106 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,107 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },108 .hsub = 1, .vsub = 1, },109 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,110 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },111 .hsub = 1, .vsub = 1, .has_alpha = true },112 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,113 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },114 .hsub = 1, .vsub = 1, .has_alpha = true },115};116 117static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {118 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,119 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },120 .hsub = 1, .vsub = 1, },121 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,122 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },123 .hsub = 1, .vsub = 1, },124 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,125 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },126 .hsub = 1, .vsub = 1, .has_alpha = true },127 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,128 .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },129 .hsub = 1, .vsub = 1, .has_alpha = true },130};131 132struct intel_modifier_desc {133 u64 modifier;134 struct {135 u8 from;136 u8 until;137 } display_ver;138#define DISPLAY_VER_ALL { 0, -1 }139 140 const struct drm_format_info *formats;141 int format_count;142#define FORMAT_OVERRIDE(format_list) \143 .formats = format_list, \144 .format_count = ARRAY_SIZE(format_list)145 146 u8 plane_caps;147 148 struct {149 u8 cc_planes:3;150 u8 packed_aux_planes:4;151 u8 planar_aux_planes:4;152 } ccs;153};154 155#define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \156 INTEL_PLANE_CAP_CCS_RC_CC | \157 INTEL_PLANE_CAP_CCS_MC)158#define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \159 INTEL_PLANE_CAP_TILING_Y | \160 INTEL_PLANE_CAP_TILING_Yf | \161 INTEL_PLANE_CAP_TILING_4)162#define INTEL_PLANE_CAP_TILING_NONE 0163 164static const struct intel_modifier_desc intel_modifiers[] = {165 {166 .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS,167 .display_ver = { 20, -1 },168 .plane_caps = INTEL_PLANE_CAP_TILING_4,169 }, {170 .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,171 .display_ver = { 14, -1 },172 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,173 }, {174 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,175 .display_ver = { 14, 14 },176 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,177 178 .ccs.packed_aux_planes = BIT(1),179 .ccs.planar_aux_planes = BIT(2) | BIT(3),180 181 FORMAT_OVERRIDE(gen12_ccs_formats),182 }, {183 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,184 .display_ver = { 14, 14 },185 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,186 187 .ccs.packed_aux_planes = BIT(1),188 189 FORMAT_OVERRIDE(gen12_ccs_formats),190 }, {191 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC,192 .display_ver = { 14, 14 },193 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,194 195 .ccs.cc_planes = BIT(2),196 .ccs.packed_aux_planes = BIT(1),197 198 FORMAT_OVERRIDE(gen12_ccs_cc_formats),199 }, {200 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,201 .display_ver = { 13, 13 },202 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,203 }, {204 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,205 .display_ver = { 13, 13 },206 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,207 208 .ccs.cc_planes = BIT(1),209 210 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),211 }, {212 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,213 .display_ver = { 13, 13 },214 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,215 }, {216 .modifier = I915_FORMAT_MOD_4_TILED,217 .display_ver = { 13, -1 },218 .plane_caps = INTEL_PLANE_CAP_TILING_4,219 }, {220 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,221 .display_ver = { 12, 13 },222 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,223 224 .ccs.packed_aux_planes = BIT(1),225 .ccs.planar_aux_planes = BIT(2) | BIT(3),226 227 FORMAT_OVERRIDE(gen12_ccs_formats),228 }, {229 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,230 .display_ver = { 12, 13 },231 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,232 233 .ccs.packed_aux_planes = BIT(1),234 235 FORMAT_OVERRIDE(gen12_ccs_formats),236 }, {237 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,238 .display_ver = { 12, 13 },239 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC,240 241 .ccs.cc_planes = BIT(2),242 .ccs.packed_aux_planes = BIT(1),243 244 FORMAT_OVERRIDE(gen12_ccs_cc_formats),245 }, {246 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,247 .display_ver = { 9, 11 },248 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC,249 250 .ccs.packed_aux_planes = BIT(1),251 252 FORMAT_OVERRIDE(skl_ccs_formats),253 }, {254 .modifier = I915_FORMAT_MOD_Y_TILED_CCS,255 .display_ver = { 9, 11 },256 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,257 258 .ccs.packed_aux_planes = BIT(1),259 260 FORMAT_OVERRIDE(skl_ccs_formats),261 }, {262 .modifier = I915_FORMAT_MOD_Yf_TILED,263 .display_ver = { 9, 11 },264 .plane_caps = INTEL_PLANE_CAP_TILING_Yf,265 }, {266 .modifier = I915_FORMAT_MOD_Y_TILED,267 .display_ver = { 9, 13 },268 .plane_caps = INTEL_PLANE_CAP_TILING_Y,269 }, {270 .modifier = I915_FORMAT_MOD_X_TILED,271 .display_ver = DISPLAY_VER_ALL,272 .plane_caps = INTEL_PLANE_CAP_TILING_X,273 }, {274 .modifier = DRM_FORMAT_MOD_LINEAR,275 .display_ver = DISPLAY_VER_ALL,276 },277};278 279static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)280{281 int i;282 283 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)284 if (intel_modifiers[i].modifier == modifier)285 return &intel_modifiers[i];286 287 return NULL;288}289 290static const struct intel_modifier_desc *lookup_modifier(u64 modifier)291{292 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);293 294 if (WARN_ON(!md))295 return &intel_modifiers[0];296 297 return md;298}299 300static const struct drm_format_info *301lookup_format_info(const struct drm_format_info formats[],302 int num_formats, u32 format)303{304 int i;305 306 for (i = 0; i < num_formats; i++) {307 if (formats[i].format == format)308 return &formats[i];309 }310 311 return NULL;312}313 314unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)315{316 const struct intel_modifier_desc *md;317 u8 tiling_caps;318 319 md = lookup_modifier_or_null(fb_modifier);320 if (!md)321 return I915_TILING_NONE;322 323 tiling_caps = lookup_modifier_or_null(fb_modifier)->plane_caps &324 INTEL_PLANE_CAP_TILING_MASK;325 326 switch (tiling_caps) {327 case INTEL_PLANE_CAP_TILING_Y:328 return I915_TILING_Y;329 case INTEL_PLANE_CAP_TILING_X:330 return I915_TILING_X;331 case INTEL_PLANE_CAP_TILING_4:332 case INTEL_PLANE_CAP_TILING_Yf:333 case INTEL_PLANE_CAP_TILING_NONE:334 return I915_TILING_NONE;335 default:336 MISSING_CASE(tiling_caps);337 return I915_TILING_NONE;338 }339}340 341/**342 * intel_fb_get_format_info: Get a modifier specific format information343 * @cmd: FB add command structure344 *345 * Returns:346 * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],347 * or %NULL if the modifier doesn't override the format.348 */349const struct drm_format_info *350intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)351{352 const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);353 354 if (!md || !md->formats)355 return NULL;356 357 return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);358}359 360static bool plane_caps_contain_any(u8 caps, u8 mask)361{362 return caps & mask;363}364 365static bool plane_caps_contain_all(u8 caps, u8 mask)366{367 return (caps & mask) == mask;368}369 370/**371 * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type372 * @modifier: Modifier to check373 *374 * Returns:375 * Returns %true if @modifier is a tiled modifier.376 */377bool intel_fb_is_tiled_modifier(u64 modifier)378{379 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,380 INTEL_PLANE_CAP_TILING_MASK);381}382 383/**384 * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type385 * @modifier: Modifier to check386 *387 * Returns:388 * Returns %true if @modifier is a render, render with color clear or389 * media compression modifier.390 */391bool intel_fb_is_ccs_modifier(u64 modifier)392{393 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,394 INTEL_PLANE_CAP_CCS_MASK);395}396 397/**398 * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type399 * @modifier: Modifier to check400 *401 * Returns:402 * Returns %true if @modifier is a render with color clear modifier.403 */404bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)405{406 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,407 INTEL_PLANE_CAP_CCS_RC_CC);408}409 410/**411 * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type412 * @modifier: Modifier to check413 *414 * Returns:415 * Returns %true if @modifier is a media compression modifier.416 */417bool intel_fb_is_mc_ccs_modifier(u64 modifier)418{419 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,420 INTEL_PLANE_CAP_CCS_MC);421}422 423/**424 * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.425 * @modifier: Modifier to check426 *427 * Returns:428 * Returns %true if @modifier requires 64k aligned physical pages.429 */430bool intel_fb_needs_64k_phys(u64 modifier)431{432 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);433 434 if (!md)435 return false;436 437 return plane_caps_contain_any(md->plane_caps,438 INTEL_PLANE_CAP_NEED64K_PHYS);439}440 441/**442 * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type443 * @modifier: Modifier to check444 *445 * Returns:446 * Returns %true if @modifier is a tile4 modifier.447 */448bool intel_fb_is_tile4_modifier(u64 modifier)449{450 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,451 INTEL_PLANE_CAP_TILING_4);452}453 454static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,455 u8 display_ver_from, u8 display_ver_until)456{457 return md->display_ver.from <= display_ver_until &&458 display_ver_from <= md->display_ver.until;459}460 461static bool plane_has_modifier(struct drm_i915_private *i915,462 u8 plane_caps,463 const struct intel_modifier_desc *md)464{465 if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until))466 return false;467 468 if (!plane_caps_contain_all(plane_caps, md->plane_caps))469 return false;470 471 /*472 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms473 * where supported.474 */475 if (intel_fb_is_ccs_modifier(md->modifier) &&476 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)477 return false;478 479 if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&480 (GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915)))481 return false;482 483 if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS &&484 (GRAPHICS_VER(i915) < 20 || IS_DGFX(i915)))485 return false;486 487 return true;488}489 490/**491 * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities492 * @i915: i915 device instance493 * @plane_caps: capabilities for the plane the modifiers are queried for494 *495 * Returns:496 * Returns the list of modifiers allowed by the @i915 platform and @plane_caps.497 * The caller must free the returned buffer.498 */499u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,500 u8 plane_caps)501{502 u64 *list, *p;503 int count = 1; /* +1 for invalid modifier terminator */504 int i;505 506 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {507 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))508 count++;509 }510 511 list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);512 if (drm_WARN_ON(&i915->drm, !list))513 return NULL;514 515 p = list;516 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {517 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))518 *p++ = intel_modifiers[i].modifier;519 }520 *p++ = DRM_FORMAT_MOD_INVALID;521 522 return list;523}524 525/**526 * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane527 * @plane: Plane to check the modifier support for528 * @modifier: The modifier to check the support for529 *530 * Returns:531 * %true if the @modifier is supported on @plane.532 */533bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)534{535 int i;536 537 for (i = 0; i < plane->base.modifier_count; i++)538 if (plane->base.modifiers[i] == modifier)539 return true;540 541 return false;542}543 544static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,545 const struct drm_format_info *info)546{547 if (!info->is_yuv)548 return false;549 550 if (hweight8(md->ccs.planar_aux_planes) == 2)551 return info->num_planes == 4;552 else553 return info->num_planes == 2;554}555 556/**557 * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar558 * @info: format to check559 * @modifier: modifier used with the format560 *561 * Returns:562 * %true if @info / @modifier is YUV semiplanar.563 */564bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,565 u64 modifier)566{567 return format_is_yuv_semiplanar(lookup_modifier(modifier), info);568}569 570static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,571 const struct drm_format_info *format)572{573 if (format_is_yuv_semiplanar(md, format))574 return md->ccs.planar_aux_planes;575 else576 return md->ccs.packed_aux_planes;577}578 579/**580 * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane581 * @fb: Framebuffer582 * @color_plane: color plane index to check583 *584 * Returns:585 * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.586 */587bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)588{589 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);590 591 return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);592}593 594/**595 * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane596 * @fb: Framebuffer597 * @color_plane: color plane index to check598 *599 * Returns:600 * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.601 */602static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)603{604 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);605 606 return check_modifier_display_ver_range(md, 12, 14) &&607 ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);608}609 610/**611 * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer612 * @fb: Framebuffer613 *614 * Returns:615 * Returns the index of the color clear plane for @fb, or -1 if @fb is not a616 * framebuffer using a render compression/color clear modifier.617 */618int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)619{620 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);621 622 if (!md->ccs.cc_planes)623 return -1;624 625 drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);626 627 return ilog2((int)md->ccs.cc_planes);628}629 630static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)631{632 return intel_fb_rc_ccs_cc_plane(fb) == color_plane;633}634 635bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)636{637 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||638 intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) ||639 is_gen12_ccs_cc_plane(fb, color_plane);640}641 642int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)643{644 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||645 (main_plane && main_plane >= fb->format->num_planes / 2));646 647 return fb->format->num_planes / 2 + main_plane;648}649 650int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)651{652 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||653 ccs_plane < fb->format->num_planes / 2);654 655 if (is_gen12_ccs_cc_plane(fb, ccs_plane))656 return 0;657 658 return ccs_plane - fb->format->num_planes / 2;659}660 661static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane)662{663 int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane);664 unsigned int main_stride = fb->base.pitches[main_plane];665 unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane);666 667 return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;668}669 670int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)671{672 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);673 struct drm_i915_private *i915 = to_i915(fb->dev);674 675 if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)676 return main_to_ccs_plane(fb, main_plane);677 else if (DISPLAY_VER(i915) < 11 &&678 format_is_yuv_semiplanar(md, fb->format))679 return 1;680 else681 return 0;682}683 684unsigned int intel_tile_size(const struct drm_i915_private *i915)685{686 return DISPLAY_VER(i915) == 2 ? 2048 : 4096;687}688 689unsigned int690intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)691{692 struct drm_i915_private *dev_priv = to_i915(fb->dev);693 unsigned int cpp = fb->format->cpp[color_plane];694 695 switch (fb->modifier) {696 case DRM_FORMAT_MOD_LINEAR:697 return intel_tile_size(dev_priv);698 case I915_FORMAT_MOD_X_TILED:699 if (DISPLAY_VER(dev_priv) == 2)700 return 128;701 else702 return 512;703 case I915_FORMAT_MOD_4_TILED_BMG_CCS:704 case I915_FORMAT_MOD_4_TILED_LNL_CCS:705 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:706 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:707 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:708 case I915_FORMAT_MOD_4_TILED:709 /*710 * Each 4K tile consists of 64B(8*8) subtiles, with711 * same shape as Y Tile(i.e 4*16B OWords)712 */713 return 128;714 case I915_FORMAT_MOD_Y_TILED_CCS:715 if (intel_fb_is_ccs_aux_plane(fb, color_plane))716 return 128;717 fallthrough;718 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:719 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:720 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:721 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:722 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:723 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:724 if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||725 is_gen12_ccs_cc_plane(fb, color_plane))726 return 64;727 fallthrough;728 case I915_FORMAT_MOD_Y_TILED:729 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))730 return 128;731 else732 return 512;733 case I915_FORMAT_MOD_Yf_TILED_CCS:734 if (intel_fb_is_ccs_aux_plane(fb, color_plane))735 return 128;736 fallthrough;737 case I915_FORMAT_MOD_Yf_TILED:738 switch (cpp) {739 case 1:740 return 64;741 case 2:742 case 4:743 return 128;744 case 8:745 case 16:746 return 256;747 default:748 MISSING_CASE(cpp);749 return cpp;750 }751 break;752 default:753 MISSING_CASE(fb->modifier);754 return cpp;755 }756}757 758unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)759{760 return intel_tile_size(to_i915(fb->dev)) /761 intel_tile_width_bytes(fb, color_plane);762}763 764/*765 * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT766 * page tile size.767 */768static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,769 unsigned int *tile_width,770 unsigned int *tile_height)771{772 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);773 unsigned int cpp = fb->format->cpp[color_plane];774 775 *tile_width = tile_width_bytes / cpp;776 *tile_height = intel_tile_height(fb, color_plane);777}778 779/*780 * Return the tile dimensions in pixel units, based on the tile block size.781 * The block covers the full GTT page sized tile on all tiled surfaces and782 * it's a 64 byte portion of the tile on TGL+ CCS surfaces.783 */784static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane,785 unsigned int *tile_width,786 unsigned int *tile_height)787{788 intel_tile_dims(fb, color_plane, tile_width, tile_height);789 790 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane))791 *tile_height = 1;792}793 794unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane)795{796 unsigned int tile_width, tile_height;797 798 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);799 800 return fb->pitches[color_plane] * tile_height;801}802 803unsigned int804intel_fb_align_height(const struct drm_framebuffer *fb,805 int color_plane, unsigned int height)806{807 unsigned int tile_height = intel_tile_height(fb, color_plane);808 809 return ALIGN(height, tile_height);810}811 812bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)813{814 return HAS_DPT(i915) && modifier != DRM_FORMAT_MOD_LINEAR;815}816 817bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)818{819 return to_i915(fb->dev)->display.params.enable_dpt &&820 intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);821}822 823void intel_fb_plane_get_subsampling(int *hsub, int *vsub,824 const struct drm_framebuffer *fb,825 int color_plane)826{827 int main_plane;828 829 if (color_plane == 0) {830 *hsub = 1;831 *vsub = 1;832 833 return;834 }835 836 /*837 * TODO: Deduct the subsampling from the char block for all CCS838 * formats and planes.839 */840 if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) {841 *hsub = fb->format->hsub;842 *vsub = fb->format->vsub;843 844 return;845 }846 847 main_plane = skl_ccs_to_main_plane(fb, color_plane);848 *hsub = drm_format_info_block_width(fb->format, color_plane) /849 drm_format_info_block_width(fb->format, main_plane);850 851 /*852 * The min stride check in the core framebuffer_check() function853 * assumes that format->hsub applies to every plane except for the854 * first plane. That's incorrect for the CCS AUX plane of the first855 * plane, but for the above check to pass we must define the block856 * width with that subsampling applied to it. Adjust the width here857 * accordingly, so we can calculate the actual subsampling factor.858 */859 if (main_plane == 0)860 *hsub *= fb->format->hsub;861 862 *vsub = 32;863}864 865static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)866{867 int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ?868 skl_ccs_to_main_plane(&fb->base, color_plane) : 0;869 unsigned int main_width = fb->base.width;870 unsigned int main_height = fb->base.height;871 int main_hsub, main_vsub;872 int hsub, vsub;873 874 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane);875 intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane);876 877 *w = DIV_ROUND_UP(main_width, main_hsub * hsub);878 *h = DIV_ROUND_UP(main_height, main_vsub * vsub);879}880 881static u32 intel_adjust_tile_offset(int *x, int *y,882 unsigned int tile_width,883 unsigned int tile_height,884 unsigned int tile_size,885 unsigned int pitch_tiles,886 u32 old_offset,887 u32 new_offset)888{889 unsigned int pitch_pixels = pitch_tiles * tile_width;890 unsigned int tiles;891 892 WARN_ON(old_offset & (tile_size - 1));893 WARN_ON(new_offset & (tile_size - 1));894 WARN_ON(new_offset > old_offset);895 896 tiles = (old_offset - new_offset) / tile_size;897 898 *y += tiles / pitch_tiles * tile_height;899 *x += tiles % pitch_tiles * tile_width;900 901 /* minimize x in case it got needlessly big */902 *y += *x / pitch_pixels * tile_height;903 *x %= pitch_pixels;904 905 return new_offset;906}907 908static u32 intel_adjust_linear_offset(int *x, int *y,909 unsigned int cpp,910 unsigned int pitch,911 u32 old_offset,912 u32 new_offset)913{914 old_offset += *y * pitch + *x * cpp;915 916 *y = (old_offset - new_offset) / pitch;917 *x = ((old_offset - new_offset) - *y * pitch) / cpp;918 919 return new_offset;920}921 922static u32 intel_adjust_aligned_offset(int *x, int *y,923 const struct drm_framebuffer *fb,924 int color_plane,925 unsigned int rotation,926 unsigned int pitch,927 u32 old_offset, u32 new_offset)928{929 struct drm_i915_private *i915 = to_i915(fb->dev);930 unsigned int cpp = fb->format->cpp[color_plane];931 932 drm_WARN_ON(&i915->drm, new_offset > old_offset);933 934 if (!is_surface_linear(fb, color_plane)) {935 unsigned int tile_size, tile_width, tile_height;936 unsigned int pitch_tiles;937 938 tile_size = intel_tile_size(i915);939 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);940 941 if (drm_rotation_90_or_270(rotation)) {942 pitch_tiles = pitch / tile_height;943 swap(tile_width, tile_height);944 } else {945 pitch_tiles = pitch / (tile_width * cpp);946 }947 948 intel_adjust_tile_offset(x, y, tile_width, tile_height,949 tile_size, pitch_tiles,950 old_offset, new_offset);951 } else {952 intel_adjust_linear_offset(x, y, cpp, pitch,953 old_offset, new_offset);954 }955 956 return new_offset;957}958 959/*960 * Adjust the tile offset by moving the difference into961 * the x/y offsets.962 */963u32 intel_plane_adjust_aligned_offset(int *x, int *y,964 const struct intel_plane_state *state,965 int color_plane,966 u32 old_offset, u32 new_offset)967{968 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,969 state->hw.rotation,970 state->view.color_plane[color_plane].mapping_stride,971 old_offset, new_offset);972}973 974/*975 * Computes the aligned offset to the base tile and adjusts976 * x, y. bytes per pixel is assumed to be a power-of-two.977 *978 * In the 90/270 rotated case, x and y are assumed979 * to be already rotated to match the rotated GTT view, and980 * pitch is the tile_height aligned framebuffer height.981 *982 * This function is used when computing the derived information983 * under intel_framebuffer, so using any of that information984 * here is not allowed. Anything under drm_framebuffer can be985 * used. This is why the user has to pass in the pitch since it986 * is specified in the rotated orientation.987 */988static u32 intel_compute_aligned_offset(struct drm_i915_private *i915,989 int *x, int *y,990 const struct drm_framebuffer *fb,991 int color_plane,992 unsigned int pitch,993 unsigned int rotation,994 unsigned int alignment)995{996 unsigned int cpp = fb->format->cpp[color_plane];997 u32 offset, offset_aligned;998 999 if (!is_surface_linear(fb, color_plane)) {1000 unsigned int tile_size, tile_width, tile_height;1001 unsigned int tile_rows, tiles, pitch_tiles;1002 1003 tile_size = intel_tile_size(i915);1004 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);1005 1006 if (drm_rotation_90_or_270(rotation)) {1007 pitch_tiles = pitch / tile_height;1008 swap(tile_width, tile_height);1009 } else {1010 pitch_tiles = pitch / (tile_width * cpp);1011 }1012 1013 tile_rows = *y / tile_height;1014 *y %= tile_height;1015 1016 tiles = *x / tile_width;1017 *x %= tile_width;1018 1019 offset = (tile_rows * pitch_tiles + tiles) * tile_size;1020 1021 offset_aligned = offset;1022 if (alignment)1023 offset_aligned = rounddown(offset_aligned, alignment);1024 1025 intel_adjust_tile_offset(x, y, tile_width, tile_height,1026 tile_size, pitch_tiles,1027 offset, offset_aligned);1028 } else {1029 offset = *y * pitch + *x * cpp;1030 offset_aligned = offset;1031 if (alignment) {1032 offset_aligned = rounddown(offset_aligned, alignment);1033 *y = (offset % alignment) / pitch;1034 *x = ((offset % alignment) - *y * pitch) / cpp;1035 } else {1036 *y = *x = 0;1037 }1038 }1039 1040 return offset_aligned;1041}1042 1043u32 intel_plane_compute_aligned_offset(int *x, int *y,1044 const struct intel_plane_state *state,1045 int color_plane)1046{1047 struct intel_plane *plane = to_intel_plane(state->uapi.plane);1048 struct drm_i915_private *i915 = to_i915(plane->base.dev);1049 const struct drm_framebuffer *fb = state->hw.fb;1050 unsigned int rotation = state->hw.rotation;1051 unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;1052 unsigned int alignment = plane->min_alignment(plane, fb, color_plane);1053 1054 return intel_compute_aligned_offset(i915, x, y, fb, color_plane,1055 pitch, rotation, alignment);1056}1057 1058/* Convert the fb->offset[] into x/y offsets */1059static int intel_fb_offset_to_xy(int *x, int *y,1060 const struct drm_framebuffer *fb,1061 int color_plane)1062{1063 struct drm_i915_private *i915 = to_i915(fb->dev);1064 unsigned int height, alignment, unused;1065 1066 if (fb->modifier != DRM_FORMAT_MOD_LINEAR)1067 alignment = intel_tile_size(i915);1068 else1069 alignment = 0;1070 1071 if (alignment != 0 && fb->offsets[color_plane] % alignment) {1072 drm_dbg_kms(&i915->drm,1073 "Misaligned offset 0x%08x for color plane %d\n",1074 fb->offsets[color_plane], color_plane);1075 return -EINVAL;1076 }1077 1078 height = drm_format_info_plane_height(fb->format, fb->height, color_plane);1079 height = ALIGN(height, intel_tile_height(fb, color_plane));1080 1081 /* Catch potential overflows early */1082 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]),1083 fb->offsets[color_plane], &unused)) {1084 drm_dbg_kms(&i915->drm,1085 "Bad offset 0x%08x or pitch %d for color plane %d\n",1086 fb->offsets[color_plane], fb->pitches[color_plane],1087 color_plane);1088 return -ERANGE;1089 }1090 1091 *x = 0;1092 *y = 0;1093 1094 intel_adjust_aligned_offset(x, y,1095 fb, color_plane, DRM_MODE_ROTATE_0,1096 fb->pitches[color_plane],1097 fb->offsets[color_plane], 0);1098 1099 return 0;1100}1101 1102static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y)1103{1104 struct drm_i915_private *i915 = to_i915(fb->dev);1105 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);1106 int main_plane;1107 int hsub, vsub;1108 int tile_width, tile_height;1109 int ccs_x, ccs_y;1110 int main_x, main_y;1111 1112 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))1113 return 0;1114 1115 /*1116 * While all the tile dimensions are based on a 2k or 4k GTT page size1117 * here the main and CCS coordinates must match only within a (64 byte1118 * on TGL+) block inside the tile.1119 */1120 intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height);1121 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);1122 1123 tile_width *= hsub;1124 tile_height *= vsub;1125 1126 ccs_x = (x * hsub) % tile_width;1127 ccs_y = (y * vsub) % tile_height;1128 1129 main_plane = skl_ccs_to_main_plane(fb, ccs_plane);1130 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width;1131 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height;1132 1133 /*1134 * CCS doesn't have its own x/y offset register, so the intra CCS tile1135 * x/y offsets must match between CCS and the main surface.1136 */1137 if (main_x != ccs_x || main_y != ccs_y) {1138 drm_dbg_kms(&i915->drm,1139 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",1140 main_x, main_y,1141 ccs_x, ccs_y,1142 intel_fb->normal_view.color_plane[main_plane].x,1143 intel_fb->normal_view.color_plane[main_plane].y,1144 x, y);1145 return -EINVAL;1146 }1147 1148 return 0;1149}1150 1151static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)1152{1153 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);1154 struct drm_i915_private *i915 = to_i915(plane->base.dev);1155 const struct drm_framebuffer *fb = plane_state->hw.fb;1156 int i;1157 1158 /* We don't want to deal with remapping with cursors */1159 if (plane->id == PLANE_CURSOR)1160 return false;1161 1162 /*1163 * The display engine limits already match/exceed the1164 * render engine limits, so not much point in remapping.1165 * Would also need to deal with the fence POT alignment1166 * and gen2 2KiB GTT tile size.1167 */1168 if (DISPLAY_VER(i915) < 4)1169 return false;1170 1171 /*1172 * The new CCS hash mode isn't compatible with remapping as1173 * the virtual address of the pages affects the compressed data.1174 */1175 if (intel_fb_is_ccs_modifier(fb->modifier))1176 return false;1177 1178 /* Linear needs a page aligned stride for remapping */1179 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {1180 unsigned int alignment = intel_tile_size(i915) - 1;1181 1182 for (i = 0; i < fb->format->num_planes; i++) {1183 if (fb->pitches[i] & alignment)1184 return false;1185 }1186 }1187 1188 return true;1189}1190 1191bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)1192{1193 struct drm_i915_private *i915 = to_i915(fb->base.dev);1194 1195 return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&1196 intel_fb_uses_dpt(&fb->base);1197}1198 1199static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)1200{1201 if (drm_rotation_90_or_270(rotation))1202 return fb->rotated_view.color_plane[color_plane].mapping_stride;1203 else if (intel_fb_needs_pot_stride_remap(fb))1204 return fb->remapped_view.color_plane[color_plane].mapping_stride;1205 else1206 return fb->normal_view.color_plane[color_plane].mapping_stride;1207}1208 1209static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)1210{1211 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);1212 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);1213 unsigned int rotation = plane_state->hw.rotation;1214 u32 stride, max_stride;1215 1216 /*1217 * No remapping for invisible planes since we don't have1218 * an actual source viewport to remap.1219 */1220 if (!plane_state->uapi.visible)1221 return false;1222 1223 if (!intel_plane_can_remap(plane_state))1224 return false;1225 1226 /*1227 * FIXME: aux plane limits on gen9+ are1228 * unclear in Bspec, for now no checking.1229 */1230 stride = intel_fb_pitch(fb, 0, rotation);1231 max_stride = plane->max_stride(plane, fb->base.format->format,1232 fb->base.modifier, rotation);1233 1234 return stride > max_stride;1235}1236 1237static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane,1238 int plane_width, int *x, int *y)1239{1240 struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);1241 int ret;1242 1243 ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane);1244 if (ret) {1245 drm_dbg_kms(fb->base.dev,1246 "bad fb plane %d offset: 0x%x\n",1247 color_plane, fb->base.offsets[color_plane]);1248 return ret;1249 }1250 1251 ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y);1252 if (ret)1253 return ret;1254 1255 /*1256 * The fence (if used) is aligned to the start of the object1257 * so having the framebuffer wrap around across the edge of the1258 * fenced region doesn't really work. We have no API to configure1259 * the fence start offset within the object (nor could we probably1260 * on gen2/3). So it's just easier if we just require that the1261 * fb layout agrees with the fence layout. We already check that the1262 * fb stride matches the fence stride elsewhere.1263 */1264 if (color_plane == 0 && i915_gem_object_is_tiled(obj) &&1265 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) {1266 drm_dbg_kms(fb->base.dev,1267 "bad fb plane %d offset: 0x%x\n",1268 color_plane, fb->base.offsets[color_plane]);1269 return -EINVAL;1270 }1271 1272 return 0;1273}1274 1275static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)1276{1277 struct drm_i915_private *i915 = to_i915(fb->base.dev);1278 unsigned int tile_size = intel_tile_size(i915);1279 u32 offset;1280 1281 offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane,1282 fb->base.pitches[color_plane],1283 DRM_MODE_ROTATE_0,1284 tile_size);1285 1286 return offset / tile_size;1287}1288 1289struct fb_plane_view_dims {1290 unsigned int width, height;1291 unsigned int tile_width, tile_height;1292};1293 1294static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane,1295 unsigned int width, unsigned int height,1296 struct fb_plane_view_dims *dims)1297{1298 dims->width = width;1299 dims->height = height;1300 1301 intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height);1302}1303 1304static unsigned int1305plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane,1306 const struct fb_plane_view_dims *dims)1307{1308 return DIV_ROUND_UP(fb->base.pitches[color_plane],1309 dims->tile_width * fb->base.format->cpp[color_plane]);1310}1311 1312static unsigned int1313plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,1314 unsigned int pitch_tiles)1315{1316 if (intel_fb_needs_pot_stride_remap(fb)) {1317 /*1318 * ADL_P, the only platform needing a POT stride has a minimum1319 * of 8 main surface tiles.1320 */1321 return roundup_pow_of_two(max(pitch_tiles, 8u));1322 } else {1323 return pitch_tiles;1324 }1325}1326 1327static unsigned int1328plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,1329 unsigned int tile_width,1330 unsigned int src_stride_tiles, unsigned int dst_stride_tiles)1331{1332 struct drm_i915_private *i915 = to_i915(fb->base.dev);1333 unsigned int stride_tiles;1334 1335 if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&1336 src_stride_tiles < dst_stride_tiles)1337 stride_tiles = src_stride_tiles;1338 else1339 stride_tiles = dst_stride_tiles;1340 1341 return stride_tiles * tile_width * fb->base.format->cpp[color_plane];1342}1343 1344static unsigned int1345plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane,1346 const struct fb_plane_view_dims *dims,1347 int x)1348{1349 return DIV_ROUND_UP(x + dims->width, dims->tile_width);1350}1351 1352static unsigned int1353plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane,1354 const struct fb_plane_view_dims *dims,1355 int y)1356{1357 return DIV_ROUND_UP(y + dims->height, dims->tile_height);1358}1359 1360static unsigned int1361plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane,1362 const struct fb_plane_view_dims *dims,1363 int x, int y)1364{1365 struct drm_i915_private *i915 = to_i915(fb->base.dev);1366 unsigned int size;1367 1368 size = (y + dims->height) * fb->base.pitches[color_plane] +1369 x * fb->base.format->cpp[color_plane];1370 1371 return DIV_ROUND_UP(size, intel_tile_size(i915));1372}1373 1374#define assign_chk_ovf(i915, var, val) ({ \1375 drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \1376 (var) = (val); \1377})1378 1379#define assign_bfld_chk_ovf(i915, var, val) ({ \1380 (var) = (val); \1381 drm_WARN_ON(&(i915)->drm, (var) != (val)); \1382 (var); \1383})1384 1385static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,1386 const struct fb_plane_view_dims *dims,1387 u32 obj_offset, u32 gtt_offset, int x, int y,1388 struct intel_fb_view *view)1389{1390 struct drm_i915_private *i915 = to_i915(fb->base.dev);1391 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];1392 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane];1393 unsigned int tile_width = dims->tile_width;1394 unsigned int tile_height = dims->tile_height;1395 unsigned int tile_size = intel_tile_size(i915);1396 struct drm_rect r;1397 u32 size = 0;1398 1399 assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset);1400 1401 if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) {1402 remap_info->linear = 1;1403 1404 assign_chk_ovf(i915, remap_info->size,1405 plane_view_linear_tiles(fb, color_plane, dims, x, y));1406 } else {1407 remap_info->linear = 0;1408 1409 assign_chk_ovf(i915, remap_info->src_stride,1410 plane_view_src_stride_tiles(fb, color_plane, dims));1411 assign_chk_ovf(i915, remap_info->width,1412 plane_view_width_tiles(fb, color_plane, dims, x));1413 assign_chk_ovf(i915, remap_info->height,1414 plane_view_height_tiles(fb, color_plane, dims, y));1415 }1416 1417 if (view->gtt.type == I915_GTT_VIEW_ROTATED) {1418 drm_WARN_ON(&i915->drm, remap_info->linear);1419 check_array_bounds(i915, view->gtt.rotated.plane, color_plane);1420 1421 assign_chk_ovf(i915, remap_info->dst_stride,1422 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height));1423 1424 /* rotate the x/y offsets to match the GTT view */1425 drm_rect_init(&r, x, y, dims->width, dims->height);1426 drm_rect_rotate(&r,1427 remap_info->width * tile_width,1428 remap_info->height * tile_height,1429 DRM_MODE_ROTATE_270);1430 1431 color_plane_info->x = r.x1;1432 color_plane_info->y = r.y1;1433 1434 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height;1435 color_plane_info->scanout_stride = color_plane_info->mapping_stride;1436 1437 size += remap_info->dst_stride * remap_info->width;1438 1439 /* rotate the tile dimensions to match the GTT view */1440 swap(tile_width, tile_height);1441 } else {1442 drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);1443 1444 check_array_bounds(i915, view->gtt.remapped.plane, color_plane);1445 1446 if (view->gtt.remapped.plane_alignment) {1447 u32 aligned_offset = ALIGN(gtt_offset,1448 view->gtt.remapped.plane_alignment);1449 1450 size += aligned_offset - gtt_offset;1451 gtt_offset = aligned_offset;1452 }1453 1454 color_plane_info->x = x;1455 color_plane_info->y = y;1456 1457 if (remap_info->linear) {1458 color_plane_info->mapping_stride = fb->base.pitches[color_plane];1459 color_plane_info->scanout_stride = color_plane_info->mapping_stride;1460 1461 size += remap_info->size;1462 } else {1463 unsigned int dst_stride;1464 1465 /*1466 * The hardware automagically calculates the CCS AUX surface1467 * stride from the main surface stride so can't really remap a1468 * smaller subset (unless we'd remap in whole AUX page units).1469 */1470 if (intel_fb_needs_pot_stride_remap(fb) &&1471 intel_fb_is_ccs_modifier(fb->base.modifier))1472 dst_stride = remap_info->src_stride;1473 else1474 dst_stride = remap_info->width;1475 1476 dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride);1477 1478 assign_chk_ovf(i915, remap_info->dst_stride, dst_stride);1479 color_plane_info->mapping_stride = dst_stride *1480 tile_width *1481 fb->base.format->cpp[color_plane];1482 color_plane_info->scanout_stride =1483 plane_view_scanout_stride(fb, color_plane, tile_width,1484 remap_info->src_stride,1485 dst_stride);1486 1487 size += dst_stride * remap_info->height;1488 }1489 }1490 1491 /*1492 * We only keep the x/y offsets, so push all of the gtt offset into1493 * the x/y offsets. x,y will hold the first pixel of the framebuffer1494 * plane from the start of the remapped/rotated gtt mapping.1495 */1496 if (remap_info->linear)1497 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y,1498 fb->base.format->cpp[color_plane],1499 color_plane_info->mapping_stride,1500 gtt_offset * tile_size, 0);1501 else1502 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y,1503 tile_width, tile_height,1504 tile_size, remap_info->dst_stride,1505 gtt_offset * tile_size, 0);1506 1507 return size;1508}1509 1510#undef assign_chk_ovf1511 1512/* Return number of tiles @color_plane needs. */1513static unsigned int1514calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,1515 const struct fb_plane_view_dims *dims,1516 int x, int y)1517{1518 unsigned int tiles;1519 1520 if (is_surface_linear(&fb->base, color_plane)) {1521 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);1522 } else {1523 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *1524 plane_view_height_tiles(fb, color_plane, dims, y);1525 /*1526 * If the plane isn't horizontally tile aligned,1527 * we need one more tile.1528 */1529 if (x != 0)1530 tiles++;1531 }1532 1533 return tiles;1534}1535 1536static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view,1537 enum i915_gtt_view_type view_type)1538{1539 memset(view, 0, sizeof(*view));1540 view->gtt.type = view_type;1541 1542 if (view_type == I915_GTT_VIEW_REMAPPED &&1543 (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))1544 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;1545}1546 1547bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)1548{1549 if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)1550 return false;1551 1552 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||1553 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;1554}1555 1556static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb)1557{1558 struct drm_i915_private *i915 = to_i915(fb->dev);1559 struct intel_plane *plane;1560 unsigned int min_alignment = 0;1561 1562 for_each_intel_plane(&i915->drm, plane) {1563 unsigned int plane_min_alignment;1564 1565 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier))1566 continue;1567 1568 plane_min_alignment = plane->min_alignment(plane, fb, 0);1569 1570 drm_WARN_ON(&i915->drm, plane_min_alignment &&1571 !is_power_of_2(plane_min_alignment));1572 1573 if (intel_plane_needs_physical(plane))1574 continue;1575 1576 min_alignment = max(min_alignment, plane_min_alignment);1577 }1578 1579 return min_alignment;1580}1581 1582int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)1583{1584 struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);1585 u32 gtt_offset_rotated = 0;1586 u32 gtt_offset_remapped = 0;1587 unsigned int max_size = 0;1588 int i, num_planes = fb->base.format->num_planes;1589 unsigned int tile_size = intel_tile_size(i915);1590 1591 intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL);1592 1593 drm_WARN_ON(&i915->drm,1594 intel_fb_supports_90_270_rotation(fb) &&1595 intel_fb_needs_pot_stride_remap(fb));1596 1597 if (intel_fb_supports_90_270_rotation(fb))1598 intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED);1599 if (intel_fb_needs_pot_stride_remap(fb))1600 intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);1601 1602 for (i = 0; i < num_planes; i++) {1603 struct fb_plane_view_dims view_dims;1604 unsigned int width, height;1605 unsigned int size;1606 u32 offset;1607 int x, y;1608 int ret;1609 1610 /*1611 * Plane 2 of Render Compression with Clear Color fb modifier1612 * is consumed by the driver and not passed to DE. Skip the1613 * arithmetic related to alignment and offset calculation.1614 */1615 if (is_gen12_ccs_cc_plane(&fb->base, i)) {1616 if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))1617 continue;1618 else1619 return -EINVAL;1620 }1621 1622 intel_fb_plane_dims(fb, i, &width, &height);1623 1624 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);1625 if (ret)1626 return ret;1627 1628 init_plane_view_dims(fb, i, width, height, &view_dims);1629 1630 /*1631 * First pixel of the framebuffer from1632 * the start of the normal gtt mapping.1633 */1634 fb->normal_view.color_plane[i].x = x;1635 fb->normal_view.color_plane[i].y = y;1636 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i];1637 fb->normal_view.color_plane[i].scanout_stride =1638 fb->normal_view.color_plane[i].mapping_stride;1639 1640 offset = calc_plane_aligned_offset(fb, i, &x, &y);1641 1642 if (intel_fb_supports_90_270_rotation(fb))1643 gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,1644 offset, gtt_offset_rotated, x, y,1645 &fb->rotated_view);1646 1647 if (intel_fb_needs_pot_stride_remap(fb))1648 gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims,1649 offset, gtt_offset_remapped, x, y,1650 &fb->remapped_view);1651 1652 size = calc_plane_normal_size(fb, i, &view_dims, x, y);1653 /* how many tiles in total needed in the bo */1654 max_size = max(max_size, offset + size);1655 }1656 1657 if (mul_u32_u32(max_size, tile_size) > intel_bo_to_drm_bo(obj)->size) {1658 drm_dbg_kms(&i915->drm,1659 "fb too big for bo (need %llu bytes, have %zu bytes)\n",1660 mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)->size);1661 return -EINVAL;1662 }1663 1664 fb->min_alignment = intel_fb_min_alignment(&fb->base);1665 1666 return 0;1667}1668 1669static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)1670{1671 struct drm_i915_private *i915 =1672 to_i915(plane_state->uapi.plane->dev);1673 struct drm_framebuffer *fb = plane_state->hw.fb;1674 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);1675 unsigned int rotation = plane_state->hw.rotation;1676 int i, num_planes = fb->format->num_planes;1677 unsigned int src_x, src_y;1678 unsigned int src_w, src_h;1679 u32 gtt_offset = 0;1680 1681 intel_fb_view_init(i915, &plane_state->view,1682 drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED :1683 I915_GTT_VIEW_REMAPPED);1684 1685 src_x = plane_state->uapi.src.x1 >> 16;1686 src_y = plane_state->uapi.src.y1 >> 16;1687 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;1688 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;1689 1690 drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));1691 1692 /* Make src coordinates relative to the viewport */1693 drm_rect_translate(&plane_state->uapi.src,1694 -(src_x << 16), -(src_y << 16));1695 1696 /* Rotate src coordinates to match rotated GTT view */1697 if (drm_rotation_90_or_270(rotation))1698 drm_rect_rotate(&plane_state->uapi.src,1699 src_w << 16, src_h << 16,1700 DRM_MODE_ROTATE_270);1701 1702 for (i = 0; i < num_planes; i++) {1703 unsigned int hsub = i ? fb->format->hsub : 1;1704 unsigned int vsub = i ? fb->format->vsub : 1;1705 struct fb_plane_view_dims view_dims;1706 unsigned int width, height;1707 unsigned int x, y;1708 u32 offset;1709 1710 x = src_x / hsub;1711 y = src_y / vsub;1712 width = src_w / hsub;1713 height = src_h / vsub;1714 1715 init_plane_view_dims(intel_fb, i, width, height, &view_dims);1716 1717 /*1718 * First pixel of the src viewport from the1719 * start of the normal gtt mapping.1720 */1721 x += intel_fb->normal_view.color_plane[i].x;1722 y += intel_fb->normal_view.color_plane[i].y;1723 1724 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y);1725 1726 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims,1727 offset, gtt_offset, x, y,1728 &plane_state->view);1729 }1730}1731 1732void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,1733 struct intel_fb_view *view)1734{1735 if (drm_rotation_90_or_270(rotation))1736 *view = fb->rotated_view;1737 else if (intel_fb_needs_pot_stride_remap(fb))1738 *view = fb->remapped_view;1739 else1740 *view = fb->normal_view;1741}1742 1743static1744u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,1745 u32 pixel_format, u64 modifier)1746{1747 /*1748 * Arbitrary limit for gen4+ chosen to match the1749 * render engine max stride.1750 *1751 * The new CCS hash mode makes remapping impossible1752 */1753 if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||1754 intel_fb_modifier_uses_dpt(dev_priv, modifier))1755 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);1756 else if (DISPLAY_VER(dev_priv) >= 7)1757 return 256 * 1024;1758 else1759 return 128 * 1024;1760}1761 1762static unsigned int1763intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)1764{1765 struct drm_i915_private *dev_priv = to_i915(fb->dev);1766 unsigned int tile_width;1767 1768 if (is_surface_linear(fb, color_plane)) {1769 unsigned int max_stride = intel_plane_fb_max_stride(dev_priv,1770 fb->format->format,1771 fb->modifier);1772 1773 /*1774 * To make remapping with linear generally feasible1775 * we need the stride to be page aligned.1776 */1777 if (fb->pitches[color_plane] > max_stride &&1778 !intel_fb_is_ccs_modifier(fb->modifier))1779 return intel_tile_size(dev_priv);1780 else1781 return 64;1782 }1783 1784 tile_width = intel_tile_width_bytes(fb, color_plane);1785 if (intel_fb_is_ccs_modifier(fb->modifier)) {1786 /*1787 * On TGL the surface stride must be 4 tile aligned, mapped by1788 * one 64 byte cacheline on the CCS AUX surface.1789 */1790 if (DISPLAY_VER(dev_priv) >= 12)1791 tile_width *= 4;1792 /*1793 * Display WA #0531: skl,bxt,kbl,glk1794 *1795 * Render decompression and plane width > 38401796 * combined with horizontal panning requires the1797 * plane stride to be a multiple of 4. We'll just1798 * require the entire fb to accommodate that to avoid1799 * potential runtime errors at plane configuration time.1800 */1801 else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&1802 color_plane == 0 && fb->width > 3840)1803 tile_width *= 4;1804 }1805 return tile_width;1806}1807 1808static int intel_plane_check_stride(const struct intel_plane_state *plane_state)1809{1810 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);1811 const struct drm_framebuffer *fb = plane_state->hw.fb;1812 unsigned int rotation = plane_state->hw.rotation;1813 u32 stride, max_stride;1814 1815 /*1816 * We ignore stride for all invisible planes that1817 * can be remapped. Otherwise we could end up1818 * with a false positive when the remapping didn't1819 * kick in due the plane being invisible.1820 */1821 if (intel_plane_can_remap(plane_state) &&1822 !plane_state->uapi.visible)1823 return 0;1824 1825 /* FIXME other color planes? */1826 stride = plane_state->view.color_plane[0].mapping_stride;1827 max_stride = plane->max_stride(plane, fb->format->format,1828 fb->modifier, rotation);1829 1830 if (stride > max_stride) {1831 drm_dbg_kms(plane->base.dev,1832 "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",1833 fb->base.id, stride,1834 plane->base.base.id, plane->base.name, max_stride);1835 return -EINVAL;1836 }1837 1838 return 0;1839}1840 1841int intel_plane_compute_gtt(struct intel_plane_state *plane_state)1842{1843 const struct intel_framebuffer *fb =1844 to_intel_framebuffer(plane_state->hw.fb);1845 unsigned int rotation = plane_state->hw.rotation;1846 1847 if (!fb)1848 return 0;1849 1850 if (intel_plane_needs_remap(plane_state)) {1851 intel_plane_remap_gtt(plane_state);1852 1853 /*1854 * Sometimes even remapping can't overcome1855 * the stride limitations :( Can happen with1856 * big plane sizes and suitably misaligned1857 * offsets.1858 */1859 return intel_plane_check_stride(plane_state);1860 }1861 1862 intel_fb_fill_view(fb, rotation, &plane_state->view);1863 1864 /* Rotate src coordinates to match rotated GTT view */1865 if (drm_rotation_90_or_270(rotation))1866 drm_rect_rotate(&plane_state->uapi.src,1867 fb->base.width << 16, fb->base.height << 16,1868 DRM_MODE_ROTATE_270);1869 1870 return intel_plane_check_stride(plane_state);1871}1872 1873static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)1874{1875 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);1876 1877 drm_framebuffer_cleanup(fb);1878 1879 if (intel_fb_uses_dpt(fb))1880 intel_dpt_destroy(intel_fb->dpt_vm);1881 1882 intel_frontbuffer_put(intel_fb->frontbuffer);1883 1884 intel_fb_bo_framebuffer_fini(intel_fb_obj(fb));1885 1886 kfree(intel_fb);1887}1888 1889static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,1890 struct drm_file *file,1891 unsigned int *handle)1892{1893 struct drm_i915_gem_object *obj = intel_fb_obj(fb);1894 struct drm_i915_private *i915 = to_i915(intel_bo_to_drm_bo(obj)->dev);1895 1896 if (i915_gem_object_is_userptr(obj)) {1897 drm_dbg(&i915->drm,1898 "attempting to use a userptr for a framebuffer, denied\n");1899 return -EINVAL;1900 }1901 1902 return drm_gem_handle_create(file, intel_bo_to_drm_bo(obj), handle);1903}1904 1905struct frontbuffer_fence_cb {1906 struct dma_fence_cb base;1907 struct intel_frontbuffer *front;1908};1909 1910static void intel_user_framebuffer_fence_wake(struct dma_fence *dma,1911 struct dma_fence_cb *data)1912{1913 struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base);1914 1915 intel_frontbuffer_queue_flush(cb->front);1916 kfree(cb);1917 dma_fence_put(dma);1918}1919 1920static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,1921 struct drm_file *file,1922 unsigned int flags, unsigned int color,1923 struct drm_clip_rect *clips,1924 unsigned int num_clips)1925{1926 struct drm_i915_gem_object *obj = intel_fb_obj(fb);1927 struct intel_frontbuffer *front = to_intel_frontbuffer(fb);1928 struct dma_fence *fence;1929 struct frontbuffer_fence_cb *cb;1930 int ret = 0;1931 1932 if (!atomic_read(&front->bits))1933 return 0;1934 1935 if (dma_resv_test_signaled(intel_bo_to_drm_bo(obj)->resv, dma_resv_usage_rw(false)))1936 goto flush;1937 1938 ret = dma_resv_get_singleton(intel_bo_to_drm_bo(obj)->resv, dma_resv_usage_rw(false),1939 &fence);1940 if (ret || !fence)1941 goto flush;1942 1943 cb = kmalloc(sizeof(*cb), GFP_KERNEL);1944 if (!cb) {1945 dma_fence_put(fence);1946 ret = -ENOMEM;1947 goto flush;1948 }1949 1950 cb->front = front;1951 1952 intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB);1953 1954 ret = dma_fence_add_callback(fence, &cb->base,1955 intel_user_framebuffer_fence_wake);1956 if (ret) {1957 intel_user_framebuffer_fence_wake(fence, &cb->base);1958 if (ret == -ENOENT)1959 ret = 0;1960 }1961 1962 return ret;1963 1964flush:1965 i915_gem_object_flush_if_display(obj);1966 intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);1967 return ret;1968}1969 1970static const struct drm_framebuffer_funcs intel_fb_funcs = {1971 .destroy = intel_user_framebuffer_destroy,1972 .create_handle = intel_user_framebuffer_create_handle,1973 .dirty = intel_user_framebuffer_dirty,1974};1975 1976int intel_framebuffer_init(struct intel_framebuffer *intel_fb,1977 struct drm_i915_gem_object *obj,1978 struct drm_mode_fb_cmd2 *mode_cmd)1979{1980 struct drm_i915_private *dev_priv = to_i915(intel_bo_to_drm_bo(obj)->dev);1981 struct drm_framebuffer *fb = &intel_fb->base;1982 u32 max_stride;1983 int ret = -EINVAL;1984 int i;1985 1986 ret = intel_fb_bo_framebuffer_init(intel_fb, obj, mode_cmd);1987 if (ret)1988 return ret;1989 1990 intel_fb->frontbuffer = intel_frontbuffer_get(obj);1991 if (!intel_fb->frontbuffer) {1992 ret = -ENOMEM;1993 goto err;1994 }1995 1996 ret = -EINVAL;1997 if (!drm_any_plane_has_format(&dev_priv->drm,1998 mode_cmd->pixel_format,1999 mode_cmd->modifier[0])) {2000 drm_dbg_kms(&dev_priv->drm,2001 "unsupported pixel format %p4cc / modifier 0x%llx\n",2002 &mode_cmd->pixel_format, mode_cmd->modifier[0]);2003 goto err_frontbuffer_put;2004 }2005 2006 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,2007 mode_cmd->modifier[0]);2008 if (mode_cmd->pitches[0] > max_stride) {2009 drm_dbg_kms(&dev_priv->drm,2010 "%s pitch (%u) must be at most %d\n",2011 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?2012 "tiled" : "linear",2013 mode_cmd->pitches[0], max_stride);2014 goto err_frontbuffer_put;2015 }2016 2017 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */2018 if (mode_cmd->offsets[0] != 0) {2019 drm_dbg_kms(&dev_priv->drm,2020 "plane 0 offset (0x%08x) must be 0\n",2021 mode_cmd->offsets[0]);2022 goto err_frontbuffer_put;2023 }2024 2025 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);2026 2027 for (i = 0; i < fb->format->num_planes; i++) {2028 unsigned int stride_alignment;2029 2030 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {2031 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",2032 i);2033 goto err_frontbuffer_put;2034 }2035 2036 stride_alignment = intel_fb_stride_alignment(fb, i);2037 if (fb->pitches[i] & (stride_alignment - 1)) {2038 drm_dbg_kms(&dev_priv->drm,2039 "plane %d pitch (%d) must be at least %u byte aligned\n",2040 i, fb->pitches[i], stride_alignment);2041 goto err_frontbuffer_put;2042 }2043 2044 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {2045 unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);2046 2047 if (fb->pitches[i] != ccs_aux_stride) {2048 drm_dbg_kms(&dev_priv->drm,2049 "ccs aux plane %d pitch (%d) must be %d\n",2050 i,2051 fb->pitches[i], ccs_aux_stride);2052 goto err_frontbuffer_put;2053 }2054 }2055 2056 fb->obj[i] = intel_bo_to_drm_bo(obj);2057 }2058 2059 ret = intel_fill_fb_info(dev_priv, intel_fb);2060 if (ret)2061 goto err_frontbuffer_put;2062 2063 if (intel_fb_uses_dpt(fb)) {2064 struct i915_address_space *vm;2065 2066 vm = intel_dpt_create(intel_fb);2067 if (IS_ERR(vm)) {2068 drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n");2069 ret = PTR_ERR(vm);2070 goto err_frontbuffer_put;2071 }2072 2073 intel_fb->dpt_vm = vm;2074 }2075 2076 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);2077 if (ret) {2078 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);2079 goto err_free_dpt;2080 }2081 2082 return 0;2083 2084err_free_dpt:2085 if (intel_fb_uses_dpt(fb))2086 intel_dpt_destroy(intel_fb->dpt_vm);2087err_frontbuffer_put:2088 intel_frontbuffer_put(intel_fb->frontbuffer);2089err:2090 intel_fb_bo_framebuffer_fini(obj);2091 return ret;2092}2093 2094struct drm_framebuffer *2095intel_user_framebuffer_create(struct drm_device *dev,2096 struct drm_file *filp,2097 const struct drm_mode_fb_cmd2 *user_mode_cmd)2098{2099 struct drm_framebuffer *fb;2100 struct drm_i915_gem_object *obj;2101 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;2102 struct drm_i915_private *i915 = to_i915(dev);2103 2104 obj = intel_fb_bo_lookup_valid_bo(i915, filp, &mode_cmd);2105 if (IS_ERR(obj))2106 return ERR_CAST(obj);2107 2108 fb = intel_framebuffer_create(obj, &mode_cmd);2109 drm_gem_object_put(intel_bo_to_drm_bo(obj));2110 2111 return fb;2112}2113 2114struct drm_framebuffer *2115intel_framebuffer_create(struct drm_i915_gem_object *obj,2116 struct drm_mode_fb_cmd2 *mode_cmd)2117{2118 struct intel_framebuffer *intel_fb;2119 int ret;2120 2121 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);2122 if (!intel_fb)2123 return ERR_PTR(-ENOMEM);2124 2125 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);2126 if (ret)2127 goto err;2128 2129 return &intel_fb->base;2130 2131err:2132 kfree(intel_fb);2133 return ERR_PTR(ret);2134}2135