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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2019 Intel Corporation4 */5 6#ifndef __INTEL_GMBUS_H__7#define __INTEL_GMBUS_H__8 9#include <linux/types.h>10 11struct drm_i915_private;12struct i2c_adapter;13 14#define GMBUS_PIN_DISABLED 015#define GMBUS_PIN_SSC 116#define GMBUS_PIN_VGADDC 217#define GMBUS_PIN_PANEL 318#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */19#define GMBUS_PIN_DPC 4 /* HDMIC */20#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */21#define GMBUS_PIN_DPD 6 /* HDMID */22#define GMBUS_PIN_RESERVED 7 /* 7 reserved */23#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */24#define GMBUS_PIN_2_BXT 225#define GMBUS_PIN_3_BXT 326#define GMBUS_PIN_4_CNP 427#define GMBUS_PIN_5_MTP 528#define GMBUS_PIN_9_TC1_ICP 929#define GMBUS_PIN_10_TC2_ICP 1030#define GMBUS_PIN_11_TC3_ICP 1131#define GMBUS_PIN_12_TC4_ICP 1232#define GMBUS_PIN_13_TC5_TGP 1333#define GMBUS_PIN_14_TC6_TGP 1434 35#define GMBUS_NUM_PINS 15 /* including 0 */36 37int intel_gmbus_setup(struct drm_i915_private *dev_priv);38void intel_gmbus_teardown(struct drm_i915_private *dev_priv);39bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,40 unsigned int pin);41int intel_gmbus_output_aksv(struct i2c_adapter *adapter);42 43struct i2c_adapter *44intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);45void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);46bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);47void intel_gmbus_reset(struct drm_i915_private *dev_priv);48 49void intel_gmbus_irq_handler(struct drm_i915_private *i915);50 51#endif /* __INTEL_GMBUS_H__ */52