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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2022 Intel Corporation4 */5 6#ifndef __INTEL_MG_PHY_REGS__7#define __INTEL_MG_PHY_REGS__8 9#include "intel_display_reg_defs.h"10 11#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \12 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))13 14#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C15#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C16#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C17#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C18#define MG_TX1_LINK_PARAMS(ln, tc_port) \19 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \20 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \21 MG_TX_LINK_PARAMS_TX1LN1_PORT1)22 23#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC24#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC25#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC26#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC27#define MG_TX2_LINK_PARAMS(ln, tc_port) \28 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \29 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \30 MG_TX_LINK_PARAMS_TX2LN1_PORT1)31#define CRI_USE_FS32 (1 << 5)32 33#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C34#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C35#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C36#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C37#define MG_TX1_PISO_READLOAD(ln, tc_port) \38 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \39 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \40 MG_TX_PISO_READLOAD_TX1LN1_PORT1)41 42#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC43#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC44#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC45#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC46#define MG_TX2_PISO_READLOAD(ln, tc_port) \47 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \48 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \49 MG_TX_PISO_READLOAD_TX2LN1_PORT1)50#define CRI_CALCINIT (1 << 1)51 52#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x16814853#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x16854854#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x16914855#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x16954856#define MG_TX1_SWINGCTRL(ln, tc_port) \57 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \58 MG_TX_SWINGCTRL_TX1LN0_PORT2, \59 MG_TX_SWINGCTRL_TX1LN1_PORT1)60 61#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C862#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C863#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C864#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C865#define MG_TX2_SWINGCTRL(ln, tc_port) \66 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \67 MG_TX_SWINGCTRL_TX2LN0_PORT2, \68 MG_TX_SWINGCTRL_TX2LN1_PORT1)69#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)70#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)71 72#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x16814473#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x16854474#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x16914475#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x16954476#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A14477#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A54478#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B14479#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B54480#define MG_TX1_DRVCTRL(ln, tc_port) \81 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \82 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \83 MG_TX_DRVCTRL_TX1LN1_TXPORT1)84 85#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C486#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C487#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C488#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C489#define MG_TX2_DRVCTRL(ln, tc_port) \90 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \91 MG_TX_DRVCTRL_TX2LN0_PORT2, \92 MG_TX_DRVCTRL_TX2LN1_PORT1)93#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)94#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)95#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)96#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)97#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)98#define CRI_LOADGEN_SEL(x) ((x) << 12)99#define CRI_LOADGEN_SEL_MASK (0x3 << 12)100 101#define MG_CLKHUB_LN0_PORT1 0x16839C102#define MG_CLKHUB_LN1_PORT1 0x16879C103#define MG_CLKHUB_LN0_PORT2 0x16939C104#define MG_CLKHUB_LN1_PORT2 0x16979C105#define MG_CLKHUB(ln, tc_port) \106 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \107 MG_CLKHUB_LN0_PORT2, \108 MG_CLKHUB_LN1_PORT1)109#define CFG_LOW_RATE_LKREN_EN (1 << 11)110 111#define MG_TX_DCC_TX1LN0_PORT1 0x168110112#define MG_TX_DCC_TX1LN1_PORT1 0x168510113#define MG_TX_DCC_TX1LN0_PORT2 0x169110114#define MG_TX_DCC_TX1LN1_PORT2 0x169510115#define MG_TX1_DCC(ln, tc_port) \116 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \117 MG_TX_DCC_TX1LN0_PORT2, \118 MG_TX_DCC_TX1LN1_PORT1)119#define MG_TX_DCC_TX2LN0_PORT1 0x168090120#define MG_TX_DCC_TX2LN1_PORT1 0x168490121#define MG_TX_DCC_TX2LN0_PORT2 0x169090122#define MG_TX_DCC_TX2LN1_PORT2 0x169490123#define MG_TX2_DCC(ln, tc_port) \124 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \125 MG_TX_DCC_TX2LN0_PORT2, \126 MG_TX_DCC_TX2LN1_PORT1)127#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)128#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)129#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)130 131#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0132#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0133#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0134#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0135#define MG_DP_MODE(ln, tc_port) \136 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \137 MG_DP_MODE_LN0_ACU_PORT2, \138 MG_DP_MODE_LN1_ACU_PORT1)139#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)140#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)141 142#define FIA1_BASE 0x163000143#define FIA2_BASE 0x16E000144#define FIA3_BASE 0x16F000145#define _FIA(fia) _PICK_EVEN_2RANGES((fia), 1, \146 FIA1_BASE, FIA1_BASE,\147 FIA2_BASE, FIA3_BASE)148#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))149 150/* ICL PHY DFLEX registers */151#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)152#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))153#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))154#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))155#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))156#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))157#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))158 159#define _MG_REFCLKIN_CTL_PORT1 0x16892C160#define _MG_REFCLKIN_CTL_PORT2 0x16992C161#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)162#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)163#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \164 _MG_REFCLKIN_CTL_PORT1, \165 _MG_REFCLKIN_CTL_PORT2)166 167#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8168#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8169#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)170#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)171#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)172#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)173#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \174 _MG_CLKTOP2_CORECLKCTL1_PORT1, \175 _MG_CLKTOP2_CORECLKCTL1_PORT2)176 177#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4178#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4179#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)180#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)181#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)182#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)183#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)184#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)185#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)186#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)187#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)188#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)189#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8190#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)191#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \192 _MG_CLKTOP2_HSCLKCTL_PORT1, \193 _MG_CLKTOP2_HSCLKCTL_PORT2)194 195#define _MG_PLL_DIV0_PORT1 0x168A00196#define _MG_PLL_DIV0_PORT2 0x169A00197#define MG_PLL_DIV0_FRACNEN_H (1 << 30)198#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)199#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8200#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)201#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)202#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)203#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \204 _MG_PLL_DIV0_PORT2)205 206#define _MG_PLL_DIV1_PORT1 0x168A04207#define _MG_PLL_DIV1_PORT2 0x169A04208#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)209#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)210#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)211#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)212#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)213#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)214#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)215#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)216#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \217 _MG_PLL_DIV1_PORT2)218 219#define _MG_PLL_LF_PORT1 0x168A08220#define _MG_PLL_LF_PORT2 0x169A08221#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)222#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)223#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)224#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)225#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)226#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)227#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \228 _MG_PLL_LF_PORT2)229 230#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C231#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C232#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)233#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)234#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)235#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)236#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)237#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)238#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \239 _MG_PLL_FRAC_LOCK_PORT1, \240 _MG_PLL_FRAC_LOCK_PORT2)241 242#define _MG_PLL_SSC_PORT1 0x168A10243#define _MG_PLL_SSC_PORT2 0x169A10244#define MG_PLL_SSC_EN (1 << 28)245#define MG_PLL_SSC_TYPE(x) ((x) << 26)246#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)247#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)248#define MG_PLL_SSC_FLLEN (1 << 9)249#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)250#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \251 _MG_PLL_SSC_PORT2)252 253#define _MG_PLL_BIAS_PORT1 0x168A14254#define _MG_PLL_BIAS_PORT2 0x169A14255#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)256#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)257#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)258#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)259#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)260#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)261#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)262#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)263#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)264#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)265#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)266#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)267#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)268#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \269 _MG_PLL_BIAS_PORT2)270 271#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18272#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18273#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)274#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)275#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)276#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)277#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)278#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \279 _MG_PLL_TDC_COLDST_BIAS_PORT1, \280 _MG_PLL_TDC_COLDST_BIAS_PORT2)281 282#endif /* __INTEL_MG_PHY_REGS__ */283