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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2021 Intel Corporation4 */5 6#include "g4x_dp.h"7#include "i915_reg.h"8#include "intel_crt.h"9#include "intel_de.h"10#include "intel_display_types.h"11#include "intel_dpll.h"12#include "intel_fdi.h"13#include "intel_fdi_regs.h"14#include "intel_lvds.h"15#include "intel_lvds_regs.h"16#include "intel_pch_display.h"17#include "intel_pch_refclk.h"18#include "intel_pps.h"19#include "intel_sdvo.h"20 21bool intel_has_pch_trancoder(struct drm_i915_private *i915,22 enum pipe pch_transcoder)23{24 return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) ||25 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A);26}27 28enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)29{30 struct drm_i915_private *i915 = to_i915(crtc->base.dev);31 32 if (HAS_PCH_LPT(i915))33 return PIPE_A;34 else35 return crtc->pipe;36}37 38static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,39 enum pipe pipe, enum port port,40 i915_reg_t dp_reg)41{42 enum pipe port_pipe;43 bool state;44 45 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);46 47 I915_STATE_WARN(dev_priv, state && port_pipe == pipe,48 "PCH DP %c enabled on transcoder %c, should be disabled\n",49 port_name(port), pipe_name(pipe));50 51 I915_STATE_WARN(dev_priv,52 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,53 "IBX PCH DP %c still using transcoder B\n",54 port_name(port));55}56 57static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,58 enum pipe pipe, enum port port,59 i915_reg_t hdmi_reg)60{61 enum pipe port_pipe;62 bool state;63 64 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);65 66 I915_STATE_WARN(dev_priv, state && port_pipe == pipe,67 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",68 port_name(port), pipe_name(pipe));69 70 I915_STATE_WARN(dev_priv,71 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,72 "IBX PCH HDMI %c still using transcoder B\n",73 port_name(port));74}75 76static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,77 enum pipe pipe)78{79 enum pipe port_pipe;80 81 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);82 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);83 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);84 85 I915_STATE_WARN(dev_priv,86 intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,87 "PCH VGA enabled on transcoder %c, should be disabled\n",88 pipe_name(pipe));89 90 I915_STATE_WARN(dev_priv,91 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe,92 "PCH LVDS enabled on transcoder %c, should be disabled\n",93 pipe_name(pipe));94 95 /* PCH SDVOB multiplex with HDMIB */96 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);97 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);98 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);99}100 101static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,102 enum pipe pipe)103{104 u32 val;105 bool enabled;106 107 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));108 enabled = !!(val & TRANS_ENABLE);109 I915_STATE_WARN(dev_priv, enabled,110 "transcoder assertion failed, should be off on pipe %c but is still active\n",111 pipe_name(pipe));112}113 114static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,115 enum port port, i915_reg_t hdmi_reg)116{117 u32 val = intel_de_read(dev_priv, hdmi_reg);118 119 if (val & SDVO_ENABLE ||120 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))121 return;122 123 drm_dbg_kms(&dev_priv->drm,124 "Sanitizing transcoder select for HDMI %c\n",125 port_name(port));126 127 val &= ~SDVO_PIPE_SEL_MASK;128 val |= SDVO_PIPE_SEL(PIPE_A);129 130 intel_de_write(dev_priv, hdmi_reg, val);131}132 133static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,134 enum port port, i915_reg_t dp_reg)135{136 u32 val = intel_de_read(dev_priv, dp_reg);137 138 if (val & DP_PORT_EN ||139 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))140 return;141 142 drm_dbg_kms(&dev_priv->drm,143 "Sanitizing transcoder select for DP %c\n",144 port_name(port));145 146 val &= ~DP_PIPE_SEL_MASK;147 val |= DP_PIPE_SEL(PIPE_A);148 149 intel_de_write(dev_priv, dp_reg, val);150}151 152static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)153{154 /*155 * The BIOS may select transcoder B on some of the PCH156 * ports even it doesn't enable the port. This would trip157 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().158 * Sanitize the transcoder select bits to prevent that. We159 * assume that the BIOS never actually enabled the port,160 * because if it did we'd actually have to toggle the port161 * on and back off to make the transcoder A select stick162 * (see. intel_dp_link_down(), intel_disable_hdmi(),163 * intel_disable_sdvo()).164 */165 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);166 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);167 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);168 169 /* PCH SDVOB multiplex with HDMIB */170 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);171 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);172 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);173}174 175static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,176 const struct intel_link_m_n *m_n)177{178 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);179 enum pipe pipe = crtc->pipe;180 181 intel_set_m_n(dev_priv, m_n,182 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),183 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));184}185 186static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,187 const struct intel_link_m_n *m_n)188{189 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);190 enum pipe pipe = crtc->pipe;191 192 intel_set_m_n(dev_priv, m_n,193 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),194 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));195}196 197void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,198 struct intel_link_m_n *m_n)199{200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);201 enum pipe pipe = crtc->pipe;202 203 intel_get_m_n(dev_priv, m_n,204 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),205 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));206}207 208void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,209 struct intel_link_m_n *m_n)210{211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);212 enum pipe pipe = crtc->pipe;213 214 intel_get_m_n(dev_priv, m_n,215 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),216 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));217}218 219static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,220 enum pipe pch_transcoder)221{222 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);224 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;225 226 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),227 intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));228 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),229 intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));230 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),231 intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));232 233 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),234 intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));235 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),236 intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));237 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),238 intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));239 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),240 intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder)));241}242 243static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)244{245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);246 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);247 enum pipe pipe = crtc->pipe;248 i915_reg_t reg;249 u32 val, pipeconf_val;250 251 /* Make sure PCH DPLL is enabled */252 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);253 254 /* FDI must be feeding us bits for PCH ports */255 assert_fdi_tx_enabled(dev_priv, pipe);256 assert_fdi_rx_enabled(dev_priv, pipe);257 258 if (HAS_PCH_CPT(dev_priv)) {259 reg = TRANS_CHICKEN2(pipe);260 val = intel_de_read(dev_priv, reg);261 /*262 * Workaround: Set the timing override bit263 * before enabling the pch transcoder.264 */265 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;266 /* Configure frame start delay to match the CPU */267 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;268 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);269 intel_de_write(dev_priv, reg, val);270 }271 272 reg = PCH_TRANSCONF(pipe);273 val = intel_de_read(dev_priv, reg);274 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));275 276 if (HAS_PCH_IBX(dev_priv)) {277 /* Configure frame start delay to match the CPU */278 val &= ~TRANS_FRAME_START_DELAY_MASK;279 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);280 281 /*282 * Make the BPC in transcoder be consistent with283 * that in pipeconf reg. For HDMI we must use 8bpc284 * here for both 8bpc and 12bpc.285 */286 val &= ~TRANSCONF_BPC_MASK;287 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))288 val |= TRANSCONF_BPC_8;289 else290 val |= pipeconf_val & TRANSCONF_BPC_MASK;291 }292 293 val &= ~TRANS_INTERLACE_MASK;294 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {295 if (HAS_PCH_IBX(dev_priv) &&296 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))297 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;298 else299 val |= TRANS_INTERLACE_INTERLACED;300 } else {301 val |= TRANS_INTERLACE_PROGRESSIVE;302 }303 304 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);305 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))306 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",307 pipe_name(pipe));308}309 310static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)311{312 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);313 enum pipe pipe = crtc->pipe;314 i915_reg_t reg;315 316 /* FDI relies on the transcoder */317 assert_fdi_tx_disabled(dev_priv, pipe);318 assert_fdi_rx_disabled(dev_priv, pipe);319 320 /* Ports must be off as well */321 assert_pch_ports_disabled(dev_priv, pipe);322 323 reg = PCH_TRANSCONF(pipe);324 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0);325 /* wait for PCH transcoder off, transcoder state */326 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))327 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",328 pipe_name(pipe));329 330 if (HAS_PCH_CPT(dev_priv))331 /* Workaround: Clear the timing override chicken bit again. */332 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe),333 TRANS_CHICKEN2_TIMING_OVERRIDE, 0);334}335 336void ilk_pch_pre_enable(struct intel_atomic_state *state,337 struct intel_crtc *crtc)338{339 const struct intel_crtc_state *crtc_state =340 intel_atomic_get_new_crtc_state(state, crtc);341 342 /*343 * Note: FDI PLL enabling _must_ be done before we enable the344 * cpu pipes, hence this is separate from all the other fdi/pch345 * enabling.346 */347 ilk_fdi_pll_enable(crtc_state);348}349 350/*351 * Enable PCH resources required for PCH ports:352 * - PCH PLLs353 * - FDI training & RX/TX354 * - update transcoder timings355 * - DP transcoding bits356 * - transcoder357 */358void ilk_pch_enable(struct intel_atomic_state *state,359 struct intel_crtc *crtc)360{361 struct intel_display *display = to_intel_display(state);362 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);363 const struct intel_crtc_state *crtc_state =364 intel_atomic_get_new_crtc_state(state, crtc);365 enum pipe pipe = crtc->pipe;366 u32 temp;367 368 assert_pch_transcoder_disabled(dev_priv, pipe);369 370 /* For PCH output, training FDI link */371 intel_fdi_link_train(crtc, crtc_state);372 373 /*374 * We need to program the right clock selection375 * before writing the pixel multiplier into the DPLL.376 */377 if (HAS_PCH_CPT(dev_priv)) {378 u32 sel;379 380 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);381 temp |= TRANS_DPLL_ENABLE(pipe);382 sel = TRANS_DPLLB_SEL(pipe);383 if (crtc_state->shared_dpll ==384 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))385 temp |= sel;386 else387 temp &= ~sel;388 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);389 }390 391 /*392 * XXX: pch pll's can be enabled any time before we enable the PCH393 * transcoder, and we actually should do this to not upset any PCH394 * transcoder that already use the clock when we share it.395 *396 * Note that enable_shared_dpll tries to do the right thing, but397 * get_shared_dpll unconditionally resets the pll - we need that398 * to have the right LVDS enable sequence.399 */400 intel_enable_shared_dpll(crtc_state);401 402 /* set transcoder timing, panel must allow it */403 assert_pps_unlocked(display, pipe);404 if (intel_crtc_has_dp_encoder(crtc_state)) {405 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);406 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);407 }408 ilk_pch_transcoder_set_timings(crtc_state, pipe);409 410 intel_fdi_normal_train(crtc);411 412 /* For PCH DP, enable TRANS_DP_CTL */413 if (HAS_PCH_CPT(dev_priv) &&414 intel_crtc_has_dp_encoder(crtc_state)) {415 const struct drm_display_mode *adjusted_mode =416 &crtc_state->hw.adjusted_mode;417 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;418 i915_reg_t reg = TRANS_DP_CTL(pipe);419 enum port port;420 421 temp = intel_de_read(dev_priv, reg);422 temp &= ~(TRANS_DP_PORT_SEL_MASK |423 TRANS_DP_VSYNC_ACTIVE_HIGH |424 TRANS_DP_HSYNC_ACTIVE_HIGH |425 TRANS_DP_BPC_MASK);426 temp |= TRANS_DP_OUTPUT_ENABLE;427 temp |= bpc << 9; /* same format but at 11:9 */428 429 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)430 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;431 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)432 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;433 434 port = intel_get_crtc_new_encoder(state, crtc_state)->port;435 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);436 temp |= TRANS_DP_PORT_SEL(port);437 438 intel_de_write(dev_priv, reg, temp);439 }440 441 ilk_enable_pch_transcoder(crtc_state);442}443 444void ilk_pch_disable(struct intel_atomic_state *state,445 struct intel_crtc *crtc)446{447 ilk_fdi_disable(crtc);448}449 450void ilk_pch_post_disable(struct intel_atomic_state *state,451 struct intel_crtc *crtc)452{453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);454 enum pipe pipe = crtc->pipe;455 456 ilk_disable_pch_transcoder(crtc);457 458 if (HAS_PCH_CPT(dev_priv)) {459 /* disable TRANS_DP_CTL */460 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe),461 TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,462 TRANS_DP_PORT_SEL_NONE);463 464 /* disable DPLL_SEL */465 intel_de_rmw(dev_priv, PCH_DPLL_SEL,466 TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);467 }468 469 ilk_fdi_pll_disable(crtc);470}471 472static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)473{474 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);476 477 /* read out port_clock from the DPLL */478 i9xx_crtc_clock_get(crtc_state);479 480 /*481 * In case there is an active pipe without active ports,482 * we may need some idea for the dotclock anyway.483 * Calculate one based on the FDI configuration.484 */485 crtc_state->hw.adjusted_mode.crtc_clock =486 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),487 &crtc_state->fdi_m_n);488}489 490void ilk_pch_get_config(struct intel_crtc_state *crtc_state)491{492 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);493 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);494 struct intel_shared_dpll *pll;495 enum pipe pipe = crtc->pipe;496 enum intel_dpll_id pll_id;497 bool pll_active;498 u32 tmp;499 500 if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)501 return;502 503 crtc_state->has_pch_encoder = true;504 505 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));506 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>507 FDI_DP_PORT_WIDTH_SHIFT) + 1;508 509 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,510 &crtc_state->fdi_m_n);511 512 if (HAS_PCH_IBX(dev_priv)) {513 /*514 * The pipe->pch transcoder and pch transcoder->pll515 * mapping is fixed.516 */517 pll_id = (enum intel_dpll_id) pipe;518 } else {519 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);520 if (tmp & TRANS_DPLLB_SEL(pipe))521 pll_id = DPLL_ID_PCH_PLL_B;522 else523 pll_id = DPLL_ID_PCH_PLL_A;524 }525 526 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);527 pll = crtc_state->shared_dpll;528 529 pll_active = intel_dpll_get_hw_state(dev_priv, pll,530 &crtc_state->dpll_hw_state);531 drm_WARN_ON(&dev_priv->drm, !pll_active);532 533 tmp = crtc_state->dpll_hw_state.i9xx.dpll;534 crtc_state->pixel_multiplier =535 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)536 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;537 538 ilk_pch_clock_get(crtc_state);539}540 541static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)542{543 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);545 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;546 u32 val, pipeconf_val;547 548 /* FDI must be feeding us bits for PCH ports */549 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);550 assert_fdi_rx_enabled(dev_priv, PIPE_A);551 552 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));553 /* Workaround: set timing override bit. */554 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;555 /* Configure frame start delay to match the CPU */556 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;557 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);558 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);559 560 val = TRANS_ENABLE;561 pipeconf_val = intel_de_read(dev_priv,562 TRANSCONF(dev_priv, cpu_transcoder));563 564 if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)565 val |= TRANS_INTERLACE_INTERLACED;566 else567 val |= TRANS_INTERLACE_PROGRESSIVE;568 569 intel_de_write(dev_priv, LPT_TRANSCONF, val);570 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,571 TRANS_STATE_ENABLE, 100))572 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");573}574 575static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)576{577 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0);578 /* wait for PCH transcoder off, transcoder state */579 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,580 TRANS_STATE_ENABLE, 50))581 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");582 583 /* Workaround: clear timing override bit. */584 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);585}586 587void lpt_pch_enable(struct intel_atomic_state *state,588 struct intel_crtc *crtc)589{590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);591 const struct intel_crtc_state *crtc_state =592 intel_atomic_get_new_crtc_state(state, crtc);593 594 assert_pch_transcoder_disabled(dev_priv, PIPE_A);595 596 lpt_program_iclkip(crtc_state);597 598 /* Set transcoder timing. */599 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);600 601 lpt_enable_pch_transcoder(crtc_state);602}603 604void lpt_pch_disable(struct intel_atomic_state *state,605 struct intel_crtc *crtc)606{607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);608 609 lpt_disable_pch_transcoder(dev_priv);610 611 lpt_disable_iclkip(dev_priv);612}613 614void lpt_pch_get_config(struct intel_crtc_state *crtc_state)615{616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);618 u32 tmp;619 620 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)621 return;622 623 crtc_state->has_pch_encoder = true;624 625 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));626 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>627 FDI_DP_PORT_WIDTH_SHIFT) + 1;628 629 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,630 &crtc_state->fdi_m_n);631 632 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);633}634 635void intel_pch_sanitize(struct drm_i915_private *i915)636{637 if (HAS_PCH_IBX(i915))638 ibx_sanitize_pch_ports(i915);639}640