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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef __INTEL_PSR_REGS_H__7#define __INTEL_PSR_REGS_H__8 9#include "intel_display_reg_defs.h"10#include "intel_dp_aux_regs.h"11 12#define TRANS_EXITLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)13#define EXITLINE_ENABLE REG_BIT(31)14#define EXITLINE_MASK REG_GENMASK(12, 0)15#define EXITLINE_SHIFT 016 17/*18 * HSW+ eDP PSR registers19 *20 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one21 * instance of it22 */23#define HSW_SRD_CTL _MMIO(0x64800)24#define _SRD_CTL_A 0x6080025#define _SRD_CTL_EDP 0x6f80026#define EDP_PSR_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)27#define EDP_PSR_ENABLE REG_BIT(31)28#define BDW_PSR_SINGLE_FRAME REG_BIT(30)29#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */30#define EDP_PSR_LINK_STANDBY REG_BIT(27)31#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25)32#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0)33#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1)34#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2)35#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3)36#define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20)37#define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x))38#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16)39#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x))40#define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)41#define EDP_PSR_TP_MASK REG_BIT(11)42#define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0)43#define EDP_PSR_TP_TP1_TP3 REG_FIELD_PREP(EDP_PSR_TP_MASK, 1)44#define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */45#define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8)46#define EDP_PSR_TP2_TP3_TIME_500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0)47#define EDP_PSR_TP2_TP3_TIME_100us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1)48#define EDP_PSR_TP2_TP3_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2)49#define EDP_PSR_TP2_TP3_TIME_0us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3)50#define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6)51#define EDP_PSR_TP4_TIME_0us REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */52#define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4)53#define EDP_PSR_TP1_TIME_500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0)54#define EDP_PSR_TP1_TIME_100us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1)55#define EDP_PSR_TP1_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2)56#define EDP_PSR_TP1_TIME_0us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3)57#define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0)58#define EDP_PSR_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x))59 60/*61 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative62 * to transcoder and bits defined for each one as if using no shift (i.e. as if63 * it was for TRANSCODER_EDP)64 */65#define EDP_PSR_IMR _MMIO(0x64834)66#define EDP_PSR_IIR _MMIO(0x64838)67#define _PSR_IMR_A 0x6081468#define _PSR_IIR_A 0x6081869#define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)70#define TRANS_PSR_IIR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)71#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \72 0 : ((trans) - TRANSCODER_A + 1) * 8)73#define TGL_PSR_MASK REG_GENMASK(2, 0)74#define TGL_PSR_ERROR REG_BIT(2)75#define TGL_PSR_POST_EXIT REG_BIT(1)76#define TGL_PSR_PRE_ENTRY REG_BIT(0)77#define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \78 _EDP_PSR_TRANS_SHIFT(trans))79#define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \80 _EDP_PSR_TRANS_SHIFT(trans))81#define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \82 _EDP_PSR_TRANS_SHIFT(trans))83#define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \84 _EDP_PSR_TRANS_SHIFT(trans))85 86#define HSW_SRD_AUX_CTL _MMIO(0x64810)87#define _SRD_AUX_CTL_A 0x6081088#define _SRD_AUX_CTL_EDP 0x6f81089#define EDP_PSR_AUX_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)90#define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK91#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK92#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK93#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11)94#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK95 96#define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */97#define _SRD_AUX_DATA_A 0x6081498#define _SRD_AUX_DATA_EDP 0x6f81499#define EDP_PSR_AUX_DATA(dev_priv, tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */100 101#define HSW_SRD_STATUS _MMIO(0x64840)102#define _SRD_STATUS_A 0x60840103#define _SRD_STATUS_EDP 0x6f840104#define EDP_PSR_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)105#define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)106#define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)107#define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)108#define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2)109#define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3)110#define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4)111#define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5)112#define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6)113#define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26)114#define EDP_PSR_STATUS_LINK_FULL_OFF REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0)115#define EDP_PSR_STATUS_LINK_FULL_ON REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1)116#define EDP_PSR_STATUS_LINK_STANDBY REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2)117#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20)118#define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16)119#define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15)120#define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12)121#define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9)122#define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8)123#define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4)124#define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0)125 126#define HSW_SRD_PERF_CNT _MMIO(0x64844)127#define _SRD_PERF_CNT_A 0x60844128#define _SRD_PERF_CNT_EDP 0x6f844129#define EDP_PSR_PERF_CNT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)130#define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0)131 132/* PSR_MASK on SKL+ */133#define HSW_SRD_DEBUG _MMIO(0x64860)134#define _SRD_DEBUG_A 0x60860135#define _SRD_DEBUG_EDP 0x6f860136#define EDP_PSR_DEBUG(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)137#define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28)138#define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27)139#define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26)140#define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25)141#define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24)142#define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */143#define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */144#define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */145#define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */146#define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */147#define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */148#define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17)149#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */150#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */151#define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */152#define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */153 154#define _PSR2_CTL_A 0x60900155#define _PSR2_CTL_EDP 0x6f900156#define EDP_PSR2_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)157#define EDP_PSR2_ENABLE REG_BIT(31)158#define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */159#define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28)160#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0)161#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1)162#define LNL_EDP_PSR2_SU_REGION_ET_ENABLE REG_BIT(27)163#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */164#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */165#define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20)166#define EDP_MAX_SU_DISABLE_TIME(t) REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t))167#define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13)168#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8169#define EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \170 EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines))171#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13)172#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5173#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \174 (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)175#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13)176#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5177#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \178 (lines) - LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)179#define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11)180#define EDP_PSR2_FAST_WAKE_MAX_LINES 8181#define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \182 EDP_PSR2_FAST_WAKE_MAX_LINES - (lines))183#define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10)184#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5185#define TGL_EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \186 (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES)187#define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8)188#define EDP_PSR2_TP2_TIME_500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0)189#define EDP_PSR2_TP2_TIME_100us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1)190#define EDP_PSR2_TP2_TIME_2500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2)191#define EDP_PSR2_TP2_TIME_50us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3)192#define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4)193#define EDP_PSR2_FRAME_BEFORE_SU(a) REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a))194#define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0)195#define EDP_PSR2_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x))196 197#define _PSR_EVENT_TRANS_A 0x60848198#define _PSR_EVENT_TRANS_B 0x61848199#define _PSR_EVENT_TRANS_C 0x62848200#define _PSR_EVENT_TRANS_D 0x63848201#define _PSR_EVENT_TRANS_EDP 0x6f848202#define PSR_EVENT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)203#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17)204#define PSR_EVENT_PSR2_DISABLED REG_BIT(16)205#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15)206#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14)207#define PSR_EVENT_GRAPHICS_RESET REG_BIT(12)208#define PSR_EVENT_PCH_INTERRUPT REG_BIT(11)209#define PSR_EVENT_MEMORY_UP REG_BIT(10)210#define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9)211#define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8)212#define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6)213#define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */214#define PSR_EVENT_HDCP_ENABLE REG_BIT(4)215#define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3)216#define PSR_EVENT_VBI_ENABLE REG_BIT(2)217#define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1)218#define PSR_EVENT_PSR_DISABLE REG_BIT(0)219 220#define _PSR2_STATUS_A 0x60940221#define _PSR2_STATUS_EDP 0x6f940222#define EDP_PSR2_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)223#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)224#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)225 226#define _PSR2_SU_STATUS_A 0x60914227#define _PSR2_SU_STATUS_EDP 0x6f914228#define _PSR2_SU_STATUS(dev_priv, tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)229#define PSR2_SU_STATUS(dev_priv, tran, frame) (_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))230#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)231#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))232#define PSR2_SU_STATUS_FRAMES 8233 234#define _PSR2_MAN_TRK_CTL_A 0x60910235#define _PSR2_MAN_TRK_CTL_EDP 0x6f910236#define PSR2_MAN_TRK_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)237#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)238#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)239#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)240#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)241#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)242#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)243#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)244#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)245#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)246#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)247#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)248#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)249#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)250#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)251#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)252 253/* PSR2 Early transport */254#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074255#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074256#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)257 258#define _ALPM_CTL_A 0x60950259#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)260#define ALPM_CTL_ALPM_ENABLE REG_BIT(31)261#define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30)262#define ALPM_CTL_LOBF_ENABLE REG_BIT(29)263#define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28)264#define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27)265#define ALPM_CTL_RESTORE_OCCURED REG_BIT(26)266#define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25)267#define ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24)268#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, 21)269#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0)270#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1)271#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2)272#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3)273#define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20)274#define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, 16)275#define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val)276#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, 8)277#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5278#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)279#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0)280#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)281 282#define _ALPM_CTL2_A 0x60954283#define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)284#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24)285#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)286#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16)287#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val)288#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK REG_GENMASK(15, 12)289#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val)290#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(10, 8)291#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val)292#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR REG_BIT(4)293#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK REG_GENMASK(2, 0)294#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)295 296#define _PORT_ALPM_CTL_A 0x16fa2c297#define _PORT_ALPM_CTL_B 0x16fc2c298#define PORT_ALPM_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B)299#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)300#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20)301#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)302#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16)303#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)304#define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0)305#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)306 307#define _PORT_ALPM_LFPS_CTL_A 0x16fa30308#define _PORT_ALPM_LFPS_CTL_B 0x16fc30309#define PORT_ALPM_LFPS_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)310#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31)311#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24)312#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7313#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)314#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, 16)315#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)316#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(12, 8)317#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)318#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(4, 0)319#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)320 321#endif /* __INTEL_PSR_REGS_H__ */322