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1/*2 * Copyright © 2006-2007 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER21 * DEALINGS IN THE SOFTWARE.22 *23 * Authors:24 * Eric Anholt <eric@anholt.net>25 */26 27#ifndef __INTEL_SDVO_REGS_H__28#define __INTEL_SDVO_REGS_H__29 30#include <linux/compiler.h>31#include <linux/types.h>32 33/*34 * SDVO command definitions and structures.35 */36 37#define SDVO_OUTPUT_FIRST (0)38#define SDVO_OUTPUT_TMDS0 (1 << 0)39#define SDVO_OUTPUT_RGB0 (1 << 1)40#define SDVO_OUTPUT_CVBS0 (1 << 2)41#define SDVO_OUTPUT_SVID0 (1 << 3)42#define SDVO_OUTPUT_YPRPB0 (1 << 4)43#define SDVO_OUTPUT_SCART0 (1 << 5)44#define SDVO_OUTPUT_LVDS0 (1 << 6)45#define SDVO_OUTPUT_TMDS1 (1 << 8)46#define SDVO_OUTPUT_RGB1 (1 << 9)47#define SDVO_OUTPUT_CVBS1 (1 << 10)48#define SDVO_OUTPUT_SVID1 (1 << 11)49#define SDVO_OUTPUT_YPRPB1 (1 << 12)50#define SDVO_OUTPUT_SCART1 (1 << 13)51#define SDVO_OUTPUT_LVDS1 (1 << 14)52#define SDVO_OUTPUT_LAST (14)53 54struct intel_sdvo_caps {55 u8 vendor_id;56 u8 device_id;57 u8 device_rev_id;58 u8 sdvo_version_major;59 u8 sdvo_version_minor;60 unsigned int sdvo_num_inputs:2;61 unsigned int smooth_scaling:1;62 unsigned int sharp_scaling:1;63 unsigned int up_scaling:1;64 unsigned int down_scaling:1;65 unsigned int stall_support:1;66 unsigned int pad:1;67 u16 output_flags;68} __packed;69 70/* Note: SDVO detailed timing flags match EDID misc flags. */71#define DTD_FLAG_HSYNC_POSITIVE (1 << 1)72#define DTD_FLAG_VSYNC_POSITIVE (1 << 2)73#define DTD_FLAG_INTERLACE (1 << 7)74 75/* This matches the EDID DTD structure, more or less */76struct intel_sdvo_dtd {77 struct {78 u16 clock; /* pixel clock, in 10kHz units */79 u8 h_active; /* lower 8 bits (pixels) */80 u8 h_blank; /* lower 8 bits (pixels) */81 u8 h_high; /* upper 4 bits each h_active, h_blank */82 u8 v_active; /* lower 8 bits (lines) */83 u8 v_blank; /* lower 8 bits (lines) */84 u8 v_high; /* upper 4 bits each v_active, v_blank */85 } part1;86 87 struct {88 u8 h_sync_off; /* lower 8 bits, from hblank start */89 u8 h_sync_width; /* lower 8 bits (pixels) */90 /* lower 4 bits each vsync offset, vsync width */91 u8 v_sync_off_width;92 /*93 * 2 high bits of hsync offset, 2 high bits of hsync width,94 * bits 4-5 of vsync offset, and 2 high bits of vsync width.95 */96 u8 sync_off_width_high;97 u8 dtd_flags;98 u8 sdvo_flags;99 /* bits 6-7 of vsync offset at bits 6-7 */100 u8 v_sync_off_high;101 u8 reserved;102 } part2;103} __packed;104 105struct intel_sdvo_pixel_clock_range {106 u16 min; /* pixel clock, in 10kHz units */107 u16 max; /* pixel clock, in 10kHz units */108} __packed;109 110struct intel_sdvo_preferred_input_timing_args {111 u16 clock;112 u16 width;113 u16 height;114 u8 interlace:1;115 u8 scaled:1;116 u8 pad:6;117} __packed;118 119/* I2C registers for SDVO */120#define SDVO_I2C_ARG_0 0x07121#define SDVO_I2C_ARG_1 0x06122#define SDVO_I2C_ARG_2 0x05123#define SDVO_I2C_ARG_3 0x04124#define SDVO_I2C_ARG_4 0x03125#define SDVO_I2C_ARG_5 0x02126#define SDVO_I2C_ARG_6 0x01127#define SDVO_I2C_ARG_7 0x00128#define SDVO_I2C_OPCODE 0x08129#define SDVO_I2C_CMD_STATUS 0x09130#define SDVO_I2C_RETURN_0 0x0a131#define SDVO_I2C_RETURN_1 0x0b132#define SDVO_I2C_RETURN_2 0x0c133#define SDVO_I2C_RETURN_3 0x0d134#define SDVO_I2C_RETURN_4 0x0e135#define SDVO_I2C_RETURN_5 0x0f136#define SDVO_I2C_RETURN_6 0x10137#define SDVO_I2C_RETURN_7 0x11138#define SDVO_I2C_VENDOR_BEGIN 0x20139 140/* Status results */141#define SDVO_CMD_STATUS_POWER_ON 0x0142#define SDVO_CMD_STATUS_SUCCESS 0x1143#define SDVO_CMD_STATUS_NOTSUPP 0x2144#define SDVO_CMD_STATUS_INVALID_ARG 0x3145#define SDVO_CMD_STATUS_PENDING 0x4146#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5147#define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6148 149/* SDVO commands, argument/result registers */150 151#define SDVO_CMD_RESET 0x01152 153/* Returns a struct intel_sdvo_caps */154#define SDVO_CMD_GET_DEVICE_CAPS 0x02155 156#define SDVO_CMD_GET_FIRMWARE_REV 0x86157# define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0158# define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1159# define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2160 161/*162 * Reports which inputs are trained (managed to sync).163 *164 * Devices must have trained within 2 vsyncs of a mode change.165 */166#define SDVO_CMD_GET_TRAINED_INPUTS 0x03167struct intel_sdvo_get_trained_inputs_response {168 unsigned int input0_trained:1;169 unsigned int input1_trained:1;170 unsigned int pad:6;171} __packed;172 173/* Returns a struct intel_sdvo_output_flags of active outputs. */174#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04175 176/*177 * Sets the current set of active outputs.178 *179 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP180 * on multi-output devices.181 */182#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05183 184/*185 * Returns the current mapping of SDVO inputs to outputs on the device.186 *187 * Returns two struct intel_sdvo_output_flags structures.188 */189#define SDVO_CMD_GET_IN_OUT_MAP 0x06190struct intel_sdvo_in_out_map {191 u16 in0, in1;192};193 194/*195 * Sets the current mapping of SDVO inputs to outputs on the device.196 *197 * Takes two struct i380_sdvo_output_flags structures.198 */199#define SDVO_CMD_SET_IN_OUT_MAP 0x07200 201/*202 * Returns a struct intel_sdvo_output_flags of attached displays.203 */204#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b205 206/*207 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.208 */209#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c210 211/*212 * Takes a struct intel_sdvo_output_flags.213 */214#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d215 216/*217 * Returns a struct intel_sdvo_output_flags of displays with hot plug218 * interrupts enabled.219 */220#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e221 222#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f223struct intel_sdvo_get_interrupt_event_source_response {224 u16 interrupt_status;225 unsigned int ambient_light_interrupt:1;226 unsigned int hdmi_audio_encrypt_change:1;227 unsigned int pad:6;228} __packed;229 230/*231 * Selects which input is affected by future input commands.232 *233 * Commands affected include SET_INPUT_TIMINGS_PART[12],234 * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],235 * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.236 */237#define SDVO_CMD_SET_TARGET_INPUT 0x10238struct intel_sdvo_set_target_input_args {239 unsigned int target_1:1;240 unsigned int pad:7;241} __packed;242 243/*244 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by245 * future output commands.246 *247 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],248 * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.249 */250#define SDVO_CMD_SET_TARGET_OUTPUT 0x11251 252#define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12253#define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13254#define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14255#define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15256#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16257#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17258#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18259#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19260/* Part 1 */261# define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0262# define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1263# define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2264# define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3265# define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4266# define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5267# define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6268# define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7269/* Part 2 */270# define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0271# define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1272# define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2273# define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3274# define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4275# define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)276# define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)277# define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)278# define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)279# define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5280# define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)281# define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)282# define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)283# define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)284# define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)285# define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)286# define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)287# define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6288 289/*290 * Generates a DTD based on the given width, height, and flags.291 *292 * This will be supported by any device supporting scaling or interlaced293 * modes.294 */295#define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a296# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0297# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1298# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2299# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3300# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4301# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5302# define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6303# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)304# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)305 306#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b307#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c308 309/* Returns a struct intel_sdvo_pixel_clock_range */310#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d311/* Returns a struct intel_sdvo_pixel_clock_range */312#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e313 314/* Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */315#define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f316 317/* Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */318#define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20319/* Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */320#define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21321# define SDVO_CLOCK_RATE_MULT_1X (1 << 0)322# define SDVO_CLOCK_RATE_MULT_2X (1 << 1)323# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)324 325#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27326/* 6 bytes of bit flags for TV formats shared by all TV format functions */327struct intel_sdvo_tv_format {328 unsigned int ntsc_m:1;329 unsigned int ntsc_j:1;330 unsigned int ntsc_443:1;331 unsigned int pal_b:1;332 unsigned int pal_d:1;333 unsigned int pal_g:1;334 unsigned int pal_h:1;335 unsigned int pal_i:1;336 337 unsigned int pal_m:1;338 unsigned int pal_n:1;339 unsigned int pal_nc:1;340 unsigned int pal_60:1;341 unsigned int secam_b:1;342 unsigned int secam_d:1;343 unsigned int secam_g:1;344 unsigned int secam_k:1;345 346 unsigned int secam_k1:1;347 unsigned int secam_l:1;348 unsigned int secam_60:1;349 unsigned int hdtv_std_smpte_240m_1080i_59:1;350 unsigned int hdtv_std_smpte_240m_1080i_60:1;351 unsigned int hdtv_std_smpte_260m_1080i_59:1;352 unsigned int hdtv_std_smpte_260m_1080i_60:1;353 unsigned int hdtv_std_smpte_274m_1080i_50:1;354 355 unsigned int hdtv_std_smpte_274m_1080i_59:1;356 unsigned int hdtv_std_smpte_274m_1080i_60:1;357 unsigned int hdtv_std_smpte_274m_1080p_23:1;358 unsigned int hdtv_std_smpte_274m_1080p_24:1;359 unsigned int hdtv_std_smpte_274m_1080p_25:1;360 unsigned int hdtv_std_smpte_274m_1080p_29:1;361 unsigned int hdtv_std_smpte_274m_1080p_30:1;362 unsigned int hdtv_std_smpte_274m_1080p_50:1;363 364 unsigned int hdtv_std_smpte_274m_1080p_59:1;365 unsigned int hdtv_std_smpte_274m_1080p_60:1;366 unsigned int hdtv_std_smpte_295m_1080i_50:1;367 unsigned int hdtv_std_smpte_295m_1080p_50:1;368 unsigned int hdtv_std_smpte_296m_720p_59:1;369 unsigned int hdtv_std_smpte_296m_720p_60:1;370 unsigned int hdtv_std_smpte_296m_720p_50:1;371 unsigned int hdtv_std_smpte_293m_480p_59:1;372 373 unsigned int hdtv_std_smpte_170m_480i_59:1;374 unsigned int hdtv_std_iturbt601_576i_50:1;375 unsigned int hdtv_std_iturbt601_576p_50:1;376 unsigned int hdtv_std_eia_7702a_480i_60:1;377 unsigned int hdtv_std_eia_7702a_480p_60:1;378 unsigned int pad:3;379} __packed;380 381#define SDVO_CMD_GET_TV_FORMAT 0x28382 383#define SDVO_CMD_SET_TV_FORMAT 0x29384 385/* Returns the resolutiosn that can be used with the given TV format */386#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83387struct intel_sdvo_sdtv_resolution_request {388 unsigned int ntsc_m:1;389 unsigned int ntsc_j:1;390 unsigned int ntsc_443:1;391 unsigned int pal_b:1;392 unsigned int pal_d:1;393 unsigned int pal_g:1;394 unsigned int pal_h:1;395 unsigned int pal_i:1;396 397 unsigned int pal_m:1;398 unsigned int pal_n:1;399 unsigned int pal_nc:1;400 unsigned int pal_60:1;401 unsigned int secam_b:1;402 unsigned int secam_d:1;403 unsigned int secam_g:1;404 unsigned int secam_k:1;405 406 unsigned int secam_k1:1;407 unsigned int secam_l:1;408 unsigned int secam_60:1;409 unsigned int pad:5;410} __packed;411 412struct intel_sdvo_sdtv_resolution_reply {413 unsigned int res_320x200:1;414 unsigned int res_320x240:1;415 unsigned int res_400x300:1;416 unsigned int res_640x350:1;417 unsigned int res_640x400:1;418 unsigned int res_640x480:1;419 unsigned int res_704x480:1;420 unsigned int res_704x576:1;421 422 unsigned int res_720x350:1;423 unsigned int res_720x400:1;424 unsigned int res_720x480:1;425 unsigned int res_720x540:1;426 unsigned int res_720x576:1;427 unsigned int res_768x576:1;428 unsigned int res_800x600:1;429 unsigned int res_832x624:1;430 431 unsigned int res_920x766:1;432 unsigned int res_1024x768:1;433 unsigned int res_1280x1024:1;434 unsigned int pad:5;435} __packed;436 437/* Get supported resolution with squire pixel aspect ratio that can be438 scaled for the requested HDTV format */439#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85440 441struct intel_sdvo_hdtv_resolution_request {442 unsigned int hdtv_std_smpte_240m_1080i_59:1;443 unsigned int hdtv_std_smpte_240m_1080i_60:1;444 unsigned int hdtv_std_smpte_260m_1080i_59:1;445 unsigned int hdtv_std_smpte_260m_1080i_60:1;446 unsigned int hdtv_std_smpte_274m_1080i_50:1;447 unsigned int hdtv_std_smpte_274m_1080i_59:1;448 unsigned int hdtv_std_smpte_274m_1080i_60:1;449 unsigned int hdtv_std_smpte_274m_1080p_23:1;450 451 unsigned int hdtv_std_smpte_274m_1080p_24:1;452 unsigned int hdtv_std_smpte_274m_1080p_25:1;453 unsigned int hdtv_std_smpte_274m_1080p_29:1;454 unsigned int hdtv_std_smpte_274m_1080p_30:1;455 unsigned int hdtv_std_smpte_274m_1080p_50:1;456 unsigned int hdtv_std_smpte_274m_1080p_59:1;457 unsigned int hdtv_std_smpte_274m_1080p_60:1;458 unsigned int hdtv_std_smpte_295m_1080i_50:1;459 460 unsigned int hdtv_std_smpte_295m_1080p_50:1;461 unsigned int hdtv_std_smpte_296m_720p_59:1;462 unsigned int hdtv_std_smpte_296m_720p_60:1;463 unsigned int hdtv_std_smpte_296m_720p_50:1;464 unsigned int hdtv_std_smpte_293m_480p_59:1;465 unsigned int hdtv_std_smpte_170m_480i_59:1;466 unsigned int hdtv_std_iturbt601_576i_50:1;467 unsigned int hdtv_std_iturbt601_576p_50:1;468 469 unsigned int hdtv_std_eia_7702a_480i_60:1;470 unsigned int hdtv_std_eia_7702a_480p_60:1;471 unsigned int pad:6;472} __packed;473 474struct intel_sdvo_hdtv_resolution_reply {475 unsigned int res_640x480:1;476 unsigned int res_800x600:1;477 unsigned int res_1024x768:1;478 unsigned int res_1280x960:1;479 unsigned int res_1400x1050:1;480 unsigned int res_1600x1200:1;481 unsigned int res_1920x1440:1;482 unsigned int res_2048x1536:1;483 484 unsigned int res_2560x1920:1;485 unsigned int res_3200x2400:1;486 unsigned int res_3840x2880:1;487 unsigned int pad1:5;488 489 unsigned int res_848x480:1;490 unsigned int res_1064x600:1;491 unsigned int res_1280x720:1;492 unsigned int res_1360x768:1;493 unsigned int res_1704x960:1;494 unsigned int res_1864x1050:1;495 unsigned int res_1920x1080:1;496 unsigned int res_2128x1200:1;497 498 unsigned int res_2560x1400:1;499 unsigned int res_2728x1536:1;500 unsigned int res_3408x1920:1;501 unsigned int res_4264x2400:1;502 unsigned int res_5120x2880:1;503 unsigned int pad2:3;504 505 unsigned int res_768x480:1;506 unsigned int res_960x600:1;507 unsigned int res_1152x720:1;508 unsigned int res_1124x768:1;509 unsigned int res_1536x960:1;510 unsigned int res_1680x1050:1;511 unsigned int res_1728x1080:1;512 unsigned int res_1920x1200:1;513 514 unsigned int res_2304x1440:1;515 unsigned int res_2456x1536:1;516 unsigned int res_3072x1920:1;517 unsigned int res_3840x2400:1;518 unsigned int res_4608x2880:1;519 unsigned int pad3:3;520 521 unsigned int res_1280x1024:1;522 unsigned int pad4:7;523 524 unsigned int res_1280x768:1;525 unsigned int pad5:7;526} __packed;527 528/* Get supported power state returns info for encoder and monitor, rely on529 last SetTargetInput and SetTargetOutput calls */530#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a531/* Get power state returns info for encoder and monitor, rely on last532 SetTargetInput and SetTargetOutput calls */533#define SDVO_CMD_GET_POWER_STATE 0x2b534#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b535#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c536# define SDVO_ENCODER_STATE_ON (1 << 0)537# define SDVO_ENCODER_STATE_STANDBY (1 << 1)538# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)539# define SDVO_ENCODER_STATE_OFF (1 << 3)540# define SDVO_MONITOR_STATE_ON (1 << 4)541# define SDVO_MONITOR_STATE_STANDBY (1 << 5)542# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)543# define SDVO_MONITOR_STATE_OFF (1 << 7)544 545#define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d546#define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e547#define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f548/*549 * The panel power sequencing parameters are in units of milliseconds.550 * The high fields are bits 8:9 of the 10-bit values.551 */552struct sdvo_panel_power_sequencing {553 u8 t0;554 u8 t1;555 u8 t2;556 u8 t3;557 u8 t4;558 559 unsigned int t0_high:2;560 unsigned int t1_high:2;561 unsigned int t2_high:2;562 unsigned int t3_high:2;563 564 unsigned int t4_high:2;565 unsigned int pad:6;566} __packed;567 568#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30569struct sdvo_max_backlight_reply {570 u8 max_value;571 u8 default_value;572} __packed;573 574#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31575#define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32576 577#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33578struct sdvo_get_ambient_light_reply {579 u16 trip_low;580 u16 trip_high;581 u16 value;582} __packed;583#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34584struct sdvo_set_ambient_light_reply {585 u16 trip_low;586 u16 trip_high;587 unsigned int enable:1;588 unsigned int pad:7;589} __packed;590 591/* Set display power state */592#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d593# define SDVO_DISPLAY_STATE_ON (1 << 0)594# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)595# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)596# define SDVO_DISPLAY_STATE_OFF (1 << 3)597 598#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84599struct intel_sdvo_enhancements_reply {600 unsigned int flicker_filter:1;601 unsigned int flicker_filter_adaptive:1;602 unsigned int flicker_filter_2d:1;603 unsigned int saturation:1;604 unsigned int hue:1;605 unsigned int brightness:1;606 unsigned int contrast:1;607 unsigned int overscan_h:1;608 609 unsigned int overscan_v:1;610 unsigned int hpos:1;611 unsigned int vpos:1;612 unsigned int sharpness:1;613 unsigned int dot_crawl:1;614 unsigned int dither:1;615 unsigned int tv_chroma_filter:1;616 unsigned int tv_luma_filter:1;617} __packed;618 619/* Picture enhancement limits below are dependent on the current TV format,620 * and thus need to be queried and set after it.621 */622#define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d623#define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b624#define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52625#define SDVO_CMD_GET_MAX_SATURATION 0x55626#define SDVO_CMD_GET_MAX_HUE 0x58627#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b628#define SDVO_CMD_GET_MAX_CONTRAST 0x5e629#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61630#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64631#define SDVO_CMD_GET_MAX_HPOS 0x67632#define SDVO_CMD_GET_MAX_VPOS 0x6a633#define SDVO_CMD_GET_MAX_SHARPNESS 0x6d634#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74635#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77636struct intel_sdvo_enhancement_limits_reply {637 u16 max_value;638 u16 default_value;639} __packed;640 641#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f642#define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80643# define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)644# define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)645# define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)646# define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)647# define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)648# define SDVO_LVDS_DUAL_CHANNEL (1 << 4)649 650#define SDVO_CMD_GET_FLICKER_FILTER 0x4e651#define SDVO_CMD_SET_FLICKER_FILTER 0x4f652#define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50653#define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51654#define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53655#define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54656#define SDVO_CMD_GET_SATURATION 0x56657#define SDVO_CMD_SET_SATURATION 0x57658#define SDVO_CMD_GET_HUE 0x59659#define SDVO_CMD_SET_HUE 0x5a660#define SDVO_CMD_GET_BRIGHTNESS 0x5c661#define SDVO_CMD_SET_BRIGHTNESS 0x5d662#define SDVO_CMD_GET_CONTRAST 0x5f663#define SDVO_CMD_SET_CONTRAST 0x60664#define SDVO_CMD_GET_OVERSCAN_H 0x62665#define SDVO_CMD_SET_OVERSCAN_H 0x63666#define SDVO_CMD_GET_OVERSCAN_V 0x65667#define SDVO_CMD_SET_OVERSCAN_V 0x66668#define SDVO_CMD_GET_HPOS 0x68669#define SDVO_CMD_SET_HPOS 0x69670#define SDVO_CMD_GET_VPOS 0x6b671#define SDVO_CMD_SET_VPOS 0x6c672#define SDVO_CMD_GET_SHARPNESS 0x6e673#define SDVO_CMD_SET_SHARPNESS 0x6f674#define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75675#define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76676#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78677#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79678struct intel_sdvo_enhancements_arg {679 u16 value;680} __packed;681 682#define SDVO_CMD_GET_DOT_CRAWL 0x70683#define SDVO_CMD_SET_DOT_CRAWL 0x71684# define SDVO_DOT_CRAWL_ON (1 << 0)685# define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)686 687#define SDVO_CMD_GET_DITHER 0x72688#define SDVO_CMD_SET_DITHER 0x73689# define SDVO_DITHER_ON (1 << 0)690# define SDVO_DITHER_DEFAULT_ON (1 << 1)691 692#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a693# define SDVO_CONTROL_BUS_PROM (1 << 0)694# define SDVO_CONTROL_BUS_DDC1 (1 << 1)695# define SDVO_CONTROL_BUS_DDC2 (1 << 2)696# define SDVO_CONTROL_BUS_DDC3 (1 << 3)697 698/* HDMI op codes */699#define SDVO_CMD_GET_SUPP_ENCODE 0x9d700#define SDVO_CMD_GET_ENCODE 0x9e701#define SDVO_CMD_SET_ENCODE 0x9f702 #define SDVO_ENCODE_DVI 0x0703 #define SDVO_ENCODE_HDMI 0x1704#define SDVO_CMD_SET_PIXEL_REPLI 0x8b705#define SDVO_CMD_GET_PIXEL_REPLI 0x8c706#define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d707#define SDVO_CMD_SET_COLORIMETRY 0x8e708 #define SDVO_COLORIMETRY_RGB256 (1 << 0)709 #define SDVO_COLORIMETRY_RGB220 (1 << 1)710 #define SDVO_COLORIMETRY_YCrCb422 (1 << 2)711 #define SDVO_COLORIMETRY_YCrCb444 (1 << 3)712#define SDVO_CMD_GET_COLORIMETRY 0x8f713#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90714#define SDVO_CMD_SET_AUDIO_STAT 0x91715#define SDVO_CMD_GET_AUDIO_STAT 0x92716 #define SDVO_AUDIO_ELD_VALID (1 << 0)717 #define SDVO_AUDIO_PRESENCE_DETECT (1 << 1)718 #define SDVO_AUDIO_CP_READY (1 << 2)719#define SDVO_CMD_SET_HBUF_INDEX 0x93720 #define SDVO_HBUF_INDEX_ELD 0721 #define SDVO_HBUF_INDEX_AVI_IF 1722#define SDVO_CMD_GET_HBUF_INDEX 0x94723#define SDVO_CMD_GET_HBUF_INFO 0x95724#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96725#define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97726#define SDVO_CMD_SET_HBUF_DATA 0x98727#define SDVO_CMD_GET_HBUF_DATA 0x99728#define SDVO_CMD_SET_HBUF_TXRATE 0x9a729#define SDVO_CMD_GET_HBUF_TXRATE 0x9b730 #define SDVO_HBUF_TX_DISABLED (0 << 6)731 #define SDVO_HBUF_TX_ONCE (2 << 6)732 #define SDVO_HBUF_TX_VSYNC (3 << 6)733#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c734#define SDVO_NEED_TO_STALL (1 << 7)735 736struct intel_sdvo_encode {737 u8 dvi_rev;738 u8 hdmi_rev;739} __packed;740 741#endif /* __INTEL_SDVO_REGS_H__ */742