128 lines · c
1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2024 Intel Corporation4 */5 6#ifndef __INTEL_VRR_REGS_H__7#define __INTEL_VRR_REGS_H__8 9#include "intel_display_reg_defs.h"10 11/* VRR registers */12#define _TRANS_VRR_CTL_A 0x6042013#define _TRANS_VRR_CTL_B 0x6142014#define _TRANS_VRR_CTL_C 0x6242015#define _TRANS_VRR_CTL_D 0x6342016#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)17#define VRR_CTL_VRR_ENABLE REG_BIT(31)18#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)19#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)20#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)21#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))22#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)23#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)24#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))25 26#define _TRANS_VRR_VMAX_A 0x6042427#define _TRANS_VRR_VMAX_B 0x6142428#define _TRANS_VRR_VMAX_C 0x6242429#define _TRANS_VRR_VMAX_D 0x6342430#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)31#define VRR_VMAX_MASK REG_GENMASK(19, 0)32 33#define _TRANS_VRR_VMIN_A 0x6043434#define _TRANS_VRR_VMIN_B 0x6143435#define _TRANS_VRR_VMIN_C 0x6243436#define _TRANS_VRR_VMIN_D 0x6343437#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)38#define VRR_VMIN_MASK REG_GENMASK(15, 0)39 40#define _TRANS_VRR_VMAXSHIFT_A 0x6042841#define _TRANS_VRR_VMAXSHIFT_B 0x6142842#define _TRANS_VRR_VMAXSHIFT_C 0x6242843#define _TRANS_VRR_VMAXSHIFT_D 0x6342844#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \45 _TRANS_VRR_VMAXSHIFT_A)46#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)47#define VRR_VMAXSHIFT_DEC REG_BIT(16)48#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)49 50#define _TRANS_VRR_STATUS_A 0x6042c51#define _TRANS_VRR_STATUS_B 0x6142c52#define _TRANS_VRR_STATUS_C 0x6242c53#define _TRANS_VRR_STATUS_D 0x6342c54#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)55#define VRR_STATUS_VMAX_REACHED REG_BIT(31)56#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)57#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)58#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)59#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)60#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)61#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)62#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)63#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)64#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)65#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)66#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)67#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)68#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)69 70#define _TRANS_VRR_VTOTAL_PREV_A 0x6048071#define _TRANS_VRR_VTOTAL_PREV_B 0x6148072#define _TRANS_VRR_VTOTAL_PREV_C 0x6248073#define _TRANS_VRR_VTOTAL_PREV_D 0x6348074#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \75 _TRANS_VRR_VTOTAL_PREV_A)76#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)77#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)78#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)79#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)80 81#define _TRANS_VRR_FLIPLINE_A 0x6043882#define _TRANS_VRR_FLIPLINE_B 0x6143883#define _TRANS_VRR_FLIPLINE_C 0x6243884#define _TRANS_VRR_FLIPLINE_D 0x6343885#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \86 _TRANS_VRR_FLIPLINE_A)87#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)88 89#define _TRANS_VRR_STATUS2_A 0x6043c90#define _TRANS_VRR_STATUS2_B 0x6143c91#define _TRANS_VRR_STATUS2_C 0x6243c92#define _TRANS_VRR_STATUS2_D 0x6343c93#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)94#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)95 96#define _TRANS_PUSH_A 0x60a7097#define _TRANS_PUSH_B 0x61a7098#define _TRANS_PUSH_C 0x62a7099#define _TRANS_PUSH_D 0x63a70100#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)101#define TRANS_PUSH_EN REG_BIT(31)102#define TRANS_PUSH_SEND REG_BIT(30)103 104#define _TRANS_VRR_VSYNC_A 0x60078105#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)106#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)107#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))108#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)109#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))110 111/*CMRR Registers*/112 113#define _TRANS_CMRR_M_LO_A 0x604F0114#define TRANS_CMRR_M_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)115 116#define _TRANS_CMRR_M_HI_A 0x604F4117#define TRANS_CMRR_M_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)118 119#define _TRANS_CMRR_N_LO_A 0x604F8120#define TRANS_CMRR_N_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)121 122#define _TRANS_CMRR_N_HI_A 0x604FC123#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)124 125#define VRR_CTL_CMRR_ENABLE REG_BIT(27)126 127#endif /* __INTEL_VRR_REGS__ */128