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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef __SKL_WATERMARK_REGS_H__7#define __SKL_WATERMARK_REGS_H__8 9#include "intel_display_reg_defs.h"10 11#define _PIPEA_MBUS_DBOX_CTL 0x7003C12#define _PIPEB_MBUS_DBOX_CTL 0x7103C13#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \14 _PIPEB_MBUS_DBOX_CTL)15#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */16#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)17#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */18#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)19#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */20#define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)21#define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)22#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)23#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)24#define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)25#define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)26#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)27#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)28#define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)29#define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)30 31#define MBUS_UBOX_CTL _MMIO(0x4503C)32#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)33#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)34 35#define MBUS_CTL _MMIO(0x4438C)36#define MBUS_JOIN REG_BIT(31)37#define MBUS_HASHING_MODE_MASK REG_BIT(30)38#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)39#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)40#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)41#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)42#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)43#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)44#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)45 46/*47 * The below are numbered starting from "S1" on gen11/gen12, but starting48 * with display 13, the bspec switches to a 0-based numbering scheme49 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).50 * We'll just use the 0-based numbering here for all platforms since it's the51 * way things will be named by the hardware team going forward, plus it's more52 * consistent with how most of the rest of our registers are named.53 */54#define _DBUF_CTL_S0 0x4500855#define _DBUF_CTL_S1 0x44FE856#define _DBUF_CTL_S2 0x4430057#define _DBUF_CTL_S3 0x4430458#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \59 _DBUF_CTL_S0, \60 _DBUF_CTL_S1, \61 _DBUF_CTL_S2, \62 _DBUF_CTL_S3))63#define DBUF_POWER_REQUEST REG_BIT(31)64#define DBUF_POWER_STATE REG_BIT(30)65#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)66#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)67#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */68#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */69 70#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)71#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)72#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)73#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)74#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)75 76#define MTL_LATENCY_SAGV _MMIO(0x4578c)77#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)78 79#define LNL_PKG_C_LATENCY _MMIO(0x46460)80#define LNL_ADDED_WAKE_TIME_MASK REG_GENMASK(28, 16)81#define LNL_PKG_C_LATENCY_MASK REG_GENMASK(12, 0)82 83#endif /* __SKL_WATERMARK_REGS_H__ */84