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1/*2 * Copyright © 2013 Intel Corporation3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER21 * DEALINGS IN THE SOFTWARE.22 *23 * Authors:24 * Shobhit Kumar <shobhit.kumar@intel.com>25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>26 */27 28#include <linux/kernel.h>29#include <linux/string_helpers.h>30 31#include "i915_drv.h"32#include "intel_de.h"33#include "intel_display_types.h"34#include "intel_dsi.h"35#include "vlv_dsi_pll.h"36#include "vlv_dsi_pll_regs.h"37#include "vlv_sideband.h"38 39static const u16 lfsr_converts[] = {40 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */41 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */42 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */43 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */44};45 46/* Get DSI clock from pixel clock */47static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,48 int lane_count)49{50 u32 dsi_clk_khz;51 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);52 53 /* DSI data rate = pixel clock * bits per pixel / lane count54 pixel clock is converted from KHz to Hz */55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);56 57 return dsi_clk_khz;58}59 60static int dsi_calc_mnp(struct drm_i915_private *dev_priv,61 struct intel_crtc_state *config,62 int target_dsi_clk)63{64 unsigned int m_min, m_max, p_min = 2, p_max = 6;65 unsigned int m, n, p;66 unsigned int calc_m, calc_p;67 int delta, ref_clk;68 69 /* target_dsi_clk is expected in kHz */70 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {71 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n");72 return -ECHRNG;73 }74 75 if (IS_CHERRYVIEW(dev_priv)) {76 ref_clk = 100000;77 n = 4;78 m_min = 70;79 m_max = 96;80 } else {81 ref_clk = 25000;82 n = 1;83 m_min = 62;84 m_max = 92;85 }86 87 calc_p = p_min;88 calc_m = m_min;89 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));90 91 for (m = m_min; m <= m_max && delta; m++) {92 for (p = p_min; p <= p_max && delta; p++) {93 /*94 * Find the optimal m and p divisors with minimal delta95 * +/- the required clock96 */97 int calc_dsi_clk = (m * ref_clk) / (p * n);98 int d = abs(target_dsi_clk - calc_dsi_clk);99 if (d < delta) {100 delta = d;101 calc_m = m;102 calc_p = p;103 }104 }105 }106 107 /* register has log2(N1), this works fine for powers of two */108 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);109 config->dsi_pll.div =110 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |111 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;112 113 return 0;114}115 116static int vlv_dsi_pclk(struct intel_encoder *encoder,117 struct intel_crtc_state *config)118{119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);120 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);121 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);122 u32 dsi_clock;123 u32 pll_ctl, pll_div;124 u32 m = 0, p = 0, n;125 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;126 int i;127 128 pll_ctl = config->dsi_pll.ctrl;129 pll_div = config->dsi_pll.div;130 131 /* mask out other bits and extract the P1 divisor */132 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;133 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);134 135 /* N1 divisor */136 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;137 n = 1 << n; /* register has log2(N1) */138 139 /* mask out the other bits and extract the M1 divisor */140 pll_div &= DSI_PLL_M1_DIV_MASK;141 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;142 143 while (pll_ctl) {144 pll_ctl = pll_ctl >> 1;145 p++;146 }147 p--;148 149 if (!p) {150 drm_err(&dev_priv->drm, "wrong P1 divisor\n");151 return 0;152 }153 154 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {155 if (lfsr_converts[i] == pll_div)156 break;157 }158 159 if (i == ARRAY_SIZE(lfsr_converts)) {160 drm_err(&dev_priv->drm, "wrong m_seed programmed\n");161 return 0;162 }163 164 m = i + 62;165 166 dsi_clock = (m * refclk) / (p * n);167 168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);169}170 171/*172 * XXX: The muxing and gating is hard coded for now. Need to add support for173 * sharing PLLs with two DSI outputs.174 */175int vlv_dsi_pll_compute(struct intel_encoder *encoder,176 struct intel_crtc_state *config)177{178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);179 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);180 int pclk, dsi_clk, ret;181 182 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,183 intel_dsi->lane_count);184 185 ret = dsi_calc_mnp(dev_priv, config, dsi_clk);186 if (ret) {187 drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n");188 return ret;189 }190 191 if (intel_dsi->ports & (1 << PORT_A))192 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;193 194 if (intel_dsi->ports & (1 << PORT_C))195 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;196 197 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;198 199 drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n",200 config->dsi_pll.div, config->dsi_pll.ctrl);201 202 pclk = vlv_dsi_pclk(encoder, config);203 config->port_clock = pclk;204 205 /* FIXME definitely not right for burst/cmd mode/pixel overlap */206 config->hw.adjusted_mode.crtc_clock = pclk;207 if (intel_dsi->dual_link)208 config->hw.adjusted_mode.crtc_clock *= 2;209 210 return 0;211}212 213void vlv_dsi_pll_enable(struct intel_encoder *encoder,214 const struct intel_crtc_state *config)215{216 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);217 218 drm_dbg_kms(&dev_priv->drm, "\n");219 220 vlv_cck_get(dev_priv);221 222 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);223 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);224 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,225 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);226 227 /* wait at least 0.5 us after ungating before enabling VCO,228 * allow hrtimer subsystem optimization by relaxing timing229 */230 usleep_range(10, 50);231 232 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);233 234 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &235 DSI_PLL_LOCK, 20)) {236 237 vlv_cck_put(dev_priv);238 drm_err(&dev_priv->drm, "DSI PLL lock failed\n");239 return;240 }241 vlv_cck_put(dev_priv);242 243 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");244}245 246void vlv_dsi_pll_disable(struct intel_encoder *encoder)247{248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);249 u32 tmp;250 251 drm_dbg_kms(&dev_priv->drm, "\n");252 253 vlv_cck_get(dev_priv);254 255 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);256 tmp &= ~DSI_PLL_VCO_EN;257 tmp |= DSI_PLL_LDO_GATE;258 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);259 260 vlv_cck_put(dev_priv);261}262 263bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)264{265 bool enabled;266 u32 val;267 u32 mask;268 269 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;270 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);271 enabled = (val & mask) == mask;272 273 if (!enabled)274 return false;275 276 /*277 * Dividers must be programmed with valid values. As per BSEPC, for278 * GEMINLAKE only PORT A divider values are checked while for BXT279 * both divider values are validated. Check this here for280 * paranoia, since BIOS is known to misconfigure PLLs in this way at281 * times, and since accessing DSI registers with invalid dividers282 * causes a system hang.283 */284 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);285 if (IS_GEMINILAKE(dev_priv)) {286 if (!(val & BXT_DSIA_16X_MASK)) {287 drm_dbg(&dev_priv->drm,288 "Invalid PLL divider (%08x)\n", val);289 enabled = false;290 }291 } else {292 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {293 drm_dbg(&dev_priv->drm,294 "Invalid PLL divider (%08x)\n", val);295 enabled = false;296 }297 }298 299 return enabled;300}301 302void bxt_dsi_pll_disable(struct intel_encoder *encoder)303{304 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);305 306 drm_dbg_kms(&dev_priv->drm, "\n");307 308 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);309 310 /*311 * PLL lock should deassert within 200us.312 * Wait up to 1ms before timing out.313 */314 if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE,315 BXT_DSI_PLL_LOCKED, 1))316 drm_err(&dev_priv->drm,317 "Timeout waiting for PLL lock deassertion\n");318}319 320u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,321 struct intel_crtc_state *config)322{323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);324 u32 pll_ctl, pll_div;325 326 drm_dbg_kms(&dev_priv->drm, "\n");327 328 vlv_cck_get(dev_priv);329 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);330 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);331 vlv_cck_put(dev_priv);332 333 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;334 config->dsi_pll.div = pll_div;335 336 return vlv_dsi_pclk(encoder, config);337}338 339static int bxt_dsi_pclk(struct intel_encoder *encoder,340 const struct intel_crtc_state *config)341{342 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);343 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);344 u32 dsi_ratio, dsi_clk;345 346 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;347 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;348 349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);350}351 352u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,353 struct intel_crtc_state *config)354{355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);356 u32 pclk;357 358 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);359 360 pclk = bxt_dsi_pclk(encoder, config);361 362 drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk);363 return pclk;364}365 366void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)367{368 struct intel_display *display = to_intel_display(encoder);369 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);370 u32 temp;371 372 temp = intel_de_read(display, MIPI_CTRL(display, port));373 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;374 intel_de_write(display, MIPI_CTRL(display, port),375 temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);376}377 378static void glk_dsi_program_esc_clock(struct drm_device *dev,379 const struct intel_crtc_state *config)380{381 struct drm_i915_private *dev_priv = to_i915(dev);382 u32 dsi_rate = 0;383 u32 pll_ratio = 0;384 u32 ddr_clk = 0;385 u32 div1_value = 0;386 u32 div2_value = 0;387 u32 txesc1_div = 0;388 u32 txesc2_div = 0;389 390 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;391 392 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;393 394 ddr_clk = dsi_rate / 2;395 396 /* Variable divider value */397 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);398 399 /* Calculate TXESC1 divider */400 if (div1_value <= 10)401 txesc1_div = div1_value;402 else if ((div1_value > 10) && (div1_value <= 20))403 txesc1_div = DIV_ROUND_UP(div1_value, 2);404 else if ((div1_value > 20) && (div1_value <= 30))405 txesc1_div = DIV_ROUND_UP(div1_value, 4);406 else if ((div1_value > 30) && (div1_value <= 40))407 txesc1_div = DIV_ROUND_UP(div1_value, 6);408 else if ((div1_value > 40) && (div1_value <= 50))409 txesc1_div = DIV_ROUND_UP(div1_value, 8);410 else411 txesc1_div = 10;412 413 /* Calculate TXESC2 divider */414 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);415 416 txesc2_div = min_t(u32, div2_value, 10);417 418 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1,419 (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);420 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2,421 (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);422}423 424/* Program BXT Mipi clocks and dividers */425static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,426 const struct intel_crtc_state *config)427{428 struct drm_i915_private *dev_priv = to_i915(dev);429 u32 tmp;430 u32 dsi_rate = 0;431 u32 pll_ratio = 0;432 u32 rx_div;433 u32 tx_div;434 u32 rx_div_upper;435 u32 rx_div_lower;436 u32 mipi_8by3_divider;437 438 /* Clear old configurations */439 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);440 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));441 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));442 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));443 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));444 445 /* Get the current DSI rate(actual) */446 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;447 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;448 449 /*450 * tx clock should be <= 20MHz and the div value must be451 * subtracted by 1 as per bspec452 */453 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;454 /*455 * rx clock should be <= 150MHz and the div value must be456 * subtracted by 1 as per bspec457 */458 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;459 460 /*461 * rx divider value needs to be updated in the462 * two differnt bit fields in the register hence splitting the463 * rx divider value accordingly464 */465 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;466 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;467 468 mipi_8by3_divider = 0x2;469 470 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);471 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);472 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);473 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);474 475 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);476}477 478int bxt_dsi_pll_compute(struct intel_encoder *encoder,479 struct intel_crtc_state *config)480{481 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);482 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);483 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;484 u32 dsi_clk;485 int pclk;486 487 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,488 intel_dsi->lane_count);489 490 /*491 * From clock diagram, to get PLL ratio divider, divide double of DSI492 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to493 * round 'up' the result494 */495 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);496 497 if (IS_BROXTON(dev_priv)) {498 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;499 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;500 } else {501 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;502 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;503 }504 505 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {506 drm_err(&dev_priv->drm,507 "Can't get a suitable ratio from DSI PLL ratios\n");508 return -ECHRNG;509 } else510 drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n");511 512 /*513 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x514 * Spec says both have to be programmed, even if one is not getting515 * used. Configure MIPI_CLOCK_CTL dividers in modeset516 */517 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;518 519 /* As per recommendation from hardware team,520 * Prog PVD ratio =1 if dsi ratio <= 50521 */522 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)523 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;524 525 pclk = bxt_dsi_pclk(encoder, config);526 config->port_clock = pclk;527 528 /* FIXME definitely not right for burst/cmd mode/pixel overlap */529 config->hw.adjusted_mode.crtc_clock = pclk;530 if (intel_dsi->dual_link)531 config->hw.adjusted_mode.crtc_clock *= 2;532 533 return 0;534}535 536void bxt_dsi_pll_enable(struct intel_encoder *encoder,537 const struct intel_crtc_state *config)538{539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);541 enum port port;542 543 drm_dbg_kms(&dev_priv->drm, "\n");544 545 /* Configure PLL vales */546 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);547 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL);548 549 /* Program TX, RX, Dphy clocks */550 if (IS_BROXTON(dev_priv)) {551 for_each_dsi_port(port, intel_dsi->ports)552 bxt_dsi_program_clocks(encoder->base.dev, port, config);553 } else {554 glk_dsi_program_esc_clock(encoder->base.dev, config);555 }556 557 /* Enable DSI PLL */558 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);559 560 /* Timeout and fail if PLL not locked */561 if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,562 BXT_DSI_PLL_LOCKED, 1)) {563 drm_err(&dev_priv->drm,564 "Timed out waiting for DSI PLL to lock\n");565 return;566 }567 568 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");569}570 571void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)572{573 struct intel_display *display = to_intel_display(encoder);574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);575 u32 tmp;576 577 /* Clear old configurations */578 if (IS_BROXTON(dev_priv)) {579 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);580 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));581 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));582 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));583 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));584 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp);585 } else {586 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0);587 588 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0);589 }590 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);591}592 593static void assert_dsi_pll(struct drm_i915_private *i915, bool state)594{595 bool cur_state;596 597 vlv_cck_get(i915);598 cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;599 vlv_cck_put(i915);600 601 I915_STATE_WARN(i915, cur_state != state,602 "DSI PLL state assertion failure (expected %s, current %s)\n",603 str_on_off(state), str_on_off(cur_state));604}605 606void assert_dsi_pll_enabled(struct drm_i915_private *i915)607{608 assert_dsi_pll(i915, true);609}610 611void assert_dsi_pll_disabled(struct drm_i915_private *i915)612{613 assert_dsi_pll(i915, false);614}615