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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2014-2018 Intel Corporation4 */5 6#ifndef _INTEL_LRC_REG_H_7#define _INTEL_LRC_REG_H_8 9#include <linux/types.h>10 11#define CTX_DESC_FORCE_RESTORE BIT_ULL(2)12 13/* GEN8 to GEN12 Reg State Context */14#define CTX_CONTEXT_CONTROL (0x02 + 1)15#define CTX_RING_HEAD (0x04 + 1)16#define CTX_RING_TAIL (0x06 + 1)17#define CTX_RING_START (0x08 + 1)18#define CTX_RING_CTL (0x0a + 1)19#define CTX_BB_STATE (0x10 + 1)20#define CTX_TIMESTAMP (0x22 + 1)21#define CTX_PDP3_UDW (0x24 + 1)22#define CTX_PDP3_LDW (0x26 + 1)23#define CTX_PDP2_UDW (0x28 + 1)24#define CTX_PDP2_LDW (0x2a + 1)25#define CTX_PDP1_UDW (0x2c + 1)26#define CTX_PDP1_LDW (0x2e + 1)27#define CTX_PDP0_UDW (0x30 + 1)28#define CTX_PDP0_LDW (0x32 + 1)29#define CTX_R_PWR_CLK_STATE (0x42 + 1)30 31#define GEN9_CTX_RING_MI_MODE 0x5432 33#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \34 u32 *reg_state__ = (reg_state); \35 const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \36 (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \37 (reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \38} while (0)39 40#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \41 u32 *reg_state__ = (reg_state); \42 const u64 addr__ = px_dma((ppgtt)->pd); \43 (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \44 (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \45} while (0)46 47#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1748#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x2649#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1950#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A51#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD52 53#define GEN8_EXECLISTS_STATUS_BUF 0x37054#define GEN11_EXECLISTS_STATUS_BUF2 0x3c055 56/*57 * The docs specify that the write pointer wraps around after 5h, "After status58 * is written out to the last available status QW at offset 5h, this pointer59 * wraps to 0."60 *61 * Therefore, one must infer than even though there are 3 bits available, 6 and62 * 7 appear to be * reserved.63 */64#define GEN8_CSB_ENTRIES 665#define GEN8_CSB_PTR_MASK 0x766#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)67#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)68 69#define GEN11_CSB_ENTRIES 1270#define GEN11_CSB_PTR_MASK 0xf71#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)72#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)73 74#define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */75#define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */76/* in Gen12 ID 0x7FF is reserved to indicate idle */77#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)78/* in Xe_HP ID 0xFFFF is reserved to indicate "invalid context" */79#define XEHP_MAX_CONTEXT_HW_ID 0xFFFF80 81#endif /* _INTEL_LRC_REG_H_ */82