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1// SPDX-License-Identifier: MIT2/*3 * Copyright © 2008-2021 Intel Corporation4 */5 6#include <drm/drm_cache.h>7 8#include "gem/i915_gem_internal.h"9 10#include "gen2_engine_cs.h"11#include "gen6_engine_cs.h"12#include "gen6_ppgtt.h"13#include "gen7_renderclear.h"14#include "i915_drv.h"15#include "i915_irq.h"16#include "i915_mitigations.h"17#include "i915_reg.h"18#include "intel_breadcrumbs.h"19#include "intel_context.h"20#include "intel_engine_regs.h"21#include "intel_gt.h"22#include "intel_gt_irq.h"23#include "intel_gt_regs.h"24#include "intel_reset.h"25#include "intel_ring.h"26#include "shmem_utils.h"27#include "intel_engine_heartbeat.h"28#include "intel_engine_pm.h"29 30/* Rough estimate of the typical request size, performing a flush,31 * set-context and then emitting the batch.32 */33#define LEGACY_REQUEST_SIZE 20034 35static void set_hwstam(struct intel_engine_cs *engine, u32 mask)36{37 /*38 * Keep the render interrupt unmasked as this papers over39 * lost interrupts following a reset.40 */41 if (engine->class == RENDER_CLASS) {42 if (GRAPHICS_VER(engine->i915) >= 6)43 mask &= ~BIT(0);44 else45 mask &= ~I915_USER_INTERRUPT;46 }47 48 intel_engine_set_hwsp_writemask(engine, mask);49}50 51static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)52{53 u32 addr;54 55 addr = lower_32_bits(phys);56 if (GRAPHICS_VER(engine->i915) >= 4)57 addr |= (phys >> 28) & 0xf0;58 59 intel_uncore_write(engine->uncore, HWS_PGA, addr);60}61 62static struct page *status_page(struct intel_engine_cs *engine)63{64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj;65 66 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));67 return sg_page(obj->mm.pages->sgl);68}69 70static void ring_setup_phys_status_page(struct intel_engine_cs *engine)71{72 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));73 set_hwstam(engine, ~0u);74}75 76static void set_hwsp(struct intel_engine_cs *engine, u32 offset)77{78 i915_reg_t hwsp;79 80 /*81 * The ring status page addresses are no longer next to the rest of82 * the ring registers as of gen7.83 */84 if (GRAPHICS_VER(engine->i915) == 7) {85 switch (engine->id) {86 /*87 * No more rings exist on Gen7. Default case is only to shut up88 * gcc switch check warning.89 */90 default:91 GEM_BUG_ON(engine->id);92 fallthrough;93 case RCS0:94 hwsp = RENDER_HWS_PGA_GEN7;95 break;96 case BCS0:97 hwsp = BLT_HWS_PGA_GEN7;98 break;99 case VCS0:100 hwsp = BSD_HWS_PGA_GEN7;101 break;102 case VECS0:103 hwsp = VEBOX_HWS_PGA_GEN7;104 break;105 }106 } else if (GRAPHICS_VER(engine->i915) == 6) {107 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);108 } else {109 hwsp = RING_HWS_PGA(engine->mmio_base);110 }111 112 intel_uncore_write_fw(engine->uncore, hwsp, offset);113 intel_uncore_posting_read_fw(engine->uncore, hwsp);114}115 116static void flush_cs_tlb(struct intel_engine_cs *engine)117{118 if (!IS_GRAPHICS_VER(engine->i915, 6, 7))119 return;120 121 /* ring should be idle before issuing a sync flush*/122 if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)123 drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",124 engine->name);125 126 ENGINE_WRITE_FW(engine, RING_INSTPM,127 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |128 INSTPM_SYNC_FLUSH));129 if (__intel_wait_for_register_fw(engine->uncore,130 RING_INSTPM(engine->mmio_base),131 INSTPM_SYNC_FLUSH, 0,132 2000, 0, NULL))133 ENGINE_TRACE(engine,134 "wait for SyncFlush to complete for TLB invalidation timed out\n");135}136 137static void ring_setup_status_page(struct intel_engine_cs *engine)138{139 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));140 set_hwstam(engine, ~0u);141 142 flush_cs_tlb(engine);143}144 145static struct i915_address_space *vm_alias(struct i915_address_space *vm)146{147 if (i915_is_ggtt(vm))148 vm = &i915_vm_to_ggtt(vm)->alias->vm;149 150 return vm;151}152 153static u32 pp_dir(struct i915_address_space *vm)154{155 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir;156}157 158static void set_pp_dir(struct intel_engine_cs *engine)159{160 struct i915_address_space *vm = vm_alias(engine->gt->vm);161 162 if (!vm)163 return;164 165 ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);166 ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));167 168 if (GRAPHICS_VER(engine->i915) >= 7) {169 ENGINE_WRITE_FW(engine,170 RING_MODE_GEN7,171 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));172 }173}174 175static bool stop_ring(struct intel_engine_cs *engine)176{177 /* Empty the ring by skipping to the end */178 ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));179 ENGINE_POSTING_READ(engine, RING_HEAD);180 181 /* The ring must be empty before it is disabled */182 ENGINE_WRITE_FW(engine, RING_CTL, 0);183 ENGINE_POSTING_READ(engine, RING_CTL);184 185 /* Then reset the disabled ring */186 ENGINE_WRITE_FW(engine, RING_HEAD, 0);187 ENGINE_WRITE_FW(engine, RING_TAIL, 0);188 189 return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;190}191 192static int xcs_resume(struct intel_engine_cs *engine)193{194 struct intel_ring *ring = engine->legacy.ring;195 196 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",197 ring->head, ring->tail);198 199 /*200 * Double check the ring is empty & disabled before we resume. Called201 * from atomic context during PCI probe, so _hardirq().202 */203 intel_synchronize_hardirq(engine->i915);204 if (!stop_ring(engine))205 goto err;206 207 if (HWS_NEEDS_PHYSICAL(engine->i915))208 ring_setup_phys_status_page(engine);209 else210 ring_setup_status_page(engine);211 212 intel_breadcrumbs_reset(engine->breadcrumbs);213 214 /* Enforce ordering by reading HEAD register back */215 ENGINE_POSTING_READ(engine, RING_HEAD);216 217 /*218 * Initialize the ring. This must happen _after_ we've cleared the ring219 * registers with the above sequence (the readback of the HEAD registers220 * also enforces ordering), otherwise the hw might lose the new ring221 * register values.222 */223 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));224 225 /* Check that the ring offsets point within the ring! */226 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));227 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));228 intel_ring_update_space(ring);229 230 set_pp_dir(engine);231 232 /* First wake the ring up to an empty/idle ring */233 ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);234 ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);235 ENGINE_POSTING_READ(engine, RING_TAIL);236 237 ENGINE_WRITE_FW(engine, RING_CTL,238 RING_CTL_SIZE(ring->size) | RING_VALID);239 240 /* If the head is still not zero, the ring is dead */241 if (__intel_wait_for_register_fw(engine->uncore,242 RING_CTL(engine->mmio_base),243 RING_VALID, RING_VALID,244 5000, 0, NULL))245 goto err;246 247 if (GRAPHICS_VER(engine->i915) > 2)248 ENGINE_WRITE_FW(engine,249 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));250 251 /* Now awake, let it get started */252 if (ring->tail != ring->head) {253 ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail);254 ENGINE_POSTING_READ(engine, RING_TAIL);255 }256 257 /* Papering over lost _interrupts_ immediately following the restart */258 intel_engine_signal_breadcrumbs(engine);259 return 0;260 261err:262 drm_err(&engine->i915->drm,263 "%s initialization failed; "264 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",265 engine->name,266 ENGINE_READ(engine, RING_CTL),267 ENGINE_READ(engine, RING_CTL) & RING_VALID,268 ENGINE_READ(engine, RING_HEAD), ring->head,269 ENGINE_READ(engine, RING_TAIL), ring->tail,270 ENGINE_READ(engine, RING_START),271 i915_ggtt_offset(ring->vma));272 return -EIO;273}274 275static void sanitize_hwsp(struct intel_engine_cs *engine)276{277 struct intel_timeline *tl;278 279 list_for_each_entry(tl, &engine->status_page.timelines, engine_link)280 intel_timeline_reset_seqno(tl);281}282 283static void xcs_sanitize(struct intel_engine_cs *engine)284{285 /*286 * Poison residual state on resume, in case the suspend didn't!287 *288 * We have to assume that across suspend/resume (or other loss289 * of control) that the contents of our pinned buffers has been290 * lost, replaced by garbage. Since this doesn't always happen,291 * let's poison such state so that we more quickly spot when292 * we falsely assume it has been preserved.293 */294 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))295 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);296 297 /*298 * The kernel_context HWSP is stored in the status_page. As above,299 * that may be lost on resume/initialisation, and so we need to300 * reset the value in the HWSP.301 */302 sanitize_hwsp(engine);303 304 /* And scrub the dirty cachelines for the HWSP */305 drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);306 307 intel_engine_reset_pinned_contexts(engine);308}309 310static void reset_prepare(struct intel_engine_cs *engine)311{312 /*313 * We stop engines, otherwise we might get failed reset and a314 * dead gpu (on elk). Also as modern gpu as kbl can suffer315 * from system hang if batchbuffer is progressing when316 * the reset is issued, regardless of READY_TO_RESET ack.317 * Thus assume it is best to stop engines on all gens318 * where we have a gpu reset.319 *320 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)321 *322 * WaMediaResetMainRingCleanup:ctg,elk (presumably)323 * WaClearRingBufHeadRegAtInit:ctg,elk324 *325 * FIXME: Wa for more modern gens needs to be validated326 */327 ENGINE_TRACE(engine, "\n");328 intel_engine_stop_cs(engine);329 330 if (!stop_ring(engine)) {331 /* G45 ring initialization often fails to reset head to zero */332 ENGINE_TRACE(engine,333 "HEAD not reset to zero, "334 "{ CTL:%08x, HEAD:%08x, TAIL:%08x, START:%08x }\n",335 ENGINE_READ_FW(engine, RING_CTL),336 ENGINE_READ_FW(engine, RING_HEAD),337 ENGINE_READ_FW(engine, RING_TAIL),338 ENGINE_READ_FW(engine, RING_START));339 if (!stop_ring(engine)) {340 drm_err(&engine->i915->drm,341 "failed to set %s head to zero "342 "ctl %08x head %08x tail %08x start %08x\n",343 engine->name,344 ENGINE_READ_FW(engine, RING_CTL),345 ENGINE_READ_FW(engine, RING_HEAD),346 ENGINE_READ_FW(engine, RING_TAIL),347 ENGINE_READ_FW(engine, RING_START));348 }349 }350}351 352static void reset_rewind(struct intel_engine_cs *engine, bool stalled)353{354 struct i915_request *pos, *rq;355 unsigned long flags;356 u32 head;357 358 rq = NULL;359 spin_lock_irqsave(&engine->sched_engine->lock, flags);360 rcu_read_lock();361 list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) {362 if (!__i915_request_is_complete(pos)) {363 rq = pos;364 break;365 }366 }367 rcu_read_unlock();368 369 /*370 * The guilty request will get skipped on a hung engine.371 *372 * Users of client default contexts do not rely on logical373 * state preserved between batches so it is safe to execute374 * queued requests following the hang. Non default contexts375 * rely on preserved state, so skipping a batch loses the376 * evolution of the state and it needs to be considered corrupted.377 * Executing more queued batches on top of corrupted state is378 * risky. But we take the risk by trying to advance through379 * the queued requests in order to make the client behaviour380 * more predictable around resets, by not throwing away random381 * amount of batches it has prepared for execution. Sophisticated382 * clients can use gem_reset_stats_ioctl and dma fence status383 * (exported via sync_file info ioctl on explicit fences) to observe384 * when it loses the context state and should rebuild accordingly.385 *386 * The context ban, and ultimately the client ban, mechanism are safety387 * valves if client submission ends up resulting in nothing more than388 * subsequent hangs.389 */390 391 if (rq) {392 /*393 * Try to restore the logical GPU state to match the394 * continuation of the request queue. If we skip the395 * context/PD restore, then the next request may try to execute396 * assuming that its context is valid and loaded on the GPU and397 * so may try to access invalid memory, prompting repeated GPU398 * hangs.399 *400 * If the request was guilty, we still restore the logical401 * state in case the next request requires it (e.g. the402 * aliasing ppgtt), but skip over the hung batch.403 *404 * If the request was innocent, we try to replay the request405 * with the restored context.406 */407 __i915_request_reset(rq, stalled);408 409 GEM_BUG_ON(rq->ring != engine->legacy.ring);410 head = rq->head;411 } else {412 head = engine->legacy.ring->tail;413 }414 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);415 416 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);417}418 419static void reset_finish(struct intel_engine_cs *engine)420{421}422 423static void reset_cancel(struct intel_engine_cs *engine)424{425 struct i915_request *request;426 unsigned long flags;427 428 spin_lock_irqsave(&engine->sched_engine->lock, flags);429 430 /* Mark all submitted requests as skipped. */431 list_for_each_entry(request, &engine->sched_engine->requests, sched.link)432 i915_request_put(i915_request_mark_eio(request));433 intel_engine_signal_breadcrumbs(engine);434 435 /* Remaining _unready_ requests will be nop'ed when submitted */436 437 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);438}439 440static void i9xx_submit_request(struct i915_request *request)441{442 i915_request_submit(request);443 wmb(); /* paranoid flush writes out of the WCB before mmio */444 445 ENGINE_WRITE(request->engine, RING_TAIL,446 intel_ring_set_tail(request->ring, request->tail));447}448 449static void __ring_context_fini(struct intel_context *ce)450{451 i915_vma_put(ce->state);452}453 454static void ring_context_destroy(struct kref *ref)455{456 struct intel_context *ce = container_of(ref, typeof(*ce), ref);457 458 GEM_BUG_ON(intel_context_is_pinned(ce));459 460 if (ce->state)461 __ring_context_fini(ce);462 463 intel_context_fini(ce);464 intel_context_free(ce);465}466 467static int ring_context_init_default_state(struct intel_context *ce,468 struct i915_gem_ww_ctx *ww)469{470 struct drm_i915_gem_object *obj = ce->state->obj;471 void *vaddr;472 473 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);474 if (IS_ERR(vaddr))475 return PTR_ERR(vaddr);476 477 shmem_read(ce->default_state, 0, vaddr, ce->engine->context_size);478 479 i915_gem_object_flush_map(obj);480 __i915_gem_object_release_map(obj);481 482 __set_bit(CONTEXT_VALID_BIT, &ce->flags);483 return 0;484}485 486static int ring_context_pre_pin(struct intel_context *ce,487 struct i915_gem_ww_ctx *ww,488 void **unused)489{490 struct i915_address_space *vm;491 int err = 0;492 493 if (ce->default_state &&494 !test_bit(CONTEXT_VALID_BIT, &ce->flags)) {495 err = ring_context_init_default_state(ce, ww);496 if (err)497 return err;498 }499 500 vm = vm_alias(ce->vm);501 if (vm)502 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww);503 504 return err;505}506 507static void __context_unpin_ppgtt(struct intel_context *ce)508{509 struct i915_address_space *vm;510 511 vm = vm_alias(ce->vm);512 if (vm)513 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));514}515 516static void ring_context_unpin(struct intel_context *ce)517{518}519 520static void ring_context_post_unpin(struct intel_context *ce)521{522 __context_unpin_ppgtt(ce);523}524 525static struct i915_vma *526alloc_context_vma(struct intel_engine_cs *engine)527{528 struct drm_i915_private *i915 = engine->i915;529 struct drm_i915_gem_object *obj;530 struct i915_vma *vma;531 int err;532 533 obj = i915_gem_object_create_shmem(i915, engine->context_size);534 if (IS_ERR(obj))535 return ERR_CAST(obj);536 537 /*538 * Try to make the context utilize L3 as well as LLC.539 *540 * On VLV we don't have L3 controls in the PTEs so we541 * shouldn't touch the cache level, especially as that542 * would make the object snooped which might have a543 * negative performance impact.544 *545 * Snooping is required on non-llc platforms in execlist546 * mode, but since all GGTT accesses use PAT entry 0 we547 * get snooping anyway regardless of cache_level.548 *549 * This is only applicable for Ivy Bridge devices since550 * later platforms don't have L3 control bits in the PTE.551 */552 if (IS_IVYBRIDGE(i915))553 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);554 555 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);556 if (IS_ERR(vma)) {557 err = PTR_ERR(vma);558 goto err_obj;559 }560 561 return vma;562 563err_obj:564 i915_gem_object_put(obj);565 return ERR_PTR(err);566}567 568static int ring_context_alloc(struct intel_context *ce)569{570 struct intel_engine_cs *engine = ce->engine;571 572 if (!intel_context_has_own_state(ce))573 ce->default_state = engine->default_state;574 575 /* One ringbuffer to rule them all */576 GEM_BUG_ON(!engine->legacy.ring);577 ce->ring = engine->legacy.ring;578 ce->timeline = intel_timeline_get(engine->legacy.timeline);579 580 GEM_BUG_ON(ce->state);581 if (engine->context_size) {582 struct i915_vma *vma;583 584 vma = alloc_context_vma(engine);585 if (IS_ERR(vma))586 return PTR_ERR(vma);587 588 ce->state = vma;589 }590 591 return 0;592}593 594static int ring_context_pin(struct intel_context *ce, void *unused)595{596 return 0;597}598 599static void ring_context_reset(struct intel_context *ce)600{601 intel_ring_reset(ce->ring, ce->ring->emit);602 clear_bit(CONTEXT_VALID_BIT, &ce->flags);603}604 605static void ring_context_revoke(struct intel_context *ce,606 struct i915_request *rq,607 unsigned int preempt_timeout_ms)608{609 struct intel_engine_cs *engine;610 611 if (!rq || !i915_request_is_active(rq))612 return;613 614 engine = rq->engine;615 lockdep_assert_held(&engine->sched_engine->lock);616 list_for_each_entry_continue(rq, &engine->sched_engine->requests,617 sched.link)618 if (rq->context == ce) {619 i915_request_set_error_once(rq, -EIO);620 __i915_request_skip(rq);621 }622}623 624static void ring_context_cancel_request(struct intel_context *ce,625 struct i915_request *rq)626{627 struct intel_engine_cs *engine = NULL;628 629 i915_request_active_engine(rq, &engine);630 631 if (engine && intel_engine_pulse(engine))632 intel_gt_handle_error(engine->gt, engine->mask, 0,633 "request cancellation by %s",634 current->comm);635}636 637static const struct intel_context_ops ring_context_ops = {638 .alloc = ring_context_alloc,639 640 .cancel_request = ring_context_cancel_request,641 642 .revoke = ring_context_revoke,643 644 .pre_pin = ring_context_pre_pin,645 .pin = ring_context_pin,646 .unpin = ring_context_unpin,647 .post_unpin = ring_context_post_unpin,648 649 .enter = intel_context_enter_engine,650 .exit = intel_context_exit_engine,651 652 .reset = ring_context_reset,653 .destroy = ring_context_destroy,654};655 656static int load_pd_dir(struct i915_request *rq,657 struct i915_address_space *vm,658 u32 valid)659{660 const struct intel_engine_cs * const engine = rq->engine;661 u32 *cs;662 663 cs = intel_ring_begin(rq, 12);664 if (IS_ERR(cs))665 return PTR_ERR(cs);666 667 *cs++ = MI_LOAD_REGISTER_IMM(1);668 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));669 *cs++ = valid;670 671 *cs++ = MI_LOAD_REGISTER_IMM(1);672 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));673 *cs++ = pp_dir(vm);674 675 /* Stall until the page table load is complete? */676 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;677 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));678 *cs++ = intel_gt_scratch_offset(engine->gt,679 INTEL_GT_SCRATCH_FIELD_DEFAULT);680 681 *cs++ = MI_LOAD_REGISTER_IMM(1);682 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));683 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);684 685 intel_ring_advance(rq, cs);686 687 return rq->engine->emit_flush(rq, EMIT_FLUSH);688}689 690static int mi_set_context(struct i915_request *rq,691 struct intel_context *ce,692 u32 flags)693{694 struct intel_engine_cs *engine = rq->engine;695 struct drm_i915_private *i915 = engine->i915;696 enum intel_engine_id id;697 const int num_engines =698 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;699 bool force_restore = false;700 int len;701 u32 *cs;702 703 len = 4;704 if (GRAPHICS_VER(i915) == 7)705 len += 2 + (num_engines ? 4 * num_engines + 6 : 0);706 else if (GRAPHICS_VER(i915) == 5)707 len += 2;708 if (flags & MI_FORCE_RESTORE) {709 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);710 flags &= ~MI_FORCE_RESTORE;711 force_restore = true;712 len += 2;713 }714 715 cs = intel_ring_begin(rq, len);716 if (IS_ERR(cs))717 return PTR_ERR(cs);718 719 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */720 if (GRAPHICS_VER(i915) == 7) {721 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;722 if (num_engines) {723 struct intel_engine_cs *signaller;724 725 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);726 for_each_engine(signaller, engine->gt, id) {727 if (signaller == engine)728 continue;729 730 *cs++ = i915_mmio_reg_offset(731 RING_PSMI_CTL(signaller->mmio_base));732 *cs++ = _MASKED_BIT_ENABLE(733 GEN6_PSMI_SLEEP_MSG_DISABLE);734 }735 }736 } else if (GRAPHICS_VER(i915) == 5) {737 /*738 * This w/a is only listed for pre-production ilk a/b steppings,739 * but is also mentioned for programming the powerctx. To be740 * safe, just apply the workaround; we do not use SyncFlush so741 * this should never take effect and so be a no-op!742 */743 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;744 }745 746 if (force_restore) {747 /*748 * The HW doesn't handle being told to restore the current749 * context very well. Quite often it likes goes to go off and750 * sulk, especially when it is meant to be reloading PP_DIR.751 * A very simple fix to force the reload is to simply switch752 * away from the current context and back again.753 *754 * Note that the kernel_context will contain random state755 * following the INHIBIT_RESTORE. We accept this since we756 * never use the kernel_context state; it is merely a757 * placeholder we use to flush other contexts.758 */759 *cs++ = MI_SET_CONTEXT;760 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |761 MI_MM_SPACE_GTT |762 MI_RESTORE_INHIBIT;763 }764 765 *cs++ = MI_NOOP;766 *cs++ = MI_SET_CONTEXT;767 *cs++ = i915_ggtt_offset(ce->state) | flags;768 /*769 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP770 * WaMiSetContext_Hang:snb,ivb,vlv771 */772 *cs++ = MI_NOOP;773 774 if (GRAPHICS_VER(i915) == 7) {775 if (num_engines) {776 struct intel_engine_cs *signaller;777 i915_reg_t last_reg = INVALID_MMIO_REG; /* keep gcc quiet */778 779 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);780 for_each_engine(signaller, engine->gt, id) {781 if (signaller == engine)782 continue;783 784 last_reg = RING_PSMI_CTL(signaller->mmio_base);785 *cs++ = i915_mmio_reg_offset(last_reg);786 *cs++ = _MASKED_BIT_DISABLE(787 GEN6_PSMI_SLEEP_MSG_DISABLE);788 }789 790 /* Insert a delay before the next switch! */791 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;792 *cs++ = i915_mmio_reg_offset(last_reg);793 *cs++ = intel_gt_scratch_offset(engine->gt,794 INTEL_GT_SCRATCH_FIELD_DEFAULT);795 *cs++ = MI_NOOP;796 }797 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;798 } else if (GRAPHICS_VER(i915) == 5) {799 *cs++ = MI_SUSPEND_FLUSH;800 }801 802 intel_ring_advance(rq, cs);803 804 return 0;805}806 807static int remap_l3_slice(struct i915_request *rq, int slice)808{809#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))810 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];811 int i;812 813 if (!remap_info)814 return 0;815 816 cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2);817 if (IS_ERR(cs))818 return PTR_ERR(cs);819 820 /*821 * Note: We do not worry about the concurrent register cacheline hang822 * here because no other code should access these registers other than823 * at initialization time.824 */825 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW);826 for (i = 0; i < L3LOG_DW; i++) {827 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));828 *cs++ = remap_info[i];829 }830 *cs++ = MI_NOOP;831 intel_ring_advance(rq, cs);832 833 return 0;834#undef L3LOG_DW835}836 837static int remap_l3(struct i915_request *rq)838{839 struct i915_gem_context *ctx = i915_request_gem_context(rq);840 int i, err;841 842 if (!ctx || !ctx->remap_slice)843 return 0;844 845 for (i = 0; i < MAX_L3_SLICES; i++) {846 if (!(ctx->remap_slice & BIT(i)))847 continue;848 849 err = remap_l3_slice(rq, i);850 if (err)851 return err;852 }853 854 ctx->remap_slice = 0;855 return 0;856}857 858static int switch_mm(struct i915_request *rq, struct i915_address_space *vm)859{860 int ret;861 862 if (!vm)863 return 0;864 865 ret = rq->engine->emit_flush(rq, EMIT_FLUSH);866 if (ret)867 return ret;868 869 /*870 * Not only do we need a full barrier (post-sync write) after871 * invalidating the TLBs, but we need to wait a little bit872 * longer. Whether this is merely delaying us, or the873 * subsequent flush is a key part of serialising with the874 * post-sync op, this extra pass appears vital before a875 * mm switch!876 */877 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G);878 if (ret)879 return ret;880 881 return rq->engine->emit_flush(rq, EMIT_INVALIDATE);882}883 884static int clear_residuals(struct i915_request *rq)885{886 struct intel_engine_cs *engine = rq->engine;887 int ret;888 889 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));890 if (ret)891 return ret;892 893 if (engine->kernel_context->state) {894 ret = mi_set_context(rq,895 engine->kernel_context,896 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT);897 if (ret)898 return ret;899 }900 901 ret = engine->emit_bb_start(rq,902 i915_vma_offset(engine->wa_ctx.vma), 0,903 0);904 if (ret)905 return ret;906 907 ret = engine->emit_flush(rq, EMIT_FLUSH);908 if (ret)909 return ret;910 911 /* Always invalidate before the next switch_mm() */912 return engine->emit_flush(rq, EMIT_INVALIDATE);913}914 915static int switch_context(struct i915_request *rq)916{917 struct intel_engine_cs *engine = rq->engine;918 struct intel_context *ce = rq->context;919 void **residuals = NULL;920 int ret;921 922 GEM_BUG_ON(HAS_EXECLISTS(engine->i915));923 924 if (engine->wa_ctx.vma && ce != engine->kernel_context) {925 if (engine->wa_ctx.vma->private != ce &&926 i915_mitigate_clear_residuals()) {927 ret = clear_residuals(rq);928 if (ret)929 return ret;930 931 residuals = &engine->wa_ctx.vma->private;932 }933 }934 935 ret = switch_mm(rq, vm_alias(ce->vm));936 if (ret)937 return ret;938 939 if (ce->state) {940 u32 flags;941 942 GEM_BUG_ON(engine->id != RCS0);943 944 /* For resource streamer on HSW+ and power context elsewhere */945 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN);946 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN);947 948 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT;949 if (test_bit(CONTEXT_VALID_BIT, &ce->flags))950 flags |= MI_RESTORE_EXT_STATE_EN;951 else952 flags |= MI_RESTORE_INHIBIT;953 954 ret = mi_set_context(rq, ce, flags);955 if (ret)956 return ret;957 }958 959 ret = remap_l3(rq);960 if (ret)961 return ret;962 963 /*964 * Now past the point of no return, this request _will_ be emitted.965 *966 * Or at least this preamble will be emitted, the request may be967 * interrupted prior to submitting the user payload. If so, we968 * still submit the "empty" request in order to preserve global969 * state tracking such as this, our tracking of the current970 * dirty context.971 */972 if (residuals) {973 intel_context_put(*residuals);974 *residuals = intel_context_get(ce);975 }976 977 return 0;978}979 980static int ring_request_alloc(struct i915_request *request)981{982 int ret;983 984 GEM_BUG_ON(!intel_context_is_pinned(request->context));985 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb);986 987 /*988 * Flush enough space to reduce the likelihood of waiting after989 * we start building the request - in which case we will just990 * have to repeat work.991 */992 request->reserved_space += LEGACY_REQUEST_SIZE;993 994 /* Unconditionally invalidate GPU caches and TLBs. */995 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);996 if (ret)997 return ret;998 999 ret = switch_context(request);1000 if (ret)1001 return ret;1002 1003 request->reserved_space -= LEGACY_REQUEST_SIZE;1004 return 0;1005}1006 1007static void gen6_bsd_submit_request(struct i915_request *request)1008{1009 struct intel_uncore *uncore = request->engine->uncore;1010 1011 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);1012 1013 /* Every tail move must follow the sequence below */1014 1015 /* Disable notification that the ring is IDLE. The GT1016 * will then assume that it is busy and bring it out of rc6.1017 */1018 intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),1019 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));1020 1021 /* Clear the context id. Here be magic! */1022 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);1023 1024 /* Wait for the ring not to be idle, i.e. for it to wake up. */1025 if (__intel_wait_for_register_fw(uncore,1026 RING_PSMI_CTL(GEN6_BSD_RING_BASE),1027 GEN6_BSD_SLEEP_INDICATOR,1028 0,1029 1000, 0, NULL))1030 drm_err(&uncore->i915->drm,1031 "timed out waiting for the BSD ring to wake up\n");1032 1033 /* Now that the ring is fully powered up, update the tail */1034 i9xx_submit_request(request);1035 1036 /* Let the ring send IDLE messages to the GT again,1037 * and so let it sleep to conserve power when idle.1038 */1039 intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),1040 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));1041 1042 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);1043}1044 1045static void i9xx_set_default_submission(struct intel_engine_cs *engine)1046{1047 engine->submit_request = i9xx_submit_request;1048}1049 1050static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)1051{1052 engine->submit_request = gen6_bsd_submit_request;1053}1054 1055static void ring_release(struct intel_engine_cs *engine)1056{1057 struct drm_i915_private *i915 = engine->i915;1058 1059 drm_WARN_ON(&i915->drm, GRAPHICS_VER(i915) > 2 &&1060 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);1061 1062 intel_engine_cleanup_common(engine);1063 1064 if (engine->wa_ctx.vma) {1065 intel_context_put(engine->wa_ctx.vma->private);1066 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);1067 }1068 1069 intel_ring_unpin(engine->legacy.ring);1070 intel_ring_put(engine->legacy.ring);1071 1072 intel_timeline_unpin(engine->legacy.timeline);1073 intel_timeline_put(engine->legacy.timeline);1074}1075 1076static void irq_handler(struct intel_engine_cs *engine, u16 iir)1077{1078 intel_engine_signal_breadcrumbs(engine);1079}1080 1081static void setup_irq(struct intel_engine_cs *engine)1082{1083 struct drm_i915_private *i915 = engine->i915;1084 1085 intel_engine_set_irq_handler(engine, irq_handler);1086 1087 if (GRAPHICS_VER(i915) >= 6) {1088 engine->irq_enable = gen6_irq_enable;1089 engine->irq_disable = gen6_irq_disable;1090 } else if (GRAPHICS_VER(i915) >= 5) {1091 engine->irq_enable = gen5_irq_enable;1092 engine->irq_disable = gen5_irq_disable;1093 } else if (GRAPHICS_VER(i915) >= 3) {1094 engine->irq_enable = gen3_irq_enable;1095 engine->irq_disable = gen3_irq_disable;1096 } else {1097 engine->irq_enable = gen2_irq_enable;1098 engine->irq_disable = gen2_irq_disable;1099 }1100}1101 1102static void add_to_engine(struct i915_request *rq)1103{1104 lockdep_assert_held(&rq->engine->sched_engine->lock);1105 list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);1106}1107 1108static void remove_from_engine(struct i915_request *rq)1109{1110 spin_lock_irq(&rq->engine->sched_engine->lock);1111 list_del_init(&rq->sched.link);1112 1113 /* Prevent further __await_execution() registering a cb, then flush */1114 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);1115 1116 spin_unlock_irq(&rq->engine->sched_engine->lock);1117 1118 i915_request_notify_execute_cb_imm(rq);1119}1120 1121static void setup_common(struct intel_engine_cs *engine)1122{1123 struct drm_i915_private *i915 = engine->i915;1124 1125 /* gen8+ are only supported with execlists */1126 GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);1127 1128 setup_irq(engine);1129 1130 engine->resume = xcs_resume;1131 engine->sanitize = xcs_sanitize;1132 1133 engine->reset.prepare = reset_prepare;1134 engine->reset.rewind = reset_rewind;1135 engine->reset.cancel = reset_cancel;1136 engine->reset.finish = reset_finish;1137 1138 engine->add_active_request = add_to_engine;1139 engine->remove_active_request = remove_from_engine;1140 1141 engine->cops = &ring_context_ops;1142 engine->request_alloc = ring_request_alloc;1143 1144 /*1145 * Using a global execution timeline; the previous final breadcrumb is1146 * equivalent to our next initial bread so we can elide1147 * engine->emit_init_breadcrumb().1148 */1149 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;1150 if (GRAPHICS_VER(i915) == 5)1151 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;1152 1153 engine->set_default_submission = i9xx_set_default_submission;1154 1155 if (GRAPHICS_VER(i915) >= 6)1156 engine->emit_bb_start = gen6_emit_bb_start;1157 else if (GRAPHICS_VER(i915) >= 4)1158 engine->emit_bb_start = gen4_emit_bb_start;1159 else if (IS_I830(i915) || IS_I845G(i915))1160 engine->emit_bb_start = i830_emit_bb_start;1161 else1162 engine->emit_bb_start = gen3_emit_bb_start;1163}1164 1165static void setup_rcs(struct intel_engine_cs *engine)1166{1167 struct drm_i915_private *i915 = engine->i915;1168 1169 if (HAS_L3_DPF(i915))1170 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;1171 1172 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;1173 1174 if (GRAPHICS_VER(i915) >= 7) {1175 engine->emit_flush = gen7_emit_flush_rcs;1176 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;1177 } else if (GRAPHICS_VER(i915) == 6) {1178 engine->emit_flush = gen6_emit_flush_rcs;1179 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;1180 } else if (GRAPHICS_VER(i915) == 5) {1181 engine->emit_flush = gen4_emit_flush_rcs;1182 } else {1183 if (GRAPHICS_VER(i915) < 4)1184 engine->emit_flush = gen2_emit_flush;1185 else1186 engine->emit_flush = gen4_emit_flush_rcs;1187 engine->irq_enable_mask = I915_USER_INTERRUPT;1188 }1189 1190 if (IS_HASWELL(i915))1191 engine->emit_bb_start = hsw_emit_bb_start;1192}1193 1194static void setup_vcs(struct intel_engine_cs *engine)1195{1196 struct drm_i915_private *i915 = engine->i915;1197 1198 if (GRAPHICS_VER(i915) >= 6) {1199 /* gen6 bsd needs a special wa for tail updates */1200 if (GRAPHICS_VER(i915) == 6)1201 engine->set_default_submission = gen6_bsd_set_default_submission;1202 engine->emit_flush = gen6_emit_flush_vcs;1203 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;1204 1205 if (GRAPHICS_VER(i915) == 6)1206 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;1207 else1208 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;1209 } else {1210 engine->emit_flush = gen4_emit_flush_vcs;1211 if (GRAPHICS_VER(i915) == 5)1212 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;1213 else1214 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;1215 }1216}1217 1218static void setup_bcs(struct intel_engine_cs *engine)1219{1220 struct drm_i915_private *i915 = engine->i915;1221 1222 engine->emit_flush = gen6_emit_flush_xcs;1223 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;1224 1225 if (GRAPHICS_VER(i915) == 6)1226 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;1227 else1228 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;1229}1230 1231static void setup_vecs(struct intel_engine_cs *engine)1232{1233 struct drm_i915_private *i915 = engine->i915;1234 1235 GEM_BUG_ON(GRAPHICS_VER(i915) < 7);1236 1237 engine->emit_flush = gen6_emit_flush_xcs;1238 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;1239 engine->irq_enable = hsw_irq_enable_vecs;1240 engine->irq_disable = hsw_irq_disable_vecs;1241 1242 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;1243}1244 1245static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,1246 struct i915_vma * const vma)1247{1248 return gen7_setup_clear_gpr_bb(engine, vma);1249}1250 1251static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine,1252 struct i915_gem_ww_ctx *ww,1253 struct i915_vma *vma)1254{1255 int err;1256 1257 err = i915_vma_pin_ww(vma, ww, 0, 0, PIN_USER | PIN_HIGH);1258 if (err)1259 return err;1260 1261 err = i915_vma_sync(vma);1262 if (err)1263 goto err_unpin;1264 1265 err = gen7_ctx_switch_bb_setup(engine, vma);1266 if (err)1267 goto err_unpin;1268 1269 engine->wa_ctx.vma = vma;1270 return 0;1271 1272err_unpin:1273 i915_vma_unpin(vma);1274 return err;1275}1276 1277static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)1278{1279 struct drm_i915_gem_object *obj;1280 struct i915_vma *vma;1281 int size, err;1282 1283 if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)1284 return NULL;1285 1286 err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);1287 if (err < 0)1288 return ERR_PTR(err);1289 if (!err)1290 return NULL;1291 1292 size = ALIGN(err, PAGE_SIZE);1293 1294 obj = i915_gem_object_create_internal(engine->i915, size);1295 if (IS_ERR(obj))1296 return ERR_CAST(obj);1297 1298 vma = i915_vma_instance(obj, engine->gt->vm, NULL);1299 if (IS_ERR(vma)) {1300 i915_gem_object_put(obj);1301 return ERR_CAST(vma);1302 }1303 1304 vma->private = intel_context_create(engine); /* dummy residuals */1305 if (IS_ERR(vma->private)) {1306 err = PTR_ERR(vma->private);1307 vma->private = NULL;1308 i915_gem_object_put(obj);1309 return ERR_PTR(err);1310 }1311 1312 return vma;1313}1314 1315int intel_ring_submission_setup(struct intel_engine_cs *engine)1316{1317 struct i915_gem_ww_ctx ww;1318 struct intel_timeline *timeline;1319 struct intel_ring *ring;1320 struct i915_vma *gen7_wa_vma;1321 int err;1322 1323 setup_common(engine);1324 1325 switch (engine->class) {1326 case RENDER_CLASS:1327 setup_rcs(engine);1328 break;1329 case VIDEO_DECODE_CLASS:1330 setup_vcs(engine);1331 break;1332 case COPY_ENGINE_CLASS:1333 setup_bcs(engine);1334 break;1335 case VIDEO_ENHANCEMENT_CLASS:1336 setup_vecs(engine);1337 break;1338 default:1339 MISSING_CASE(engine->class);1340 return -ENODEV;1341 }1342 1343 timeline = intel_timeline_create_from_engine(engine,1344 I915_GEM_HWS_SEQNO_ADDR);1345 if (IS_ERR(timeline)) {1346 err = PTR_ERR(timeline);1347 goto err;1348 }1349 GEM_BUG_ON(timeline->has_initial_breadcrumb);1350 1351 ring = intel_engine_create_ring(engine, SZ_16K);1352 if (IS_ERR(ring)) {1353 err = PTR_ERR(ring);1354 goto err_timeline;1355 }1356 1357 GEM_BUG_ON(engine->legacy.ring);1358 engine->legacy.ring = ring;1359 engine->legacy.timeline = timeline;1360 1361 gen7_wa_vma = gen7_ctx_vma(engine);1362 if (IS_ERR(gen7_wa_vma)) {1363 err = PTR_ERR(gen7_wa_vma);1364 goto err_ring;1365 }1366 1367 i915_gem_ww_ctx_init(&ww, false);1368 1369retry:1370 err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww);1371 if (!err && gen7_wa_vma)1372 err = i915_gem_object_lock(gen7_wa_vma->obj, &ww);1373 if (!err)1374 err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww);1375 if (!err)1376 err = intel_timeline_pin(timeline, &ww);1377 if (!err) {1378 err = intel_ring_pin(ring, &ww);1379 if (err)1380 intel_timeline_unpin(timeline);1381 }1382 if (err)1383 goto out;1384 1385 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);1386 1387 if (gen7_wa_vma) {1388 err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma);1389 if (err) {1390 intel_ring_unpin(ring);1391 intel_timeline_unpin(timeline);1392 }1393 }1394 1395out:1396 if (err == -EDEADLK) {1397 err = i915_gem_ww_ctx_backoff(&ww);1398 if (!err)1399 goto retry;1400 }1401 i915_gem_ww_ctx_fini(&ww);1402 if (err)1403 goto err_gen7_put;1404 1405 /* Finally, take ownership and responsibility for cleanup! */1406 engine->release = ring_release;1407 1408 return 0;1409 1410err_gen7_put:1411 if (gen7_wa_vma) {1412 intel_context_put(gen7_wa_vma->private);1413 i915_gem_object_put(gen7_wa_vma->obj);1414 }1415err_ring:1416 intel_ring_put(ring);1417err_timeline:1418 intel_timeline_put(timeline);1419err:1420 intel_engine_cleanup_common(engine);1421 return err;1422}1423 1424#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)1425#include "selftest_ring_submission.c"1426#endif1427