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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2014-2021 Intel Corporation4 */5 6#ifndef _ABI_GUC_ACTIONS_ABI_H7#define _ABI_GUC_ACTIONS_ABI_H8 9/**10 * DOC: HOST2GUC_SELF_CFG11 *12 * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_.13 *14 * This message must be sent as `MMIO HXG Message`_.15 *16 * +---+-------+--------------------------------------------------------------+17 * | | Bits | Description |18 * +===+=======+==============================================================+19 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |20 * | +-------+--------------------------------------------------------------+21 * | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ |22 * | +-------+--------------------------------------------------------------+23 * | | 27:16 | DATA0 = MBZ |24 * | +-------+--------------------------------------------------------------+25 * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 |26 * +---+-------+--------------------------------------------------------------+27 * | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ |28 * | +-------+--------------------------------------------------------------+29 * | | 15:0 | **KLV_LEN** - KLV length |30 * | | | |31 * | | | - 32 bit KLV = 1 |32 * | | | - 64 bit KLV = 2 |33 * +---+-------+--------------------------------------------------------------+34 * | 2 | 31:0 | **VALUE32** - Bits 31-0 of the KLV value |35 * +---+-------+--------------------------------------------------------------+36 * | 3 | 31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2) |37 * +---+-------+--------------------------------------------------------------+38 *39 * +---+-------+--------------------------------------------------------------+40 * | | Bits | Description |41 * +===+=======+==============================================================+42 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ |43 * | +-------+--------------------------------------------------------------+44 * | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ |45 * | +-------+--------------------------------------------------------------+46 * | | 27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized |47 * +---+-------+--------------------------------------------------------------+48 */49#define GUC_ACTION_HOST2GUC_SELF_CFG 0x050850 51#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)52#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA053#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffU << 16)54#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0)55#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn56#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn57 58#define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN59#define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM GUC_HXG_RESPONSE_MSG_0_DATA060 61/**62 * DOC: HOST2GUC_CONTROL_CTB63 *64 * This H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.65 *66 * This message must be sent as `MMIO HXG Message`_.67 *68 * +---+-------+--------------------------------------------------------------+69 * | | Bits | Description |70 * +===+=======+==============================================================+71 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |72 * | +-------+--------------------------------------------------------------+73 * | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ |74 * | +-------+--------------------------------------------------------------+75 * | | 27:16 | DATA0 = MBZ |76 * | +-------+--------------------------------------------------------------+77 * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509 |78 * +---+-------+--------------------------------------------------------------+79 * | 1 | 31:0 | **CONTROL** - control `CTB based communication`_ |80 * | | | |81 * | | | - _`GUC_CTB_CONTROL_DISABLE` = 0 |82 * | | | - _`GUC_CTB_CONTROL_ENABLE` = 1 |83 * +---+-------+--------------------------------------------------------------+84 *85 * +---+-------+--------------------------------------------------------------+86 * | | Bits | Description |87 * +===+=======+==============================================================+88 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ |89 * | +-------+--------------------------------------------------------------+90 * | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ |91 * | +-------+--------------------------------------------------------------+92 * | | 27:0 | DATA0 = MBZ |93 * +---+-------+--------------------------------------------------------------+94 */95#define GUC_ACTION_HOST2GUC_CONTROL_CTB 0x450996 97#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)98#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA099#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL GUC_HXG_REQUEST_MSG_n_DATAn100#define GUC_CTB_CONTROL_DISABLE 0u101#define GUC_CTB_CONTROL_ENABLE 1u102 103#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN104#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_0_MBZ GUC_HXG_RESPONSE_MSG_0_DATA0105 106/* legacy definitions */107 108enum intel_guc_action {109 INTEL_GUC_ACTION_DEFAULT = 0x0,110 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,111 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,112 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,113 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,114 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,115 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,116 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,117 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,118 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,119 INTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506,120 INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV = 0x509,121 INTEL_GUC_ACTION_SCHED_CONTEXT = 0x1000,122 INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001,123 INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,124 INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,125 INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,126 INTEL_GUC_ACTION_V69_SET_CONTEXT_PRIORITY = 0x1005,127 INTEL_GUC_ACTION_V69_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,128 INTEL_GUC_ACTION_V69_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,129 INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,130 INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,131 INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,132 INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,133 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,134 INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,135 INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,136 INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,137 INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,138 INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,139 INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,140 INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,141 INTEL_GUC_ACTION_TLB_INVALIDATION = 0x7000,142 INTEL_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,143 INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,144 INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,145 INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,146 INTEL_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,147 INTEL_GUC_ACTION_LIMIT148};149 150enum intel_guc_rc_options {151 INTEL_GUCRC_HOST_CONTROL,152 INTEL_GUCRC_FIRMWARE_CONTROL,153};154 155enum intel_guc_preempt_options {156 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,157 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,158};159 160enum intel_guc_report_status {161 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,162 INTEL_GUC_REPORT_STATUS_ACKED = 0x1,163 INTEL_GUC_REPORT_STATUS_ERROR = 0x2,164 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,165};166 167enum intel_guc_sleep_state_status {168 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,169 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,170 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3171#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000172};173 174#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)175#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4176#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)177#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)178 179enum intel_guc_state_capture_event_status {180 INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0,181 INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1,182};183 184#define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x000000FF185 186#define INTEL_GUC_TLB_INVAL_TYPE_MASK REG_GENMASK(7, 0)187#define INTEL_GUC_TLB_INVAL_MODE_MASK REG_GENMASK(11, 8)188#define INTEL_GUC_TLB_INVAL_FLUSH_CACHE REG_BIT(31)189 190enum intel_guc_tlb_invalidation_type {191 INTEL_GUC_TLB_INVAL_ENGINES = 0x0,192 INTEL_GUC_TLB_INVAL_GUC = 0x3,193};194 195/*196 * 0: Heavy mode of Invalidation:197 * The pipeline of the engine(s) for which the invalidation is targeted to is198 * blocked, and all the in-flight transactions are guaranteed to be Globally199 * Observed before completing the TLB invalidation200 * 1: Lite mode of Invalidation:201 * TLBs of the targeted engine(s) are immediately invalidated.202 * In-flight transactions are NOT guaranteed to be Globally Observed before203 * completing TLB invalidation.204 * Light Invalidation Mode is to be used only when205 * it can be guaranteed (by SW) that the address translations remain invariant206 * for the in-flight transactions across the TLB invalidation. In other words,207 * this mode can be used when the TLB invalidation is intended to clear out the208 * stale cached translations that are no longer in use. Light Invalidation Mode209 * is much faster than the Heavy Invalidation Mode, as it does not wait for the210 * in-flight transactions to be GOd.211 */212enum intel_guc_tlb_inval_mode {213 INTEL_GUC_TLB_INVAL_MODE_HEAVY = 0x0,214 INTEL_GUC_TLB_INVAL_MODE_LITE = 0x1,215};216 217#endif /* _ABI_GUC_ACTIONS_ABI_H */218