819 lines · c
1/*2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE21 * SOFTWARE.22 *23 * Authors:24 * Ke Yu25 * Zhiyuan Lv <zhiyuan.lv@intel.com>26 *27 * Contributors:28 * Terrence Xu <terrence.xu@intel.com>29 * Changbin Du <changbin.du@intel.com>30 * Bing Niu <bing.niu@intel.com>31 * Zhi Wang <zhi.a.wang@intel.com>32 *33 */34 35#include "i915_drv.h"36#include "i915_reg.h"37#include "gvt.h"38 39#include "display/bxt_dpio_phy_regs.h"40#include "display/i9xx_plane_regs.h"41#include "display/intel_cursor_regs.h"42#include "display/intel_display.h"43#include "display/intel_dpio_phy.h"44#include "display/intel_sprite_regs.h"45 46static int get_edp_pipe(struct intel_vgpu *vgpu)47{48 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);49 int pipe = -1;50 51 switch (data & TRANS_DDI_EDP_INPUT_MASK) {52 case TRANS_DDI_EDP_INPUT_A_ON:53 case TRANS_DDI_EDP_INPUT_A_ONOFF:54 pipe = PIPE_A;55 break;56 case TRANS_DDI_EDP_INPUT_B_ONOFF:57 pipe = PIPE_B;58 break;59 case TRANS_DDI_EDP_INPUT_C_ONOFF:60 pipe = PIPE_C;61 break;62 }63 return pipe;64}65 66static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)67{68 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;69 70 if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE))71 return 0;72 73 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))74 return 0;75 return 1;76}77 78int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)79{80 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;81 82 if (drm_WARN_ON(&dev_priv->drm,83 pipe < PIPE_A || pipe >= I915_MAX_PIPES))84 return -EINVAL;85 86 if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE)87 return 1;88 89 if (edp_pipe_is_enabled(vgpu) &&90 get_edp_pipe(vgpu) == pipe)91 return 1;92 return 0;93}94 95static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {96 {97/* EDID with 1024x768 as its resolution */98 /*Header*/99 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,100 /* Vendor & Product Identification */101 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,102 /* Version & Revision */103 0x01, 0x04,104 /* Basic Display Parameters & Features */105 0xa5, 0x34, 0x20, 0x78, 0x23,106 /* Color Characteristics */107 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,108 /* Established Timings: maximum resolution is 1024x768 */109 0x21, 0x08, 0x00,110 /* Standard Timings. All invalid */111 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,112 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,113 /* 18 Byte Data Blocks 1: invalid */114 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,115 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,116 /* 18 Byte Data Blocks 2: invalid */117 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,118 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,119 /* 18 Byte Data Blocks 3: invalid */120 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,121 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,122 /* 18 Byte Data Blocks 4: invalid */123 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,124 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,125 /* Extension Block Count */126 0x00,127 /* Checksum */128 0xef,129 },130 {131/* EDID with 1920x1200 as its resolution */132 /*Header*/133 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,134 /* Vendor & Product Identification */135 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,136 /* Version & Revision */137 0x01, 0x04,138 /* Basic Display Parameters & Features */139 0xa5, 0x34, 0x20, 0x78, 0x23,140 /* Color Characteristics */141 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,142 /* Established Timings: maximum resolution is 1024x768 */143 0x21, 0x08, 0x00,144 /*145 * Standard Timings.146 * below new resolutions can be supported:147 * 1920x1080, 1280x720, 1280x960, 1280x1024,148 * 1440x900, 1600x1200, 1680x1050149 */150 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,151 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,152 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */153 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,154 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,155 /* 18 Byte Data Blocks 2: invalid */156 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,157 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,158 /* 18 Byte Data Blocks 3: invalid */159 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,160 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,161 /* 18 Byte Data Blocks 4: invalid */162 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,163 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,164 /* Extension Block Count */165 0x00,166 /* Checksum */167 0x45,168 },169};170 171#define DPCD_HEADER_SIZE 0xb172 173/* let the virtual display supports DP1.2 */174static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {175 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00176};177 178static void emulate_monitor_status_change(struct intel_vgpu *vgpu)179{180 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;181 int pipe;182 183 if (IS_BROXTON(dev_priv)) {184 enum transcoder trans;185 enum port port;186 187 /* Clear PIPE, DDI, PHY, HPD before setting new */188 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=189 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |190 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |191 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));192 193 for_each_pipe(dev_priv, pipe) {194 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &=195 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);196 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE;197 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;198 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK;199 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE;200 }201 202 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {203 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &=204 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |205 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);206 }207 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=208 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |209 TRANS_DDI_PORT_MASK);210 211 for (port = PORT_A; port <= PORT_C; port++) {212 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=213 ~BXT_PHY_LANE_ENABLED;214 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=215 (BXT_PHY_CMNLANE_POWERDOWN_ACK |216 BXT_PHY_LANE_POWERDOWN_ACK);217 218 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=219 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |220 PORT_PLL_REF_SEL | PORT_PLL_LOCK |221 PORT_PLL_ENABLE);222 223 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=224 ~(DDI_INIT_DISPLAY_DETECTED |225 DDI_BUF_CTL_ENABLE);226 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;227 }228 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=229 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);230 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=231 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);232 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=233 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);234 /* No hpd_invert set in vgpu vbt, need to clear invert mask */235 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;236 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;237 238 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));239 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=240 ~PHY_POWER_GOOD;241 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=242 ~PHY_POWER_GOOD;243 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);244 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);245 246 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;247 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;248 249 /*250 * Only 1 PIPE enabled in current vGPU display and PIPE_A is251 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,252 * TRANSCODER_A can be enabled. PORT_x depends on the input of253 * setup_virtual_dp_monitor.254 */255 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;256 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;257 258 /*259 * Golden M/N are calculated based on:260 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),261 * DP link clk 1620 MHz and non-constant_n.262 * TODO: calculate DP link symbol clk and stream clk m/n.263 */264 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);265 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;266 vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;267 vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;268 vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;269 270 /* Enable per-DDI/PORT vreg */271 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {272 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);273 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=274 PHY_POWER_GOOD;275 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=276 BIT(30);277 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=278 BXT_PHY_LANE_ENABLED;279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=280 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |281 BXT_PHY_LANE_POWERDOWN_ACK);282 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=283 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |284 PORT_PLL_REF_SEL | PORT_PLL_LOCK |285 PORT_PLL_ENABLE);286 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=287 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=289 ~DDI_BUF_IS_IDLE;290 vgpu_vreg_t(vgpu,291 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |=292 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |293 TRANS_DDI_FUNC_ENABLE);294 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=295 PORTA_HOTPLUG_ENABLE;296 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=297 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);298 }299 300 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {301 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;302 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);303 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=304 PHY_POWER_GOOD;305 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=306 BIT(30);307 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=308 BXT_PHY_LANE_ENABLED;309 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=310 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |311 BXT_PHY_LANE_POWERDOWN_ACK);312 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=313 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |314 PORT_PLL_REF_SEL | PORT_PLL_LOCK |315 PORT_PLL_ENABLE);316 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=317 DDI_BUF_CTL_ENABLE;318 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=319 ~DDI_BUF_IS_IDLE;320 vgpu_vreg_t(vgpu,321 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=322 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |323 (PORT_B << TRANS_DDI_PORT_SHIFT) |324 TRANS_DDI_FUNC_ENABLE);325 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=326 PORTB_HOTPLUG_ENABLE;327 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=328 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);329 }330 331 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {332 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;333 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);334 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=335 PHY_POWER_GOOD;336 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=337 BIT(30);338 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=339 BXT_PHY_LANE_ENABLED;340 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=341 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |342 BXT_PHY_LANE_POWERDOWN_ACK);343 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=344 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |345 PORT_PLL_REF_SEL | PORT_PLL_LOCK |346 PORT_PLL_ENABLE);347 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=348 DDI_BUF_CTL_ENABLE;349 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=350 ~DDI_BUF_IS_IDLE;351 vgpu_vreg_t(vgpu,352 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=353 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |354 (PORT_B << TRANS_DDI_PORT_SHIFT) |355 TRANS_DDI_FUNC_ENABLE);356 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=357 PORTC_HOTPLUG_ENABLE;358 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=359 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);360 }361 362 return;363 }364 365 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |366 SDE_PORTC_HOTPLUG_CPT |367 SDE_PORTD_HOTPLUG_CPT);368 369 if (IS_SKYLAKE(dev_priv) ||370 IS_KABYLAKE(dev_priv) ||371 IS_COFFEELAKE(dev_priv) ||372 IS_COMETLAKE(dev_priv)) {373 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |374 SDE_PORTE_HOTPLUG_SPT);375 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=376 SKL_FUSE_DOWNLOAD_STATUS |377 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |378 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |379 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);380 /*381 * Only 1 PIPE enabled in current vGPU display and PIPE_A is382 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,383 * TRANSCODER_A can be enabled. PORT_x depends on the input of384 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x385 * so we fixed to DPLL0 here.386 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode387 */388 vgpu_vreg_t(vgpu, DPLL_CTRL1) =389 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);390 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=391 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);392 vgpu_vreg_t(vgpu, LCPLL1_CTL) =393 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;394 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);395 /*396 * Golden M/N are calculated based on:397 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),398 * DP link clk 1620 MHz and non-constant_n.399 * TODO: calculate DP link symbol clk and stream clk m/n.400 */401 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);402 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;403 vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;404 vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;405 vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;406 }407 408 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {409 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=410 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);411 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=412 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);413 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=414 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);415 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;416 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=417 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |418 TRANS_DDI_PORT_MASK);419 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=420 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |421 (PORT_B << TRANS_DDI_PORT_SHIFT) |422 TRANS_DDI_FUNC_ENABLE);423 if (IS_BROADWELL(dev_priv)) {424 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=425 ~PORT_CLK_SEL_MASK;426 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=427 PORT_CLK_SEL_LCPLL_810;428 }429 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;430 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;431 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;432 }433 434 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {435 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=436 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);437 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=438 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);439 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=440 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);441 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;442 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=443 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |444 TRANS_DDI_PORT_MASK);445 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=446 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |447 (PORT_C << TRANS_DDI_PORT_SHIFT) |448 TRANS_DDI_FUNC_ENABLE);449 if (IS_BROADWELL(dev_priv)) {450 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=451 ~PORT_CLK_SEL_MASK;452 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=453 PORT_CLK_SEL_LCPLL_810;454 }455 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;456 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;457 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;458 }459 460 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {461 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=462 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);463 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=464 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);465 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=466 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);467 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;468 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=469 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |470 TRANS_DDI_PORT_MASK);471 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=472 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |473 (PORT_D << TRANS_DDI_PORT_SHIFT) |474 TRANS_DDI_FUNC_ENABLE);475 if (IS_BROADWELL(dev_priv)) {476 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=477 ~PORT_CLK_SEL_MASK;478 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=479 PORT_CLK_SEL_LCPLL_810;480 }481 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;482 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;483 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;484 }485 486 if ((IS_SKYLAKE(dev_priv) ||487 IS_KABYLAKE(dev_priv) ||488 IS_COFFEELAKE(dev_priv) ||489 IS_COMETLAKE(dev_priv)) &&490 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {491 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;492 }493 494 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {495 if (IS_BROADWELL(dev_priv))496 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=497 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);498 else499 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;500 501 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;502 }503 504 /* Clear host CRT status, so guest couldn't detect this host CRT. */505 if (IS_BROADWELL(dev_priv))506 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;507 508 /* Disable Primary/Sprite/Cursor plane */509 for_each_pipe(dev_priv, pipe) {510 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE;511 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;512 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK;513 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE;514 }515 516 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;517}518 519static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)520{521 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);522 523 kfree(port->edid);524 port->edid = NULL;525 526 kfree(port->dpcd);527 port->dpcd = NULL;528}529 530static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)531{532 struct intel_vgpu_vblank_timer *vblank_timer;533 struct intel_vgpu *vgpu;534 535 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer);536 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);537 538 /* Set vblank emulation request per-vGPU bit */539 intel_gvt_request_service(vgpu->gvt,540 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);541 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);542 return HRTIMER_RESTART;543}544 545static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,546 int type, unsigned int resolution)547{548 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;549 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);550 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;551 552 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))553 return -EINVAL;554 555 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);556 if (!port->edid)557 return -ENOMEM;558 559 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);560 if (!port->dpcd) {561 kfree(port->edid);562 return -ENOMEM;563 }564 565 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],566 EDID_SIZE);567 port->edid->data_valid = true;568 569 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);570 port->dpcd->data_valid = true;571 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;572 port->type = type;573 port->id = resolution;574 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC;575 vgpu->display.port_num = port_num;576 577 /* Init hrtimer based on default refresh rate */578 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);579 vblank_timer->timer.function = vblank_timer_fn;580 vblank_timer->vrefresh_k = port->vrefresh_k;581 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);582 583 emulate_monitor_status_change(vgpu);584 585 return 0;586}587 588/**589 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer590 * @vgpu: vGPU operated591 * @turnon: Turn ON/OFF vblank_timer592 *593 * This function is used to turn on/off or update the per-vGPU vblank_timer594 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated595 * if guest changed the refresh rate.596 *597 */598void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)599{600 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;601 struct intel_vgpu_port *port =602 intel_vgpu_port(vgpu, vgpu->display.port_num);603 604 if (turnon) {605 /*606 * Skip the re-enable if already active and vrefresh unchanged.607 * Otherwise, stop timer if already active and restart with new608 * period.609 */610 if (vblank_timer->vrefresh_k != port->vrefresh_k ||611 !hrtimer_active(&vblank_timer->timer)) {612 /* Stop timer before start with new period if active */613 if (hrtimer_active(&vblank_timer->timer))614 hrtimer_cancel(&vblank_timer->timer);615 616 /* Make sure new refresh rate updated to timer period */617 vblank_timer->vrefresh_k = port->vrefresh_k;618 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);619 hrtimer_start(&vblank_timer->timer,620 ktime_add_ns(ktime_get(), vblank_timer->period),621 HRTIMER_MODE_ABS);622 }623 } else {624 /* Caller request to stop vblank */625 hrtimer_cancel(&vblank_timer->timer);626 }627}628 629static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)630{631 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;632 struct intel_vgpu_irq *irq = &vgpu->irq;633 int vblank_event[] = {634 [PIPE_A] = PIPE_A_VBLANK,635 [PIPE_B] = PIPE_B_VBLANK,636 [PIPE_C] = PIPE_C_VBLANK,637 };638 int event;639 640 if (pipe < PIPE_A || pipe > PIPE_C)641 return;642 643 for_each_set_bit(event, irq->flip_done_event[pipe],644 INTEL_GVT_EVENT_MAX) {645 clear_bit(event, irq->flip_done_event[pipe]);646 if (!pipe_is_enabled(vgpu, pipe))647 continue;648 649 intel_vgpu_trigger_virtual_event(vgpu, event);650 }651 652 if (pipe_is_enabled(vgpu, pipe)) {653 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++;654 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);655 }656}657 658void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)659{660 int pipe;661 662 mutex_lock(&vgpu->vgpu_lock);663 for_each_pipe(vgpu->gvt->gt->i915, pipe)664 emulate_vblank_on_pipe(vgpu, pipe);665 mutex_unlock(&vgpu->vgpu_lock);666}667 668/**669 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU670 * @vgpu: a vGPU671 * @connected: link state672 *673 * This function is used to trigger hotplug interrupt for vGPU674 *675 */676void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)677{678 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;679 680 /* TODO: add more platforms support */681 if (IS_SKYLAKE(i915) ||682 IS_KABYLAKE(i915) ||683 IS_COFFEELAKE(i915) ||684 IS_COMETLAKE(i915)) {685 if (connected) {686 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=687 SFUSE_STRAP_DDID_DETECTED;688 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;689 } else {690 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=691 ~SFUSE_STRAP_DDID_DETECTED;692 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;693 }694 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;695 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=696 PORTD_HOTPLUG_STATUS_MASK;697 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);698 } else if (IS_BROXTON(i915)) {699 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {700 if (connected) {701 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=702 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);703 } else {704 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=705 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);706 }707 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=708 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);709 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=710 ~PORTA_HOTPLUG_STATUS_MASK;711 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=712 PORTA_HOTPLUG_LONG_DETECT;713 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);714 }715 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {716 if (connected) {717 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=718 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);719 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=720 SFUSE_STRAP_DDIB_DETECTED;721 } else {722 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=723 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);724 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=725 ~SFUSE_STRAP_DDIB_DETECTED;726 }727 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=728 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);729 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=730 ~PORTB_HOTPLUG_STATUS_MASK;731 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=732 PORTB_HOTPLUG_LONG_DETECT;733 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);734 }735 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {736 if (connected) {737 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=738 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);739 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=740 SFUSE_STRAP_DDIC_DETECTED;741 } else {742 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=743 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);744 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=745 ~SFUSE_STRAP_DDIC_DETECTED;746 }747 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=748 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);749 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=750 ~PORTC_HOTPLUG_STATUS_MASK;751 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=752 PORTC_HOTPLUG_LONG_DETECT;753 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);754 }755 }756}757 758/**759 * intel_vgpu_clean_display - clean vGPU virtual display emulation760 * @vgpu: a vGPU761 *762 * This function is used to clean vGPU virtual display emulation stuffs763 *764 */765void intel_vgpu_clean_display(struct intel_vgpu *vgpu)766{767 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;768 769 if (IS_SKYLAKE(dev_priv) ||770 IS_KABYLAKE(dev_priv) ||771 IS_COFFEELAKE(dev_priv) ||772 IS_COMETLAKE(dev_priv))773 clean_virtual_dp_monitor(vgpu, PORT_D);774 else775 clean_virtual_dp_monitor(vgpu, PORT_B);776 777 vgpu_update_vblank_emulation(vgpu, false);778}779 780/**781 * intel_vgpu_init_display- initialize vGPU virtual display emulation782 * @vgpu: a vGPU783 * @resolution: resolution index for intel_vgpu_edid784 *785 * This function is used to initialize vGPU virtual display emulation stuffs786 *787 * Returns:788 * Zero on success, negative error code if failed.789 *790 */791int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)792{793 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;794 795 intel_vgpu_init_i2c_edid(vgpu);796 797 if (IS_SKYLAKE(dev_priv) ||798 IS_KABYLAKE(dev_priv) ||799 IS_COFFEELAKE(dev_priv) ||800 IS_COMETLAKE(dev_priv))801 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,802 resolution);803 else804 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,805 resolution);806}807 808/**809 * intel_vgpu_reset_display- reset vGPU virtual display emulation810 * @vgpu: a vGPU811 *812 * This function is used to reset vGPU virtual display emulation stuffs813 *814 */815void intel_vgpu_reset_display(struct intel_vgpu *vgpu)816{817 emulate_monitor_status_change(vgpu);818}819