163 lines · c
1/*2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE21 * SOFTWARE.22 *23 * Authors:24 * Kevin Tian <kevin.tian@intel.com>25 *26 * Contributors:27 * Bing Niu <bing.niu@intel.com>28 * Xu Han <xu.han@intel.com>29 * Ping Gao <ping.a.gao@intel.com>30 * Xiaoguang Chen <xiaoguang.chen@intel.com>31 * Yang Liu <yang2.liu@intel.com>32 * Tina Zhang <tina.zhang@intel.com>33 *34 */35 36#ifndef _GVT_FB_DECODER_H_37#define _GVT_FB_DECODER_H_38 39#include <linux/types.h>40 41#include "display/intel_display_limits.h"42 43struct intel_vgpu;44 45#define _PLANE_CTL_FORMAT_SHIFT 2446#define _PLANE_CTL_TILED_SHIFT 1047#define _PIPE_V_SRCSZ_SHIFT 048#define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT)49#define _PIPE_H_SRCSZ_SHIFT 1650#define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT)51 52#define _PRI_PLANE_FMT_SHIFT 2653#define _PRI_PLANE_STRIDE_MASK (0x3ff << 6)54#define _PRI_PLANE_X_OFF_SHIFT 055#define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT)56#define _PRI_PLANE_Y_OFF_SHIFT 1657#define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT)58 59#define _CURSOR_MODE 0x3f60#define _CURSOR_ALPHA_FORCE_SHIFT 861#define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT)62#define _CURSOR_ALPHA_PLANE_SHIFT 1063#define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT)64#define _CURSOR_POS_X_SHIFT 065#define _CURSOR_POS_X_MASK (0x1fff << _CURSOR_POS_X_SHIFT)66#define _CURSOR_SIGN_X_SHIFT 1567#define _CURSOR_SIGN_X_MASK (1 << _CURSOR_SIGN_X_SHIFT)68#define _CURSOR_POS_Y_SHIFT 1669#define _CURSOR_POS_Y_MASK (0xfff << _CURSOR_POS_Y_SHIFT)70#define _CURSOR_SIGN_Y_SHIFT 3171#define _CURSOR_SIGN_Y_MASK (1 << _CURSOR_SIGN_Y_SHIFT)72 73#define _SPRITE_FMT_SHIFT 2574#define _SPRITE_COLOR_ORDER_SHIFT 2075#define _SPRITE_YUV_ORDER_SHIFT 1676#define _SPRITE_STRIDE_SHIFT 677#define _SPRITE_STRIDE_MASK (0x1ff << _SPRITE_STRIDE_SHIFT)78#define _SPRITE_SIZE_WIDTH_SHIFT 079#define _SPRITE_SIZE_HEIGHT_SHIFT 1680#define _SPRITE_SIZE_WIDTH_MASK (0x1fff << _SPRITE_SIZE_WIDTH_SHIFT)81#define _SPRITE_SIZE_HEIGHT_MASK (0xfff << _SPRITE_SIZE_HEIGHT_SHIFT)82#define _SPRITE_POS_X_SHIFT 083#define _SPRITE_POS_Y_SHIFT 1684#define _SPRITE_POS_X_MASK (0x1fff << _SPRITE_POS_X_SHIFT)85#define _SPRITE_POS_Y_MASK (0xfff << _SPRITE_POS_Y_SHIFT)86#define _SPRITE_OFFSET_START_X_SHIFT 087#define _SPRITE_OFFSET_START_Y_SHIFT 1688#define _SPRITE_OFFSET_START_X_MASK (0x1fff << _SPRITE_OFFSET_START_X_SHIFT)89#define _SPRITE_OFFSET_START_Y_MASK (0xfff << _SPRITE_OFFSET_START_Y_SHIFT)90 91enum GVT_FB_EVENT {92 FB_MODE_SET_START = 1,93 FB_MODE_SET_END,94 FB_DISPLAY_FLIP,95};96 97enum DDI_PORT {98 DDI_PORT_NONE = 0,99 DDI_PORT_B = 1,100 DDI_PORT_C = 2,101 DDI_PORT_D = 3,102 DDI_PORT_E = 4103};104 105/* color space conversion and gamma correction are not included */106struct intel_vgpu_primary_plane_format {107 u8 enabled; /* plane is enabled */108 u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */109 u8 bpp; /* bits per pixel */110 u32 hw_format; /* format field in the PRI_CTL register */111 u32 drm_format; /* format in DRM definition */112 u32 base; /* framebuffer base in graphics memory */113 u64 base_gpa;114 u32 x_offset; /* in pixels */115 u32 y_offset; /* in lines */116 u32 width; /* in pixels */117 u32 height; /* in lines */118 u32 stride; /* in bytes */119};120 121struct intel_vgpu_sprite_plane_format {122 u8 enabled; /* plane is enabled */123 u8 tiled; /* X-tiled */124 u8 bpp; /* bits per pixel */125 u32 hw_format; /* format field in the SPR_CTL register */126 u32 drm_format; /* format in DRM definition */127 u32 base; /* sprite base in graphics memory */128 u64 base_gpa;129 u32 x_pos; /* in pixels */130 u32 y_pos; /* in lines */131 u32 x_offset; /* in pixels */132 u32 y_offset; /* in lines */133 u32 width; /* in pixels */134 u32 height; /* in lines */135 u32 stride; /* in bytes */136};137 138struct intel_vgpu_cursor_plane_format {139 u8 enabled;140 u8 mode; /* cursor mode select */141 u8 bpp; /* bits per pixel */142 u32 drm_format; /* format in DRM definition */143 u32 base; /* cursor base in graphics memory */144 u64 base_gpa;145 u32 x_pos; /* in pixels */146 u32 y_pos; /* in lines */147 u8 x_sign; /* X Position Sign */148 u8 y_sign; /* Y Position Sign */149 u32 width; /* in pixels */150 u32 height; /* in lines */151 u32 x_hot; /* in pixels */152 u32 y_hot; /* in pixels */153};154 155int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,156 struct intel_vgpu_primary_plane_format *plane);157int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,158 struct intel_vgpu_cursor_plane_format *plane);159int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,160 struct intel_vgpu_sprite_plane_format *plane);161 162#endif163