512 lines · c
1/*2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE21 * SOFTWARE.22 *23 * Authors:24 * Eddie Dong <eddie.dong@intel.com>25 * Kevin Tian <kevin.tian@intel.com>26 *27 * Contributors:28 * Ping Gao <ping.a.gao@intel.com>29 * Zhi Wang <zhi.a.wang@intel.com>30 * Bing Niu <bing.niu@intel.com>31 *32 */33 34#include "i915_drv.h"35#include "gvt.h"36#include "i915_pvinfo.h"37#include <linux/vmalloc.h>38 39void populate_pvinfo_page(struct intel_vgpu *vgpu)40{41 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;42 /* setup the ballooning information */43 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;44 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;45 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;46 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;47 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;48 49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;51 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;52 53 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =54 vgpu_aperture_gmadr_base(vgpu);55 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =56 vgpu_aperture_sz(vgpu);57 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =58 vgpu_hidden_gmadr_base(vgpu);59 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =60 vgpu_hidden_sz(vgpu);61 62 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);63 64 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;65 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;66 67 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);68 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",69 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));70 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",71 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));72 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));73 74 drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE);75}76 77/*78 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU79 * generation type (e.g V4 as BDW server, V5 as SKL server).80 *81 * Depening on the physical SKU resource, we might see vGPU types like82 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of83 * vGPU on same physical GPU depending on available resource. Each vGPU84 * type will have a different number of avail_instance to indicate how85 * many vGPU instance can be created for this type.86 */87#define VGPU_MAX_WEIGHT 1688#define VGPU_WEIGHT(vgpu_num) \89 (VGPU_MAX_WEIGHT / (vgpu_num))90 91static const struct intel_vgpu_config intel_vgpu_configs[] = {92 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },93 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },94 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },95 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },96};97 98/**99 * intel_gvt_init_vgpu_types - initialize vGPU type list100 * @gvt : GVT device101 *102 * Initialize vGPU type list based on available resource.103 *104 */105int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)106{107 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;108 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;109 unsigned int num_types = ARRAY_SIZE(intel_vgpu_configs);110 unsigned int i;111 112 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type),113 GFP_KERNEL);114 if (!gvt->types)115 return -ENOMEM;116 117 gvt->mdev_types = kcalloc(num_types, sizeof(*gvt->mdev_types),118 GFP_KERNEL);119 if (!gvt->mdev_types)120 goto out_free_types;121 122 for (i = 0; i < num_types; ++i) {123 const struct intel_vgpu_config *conf = &intel_vgpu_configs[i];124 125 if (low_avail / conf->low_mm == 0)126 break;127 if (conf->weight < 1 || conf->weight > VGPU_MAX_WEIGHT)128 goto out_free_mdev_types;129 130 sprintf(gvt->types[i].name, "GVTg_V%u_%s",131 GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name);132 gvt->types[i].conf = conf;133 134 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",135 i, gvt->types[i].name,136 min(low_avail / conf->low_mm,137 high_avail / conf->high_mm),138 conf->low_mm, conf->high_mm, conf->fence,139 conf->weight, vgpu_edid_str(conf->edid));140 141 gvt->mdev_types[i] = &gvt->types[i].type;142 gvt->mdev_types[i]->sysfs_name = gvt->types[i].name;143 }144 145 gvt->num_types = i;146 return 0;147 148out_free_mdev_types:149 kfree(gvt->mdev_types);150out_free_types:151 kfree(gvt->types);152 return -EINVAL;153}154 155void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)156{157 kfree(gvt->mdev_types);158 kfree(gvt->types);159}160 161/**162 * intel_gvt_activate_vgpu - activate a virtual GPU163 * @vgpu: virtual GPU164 *165 * This function is called when user wants to activate a virtual GPU.166 *167 */168void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)169{170 set_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);171}172 173/**174 * intel_gvt_deactivate_vgpu - deactivate a virtual GPU175 * @vgpu: virtual GPU176 *177 * This function is called when user wants to deactivate a virtual GPU.178 * The virtual GPU will be stopped.179 *180 */181void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)182{183 mutex_lock(&vgpu->vgpu_lock);184 185 clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);186 187 if (atomic_read(&vgpu->submission.running_workload_num)) {188 mutex_unlock(&vgpu->vgpu_lock);189 intel_gvt_wait_vgpu_idle(vgpu);190 mutex_lock(&vgpu->vgpu_lock);191 }192 193 intel_vgpu_stop_schedule(vgpu);194 195 mutex_unlock(&vgpu->vgpu_lock);196}197 198/**199 * intel_gvt_release_vgpu - release a virtual GPU200 * @vgpu: virtual GPU201 *202 * This function is called when user wants to release a virtual GPU.203 * The virtual GPU will be stopped and all runtime information will be204 * destroyed.205 *206 */207void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)208{209 intel_gvt_deactivate_vgpu(vgpu);210 211 mutex_lock(&vgpu->vgpu_lock);212 vgpu->d3_entered = false;213 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);214 intel_vgpu_dmabuf_cleanup(vgpu);215 mutex_unlock(&vgpu->vgpu_lock);216}217 218/**219 * intel_gvt_destroy_vgpu - destroy a virtual GPU220 * @vgpu: virtual GPU221 *222 * This function is called when user wants to destroy a virtual GPU.223 *224 */225void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)226{227 struct intel_gvt *gvt = vgpu->gvt;228 struct drm_i915_private *i915 = gvt->gt->i915;229 230 drm_WARN(&i915->drm, test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status),231 "vGPU is still active!\n");232 233 /*234 * remove idr first so later clean can judge if need to stop235 * service if no active vgpu.236 */237 mutex_lock(&gvt->lock);238 idr_remove(&gvt->vgpu_idr, vgpu->id);239 mutex_unlock(&gvt->lock);240 241 mutex_lock(&vgpu->vgpu_lock);242 intel_gvt_debugfs_remove_vgpu(vgpu);243 intel_vgpu_clean_sched_policy(vgpu);244 intel_vgpu_clean_submission(vgpu);245 intel_vgpu_clean_display(vgpu);246 intel_vgpu_clean_opregion(vgpu);247 intel_vgpu_reset_ggtt(vgpu, true);248 intel_vgpu_clean_gtt(vgpu);249 intel_vgpu_detach_regions(vgpu);250 intel_vgpu_free_resource(vgpu);251 intel_vgpu_clean_mmio(vgpu);252 intel_vgpu_dmabuf_cleanup(vgpu);253 mutex_unlock(&vgpu->vgpu_lock);254}255 256#define IDLE_VGPU_IDR 0257 258/**259 * intel_gvt_create_idle_vgpu - create an idle virtual GPU260 * @gvt: GVT device261 *262 * This function is called when user wants to create an idle virtual GPU.263 *264 * Returns:265 * pointer to intel_vgpu, error pointer if failed.266 */267struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)268{269 struct intel_vgpu *vgpu;270 enum intel_engine_id i;271 int ret;272 273 vgpu = vzalloc(sizeof(*vgpu));274 if (!vgpu)275 return ERR_PTR(-ENOMEM);276 277 vgpu->id = IDLE_VGPU_IDR;278 vgpu->gvt = gvt;279 mutex_init(&vgpu->vgpu_lock);280 281 for (i = 0; i < I915_NUM_ENGINES; i++)282 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);283 284 ret = intel_vgpu_init_sched_policy(vgpu);285 if (ret)286 goto out_free_vgpu;287 288 clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);289 return vgpu;290 291out_free_vgpu:292 vfree(vgpu);293 return ERR_PTR(ret);294}295 296/**297 * intel_gvt_destroy_idle_vgpu - destroy an idle virtual GPU298 * @vgpu: virtual GPU299 *300 * This function is called when user wants to destroy an idle virtual GPU.301 *302 */303void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)304{305 mutex_lock(&vgpu->vgpu_lock);306 intel_vgpu_clean_sched_policy(vgpu);307 mutex_unlock(&vgpu->vgpu_lock);308 309 vfree(vgpu);310}311 312int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,313 const struct intel_vgpu_config *conf)314{315 struct intel_gvt *gvt = vgpu->gvt;316 struct drm_i915_private *dev_priv = gvt->gt->i915;317 int ret;318 319 gvt_dbg_core("low %u MB high %u MB fence %u\n",320 BYTES_TO_MB(conf->low_mm), BYTES_TO_MB(conf->high_mm),321 conf->fence);322 323 mutex_lock(&gvt->lock);324 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,325 GFP_KERNEL);326 if (ret < 0)327 goto out_unlock;328 329 vgpu->id = ret;330 vgpu->sched_ctl.weight = conf->weight;331 mutex_init(&vgpu->vgpu_lock);332 mutex_init(&vgpu->dmabuf_lock);333 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);334 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);335 idr_init_base(&vgpu->object_idr, 1);336 intel_vgpu_init_cfg_space(vgpu, 1);337 vgpu->d3_entered = false;338 339 ret = intel_vgpu_init_mmio(vgpu);340 if (ret)341 goto out_clean_idr;342 343 ret = intel_vgpu_alloc_resource(vgpu, conf);344 if (ret)345 goto out_clean_vgpu_mmio;346 347 populate_pvinfo_page(vgpu);348 349 ret = intel_vgpu_init_gtt(vgpu);350 if (ret)351 goto out_clean_vgpu_resource;352 353 ret = intel_vgpu_init_opregion(vgpu);354 if (ret)355 goto out_clean_gtt;356 357 ret = intel_vgpu_init_display(vgpu, conf->edid);358 if (ret)359 goto out_clean_opregion;360 361 ret = intel_vgpu_setup_submission(vgpu);362 if (ret)363 goto out_clean_display;364 365 ret = intel_vgpu_init_sched_policy(vgpu);366 if (ret)367 goto out_clean_submission;368 369 intel_gvt_debugfs_add_vgpu(vgpu);370 371 ret = intel_gvt_set_opregion(vgpu);372 if (ret)373 goto out_clean_sched_policy;374 375 if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))376 ret = intel_gvt_set_edid(vgpu, PORT_B);377 else378 ret = intel_gvt_set_edid(vgpu, PORT_D);379 if (ret)380 goto out_clean_sched_policy;381 382 intel_gvt_update_reg_whitelist(vgpu);383 mutex_unlock(&gvt->lock);384 return 0;385 386out_clean_sched_policy:387 intel_vgpu_clean_sched_policy(vgpu);388out_clean_submission:389 intel_vgpu_clean_submission(vgpu);390out_clean_display:391 intel_vgpu_clean_display(vgpu);392out_clean_opregion:393 intel_vgpu_clean_opregion(vgpu);394out_clean_gtt:395 intel_vgpu_clean_gtt(vgpu);396out_clean_vgpu_resource:397 intel_vgpu_free_resource(vgpu);398out_clean_vgpu_mmio:399 intel_vgpu_clean_mmio(vgpu);400out_clean_idr:401 idr_remove(&gvt->vgpu_idr, vgpu->id);402out_unlock:403 mutex_unlock(&gvt->lock);404 return ret;405}406 407/**408 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset409 * @vgpu: virtual GPU410 * @dmlr: vGPU Device Model Level Reset or GT Reset411 * @engine_mask: engines to reset for GT reset412 *413 * This function is called when user wants to reset a virtual GPU through414 * device model reset or GT reset. The caller should hold the vgpu lock.415 *416 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset417 * the whole vGPU to default state as when it is created. This vGPU function418 * is required both for functionary and security concerns.The ultimate goal419 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we420 * assign a vGPU to a virtual machine we must isse such reset first.421 *422 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines423 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.424 * Unlike the FLR, GT reset only reset particular resource of a vGPU per425 * the reset request. Guest driver can issue a GT reset by programming the426 * virtual GDRST register to reset specific virtual GPU engine or all427 * engines.428 *429 * The parameter dev_level is to identify if we will do DMLR or GT reset.430 * The parameter engine_mask is to specific the engines that need to be431 * resetted. If value ALL_ENGINES is given for engine_mask, it means432 * the caller requests a full GT reset that we will reset all virtual433 * GPU engines. For FLR, engine_mask is ignored.434 */435void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,436 intel_engine_mask_t engine_mask)437{438 struct intel_gvt *gvt = vgpu->gvt;439 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;440 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;441 442 gvt_dbg_core("------------------------------------------\n");443 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",444 vgpu->id, dmlr, engine_mask);445 446 vgpu->resetting_eng = resetting_eng;447 448 intel_vgpu_stop_schedule(vgpu);449 /*450 * The current_vgpu will set to NULL after stopping the451 * scheduler when the reset is triggered by current vgpu.452 */453 if (scheduler->current_vgpu == NULL) {454 mutex_unlock(&vgpu->vgpu_lock);455 intel_gvt_wait_vgpu_idle(vgpu);456 mutex_lock(&vgpu->vgpu_lock);457 }458 459 intel_vgpu_reset_submission(vgpu, resetting_eng);460 /* full GPU reset or device model level reset */461 if (engine_mask == ALL_ENGINES || dmlr) {462 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);463 if (engine_mask == ALL_ENGINES)464 intel_vgpu_invalidate_ppgtt(vgpu);465 /*fence will not be reset during virtual reset */466 if (dmlr) {467 if(!vgpu->d3_entered) {468 intel_vgpu_invalidate_ppgtt(vgpu);469 intel_vgpu_destroy_all_ppgtt_mm(vgpu);470 }471 intel_vgpu_reset_ggtt(vgpu, true);472 intel_vgpu_reset_resource(vgpu);473 }474 475 intel_vgpu_reset_mmio(vgpu, dmlr);476 populate_pvinfo_page(vgpu);477 478 if (dmlr) {479 intel_vgpu_reset_display(vgpu);480 intel_vgpu_reset_cfg_space(vgpu);481 /* only reset the failsafe mode when dmlr reset */482 vgpu->failsafe = false;483 /*484 * PCI_D0 is set before dmlr, so reset d3_entered here485 * after done using.486 */487 if(vgpu->d3_entered)488 vgpu->d3_entered = false;489 else490 vgpu->pv_notified = false;491 }492 }493 494 vgpu->resetting_eng = 0;495 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);496 gvt_dbg_core("------------------------------------------\n");497}498 499/**500 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)501 * @vgpu: virtual GPU502 *503 * This function is called when user wants to reset a virtual GPU.504 *505 */506void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)507{508 mutex_lock(&vgpu->vgpu_lock);509 intel_gvt_reset_vgpu_locked(vgpu, true, 0);510 mutex_unlock(&vgpu->vgpu_lock);511}512